[mirror_ubuntu-bionic-kernel.git] / Documentation / devicetree / bindings / usb / rockchip,dwc3.txt

Rockchip SuperSpeed DWC3 USB SoC controller

Required properties:
- compatible:	should contain "rockchip,rk3399-dwc3" for rk3399 SoC
- clocks:	A list of phandle + clock-specifier pairs for the
		clocks listed in clock-names
- clock-names:	Should contain the following:
  "ref_clk"	Controller reference clk, have to be 24 MHz
  "suspend_clk"	Controller suspend clk, have to be 24 MHz or 32 KHz
  "bus_clk"	Master/Core clock, have to be >= 62.5 MHz for SS
		operation and >= 30MHz for HS operation
  "grf_clk"	Controller grf clk

Required child node:
A child node must exist to represent the core DWC3 IP block. The name of
the node is not important. The content of the node is defined in dwc3.txt.

Phy documentation is provided in the following places:
Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt

Example device nodes:

	usbdrd3_0: usb@fe800000 {
		compatible = "rockchip,rk3399-dwc3";
		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
		clock-names = "ref_clk", "suspend_clk",
			      "bus_clk", "grf_clk";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		usbdrd_dwc3_0: dwc3@fe800000 {
			compatible = "snps,dwc3";
			reg = <0x0 0xfe800000 0x0 0x100000>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "otg";
		};
	};

	usbdrd3_1: usb@fe900000 {
		compatible = "rockchip,rk3399-dwc3";
		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
		clock-names = "ref_clk", "suspend_clk",
			      "bus_clk", "grf_clk";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		usbdrd_dwc3_1: dwc3@fe900000 {
			compatible = "snps,dwc3";
			reg = <0x0 0xfe900000 0x0 0x100000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "otg";
		};
	};
Commit	Line	Data
76bf85cc WW	1	Rockchip SuperSpeed DWC3 USB SoC controller
	2
	3	Required properties:
	4	- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
	5	- clocks: A list of phandle + clock-specifier pairs for the
	6	clocks listed in clock-names
	7	- clock-names: Should contain the following:
	8	"ref_clk" Controller reference clk, have to be 24 MHz
	9	"suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
	10	"bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
	11	operation and >= 30MHz for HS operation
	12	"grf_clk" Controller grf clk
	13
	14	Required child node:
	15	A child node must exist to represent the core DWC3 IP block. The name of
	16	the node is not important. The content of the node is defined in dwc3.txt.
	17
	18	Phy documentation is provided in the following places:
	19	Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt
	20
	21	Example device nodes:
	22
	23	usbdrd3_0: usb@fe800000 {
	24	compatible = "rockchip,rk3399-dwc3";
	25	clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
	26	<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
	27	clock-names = "ref_clk", "suspend_clk",
	28	"bus_clk", "grf_clk";
	29	#address-cells = <2>;
	30	#size-cells = <2>;
	31	ranges;
76bf85cc WW	32	usbdrd_dwc3_0: dwc3@fe800000 {
	33	compatible = "snps,dwc3";
	34	reg = <0x0 0xfe800000 0x0 0x100000>;
	35	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	36	dr_mode = "otg";
76bf85cc WW	37	};
	38	};
	39
	40	usbdrd3_1: usb@fe900000 {
	41	compatible = "rockchip,rk3399-dwc3";
	42	clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
	43	<&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
	44	clock-names = "ref_clk", "suspend_clk",
	45	"bus_clk", "grf_clk";
	46	#address-cells = <2>;
	47	#size-cells = <2>;
	48	ranges;
76bf85cc WW	49	usbdrd_dwc3_1: dwc3@fe900000 {
	50	compatible = "snps,dwc3";
	51	reg = <0x0 0xfe900000 0x0 0x100000>;
	52	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	53	dr_mode = "otg";
76bf85cc WW	54	};
76bf85cc WW	55	};