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Commit | Line | Data |
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f2e87696 AP |
1 | ARM AMBA Primecell SP805 Watchdog |
2 | ||
3 | Required properties: | |
4 | - compatible: Should be "arm,sp805" & "arm,primecell" | |
5 | - reg: Should contain location and length for watchdog timer register. | |
6 | - interrupts: Should contain the list of watchdog timer interrupts. | |
7 | - clocks: clocks driving the watchdog timer hardware. This list should be 2 | |
8 | clocks. With 2 clocks, the order is wdogclk clock, apb_pclk. | |
9 | ||
10 | Example: | |
11 | watchdog@66090000 { | |
12 | compatible = "arm,sp805", "arm,primecell"; | |
13 | reg = <0x66090000 0x1000>; | |
14 | interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; | |
15 | clocks = <&apb_pclk>,<&apb_pclk>; | |
16 | clock-names = "wdogclk", "apb_pclk"; | |
17 | }; |