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Commit | Line | Data |
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22554020 JN |
1 | =========================== |
2 | drm/i915 Intel GFX Driver | |
3 | =========================== | |
ca00c2b9 JN |
4 | |
5 | The drm/i915 driver supports all (with the exception of some very early | |
6 | models) integrated GFX chipsets with both Intel display and rendering | |
7 | blocks. This excludes a set of SoC platforms with an SGX rendering unit, | |
8 | those have basic support through the gma500 drm driver. | |
9 | ||
10 | Core Driver Infrastructure | |
22554020 | 11 | ========================== |
ca00c2b9 JN |
12 | |
13 | This section covers core driver infrastructure used by both the display | |
14 | and the GEM parts of the driver. | |
15 | ||
16 | Runtime Power Management | |
22554020 | 17 | ------------------------ |
ca00c2b9 JN |
18 | |
19 | .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c | |
20 | :doc: runtime pm | |
21 | ||
22 | .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c | |
23 | :internal: | |
24 | ||
25 | .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c | |
26 | :internal: | |
27 | ||
28 | Interrupt Handling | |
22554020 | 29 | ------------------ |
ca00c2b9 JN |
30 | |
31 | .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c | |
32 | :doc: interrupt handling | |
33 | ||
34 | .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c | |
35 | :functions: intel_irq_init intel_irq_init_hw intel_hpd_init | |
36 | ||
37 | .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c | |
38 | :functions: intel_runtime_pm_disable_interrupts | |
39 | ||
40 | .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c | |
41 | :functions: intel_runtime_pm_enable_interrupts | |
42 | ||
43 | Intel GVT-g Guest Support(vGPU) | |
22554020 | 44 | ------------------------------- |
ca00c2b9 JN |
45 | |
46 | .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c | |
47 | :doc: Intel GVT-g guest support | |
48 | ||
49 | .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c | |
50 | :internal: | |
51 | ||
22681c7b ZW |
52 | Intel GVT-g Host Support(vGPU device model) |
53 | ------------------------------------------- | |
54 | ||
55 | .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c | |
56 | :doc: Intel GVT-g host support | |
57 | ||
58 | .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c | |
59 | :internal: | |
60 | ||
7d3c425f OM |
61 | Workarounds |
62 | ----------- | |
63 | ||
bcc8737d | 64 | .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c |
7d3c425f OM |
65 | :doc: Hardware workarounds |
66 | ||
ca00c2b9 | 67 | Display Hardware Handling |
22554020 | 68 | ========================= |
ca00c2b9 JN |
69 | |
70 | This section covers everything related to the display hardware including | |
71 | the mode setting infrastructure, plane, sprite and cursor handling and | |
72 | display, output probing and related topics. | |
73 | ||
74 | Mode Setting Infrastructure | |
22554020 | 75 | --------------------------- |
ca00c2b9 JN |
76 | |
77 | The i915 driver is thus far the only DRM driver which doesn't use the | |
78 | common DRM helper code to implement mode setting sequences. Thus it has | |
79 | its own tailor-made infrastructure for executing a display configuration | |
80 | change. | |
81 | ||
82 | Frontbuffer Tracking | |
22554020 | 83 | -------------------- |
ca00c2b9 | 84 | |
6800d9a5 | 85 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c |
ca00c2b9 JN |
86 | :doc: frontbuffer tracking |
87 | ||
6800d9a5 | 88 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h |
5d723d7a CW |
89 | :internal: |
90 | ||
6800d9a5 | 91 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c |
ca00c2b9 JN |
92 | :internal: |
93 | ||
ca00c2b9 | 94 | Display FIFO Underrun Reporting |
22554020 | 95 | ------------------------------- |
ca00c2b9 | 96 | |
6800d9a5 | 97 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c |
ca00c2b9 JN |
98 | :doc: fifo underrun handling |
99 | ||
6800d9a5 | 100 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c |
ca00c2b9 JN |
101 | :internal: |
102 | ||
103 | Plane Configuration | |
22554020 | 104 | ------------------- |
ca00c2b9 JN |
105 | |
106 | This section covers plane configuration and composition with the primary | |
107 | plane, sprites, cursors and overlays. This includes the infrastructure | |
108 | to do atomic vsync'ed updates of all this state and also tightly coupled | |
109 | topics like watermark setup and computation, framebuffer compression and | |
110 | panel self refresh. | |
111 | ||
112 | Atomic Plane Helpers | |
22554020 | 113 | -------------------- |
ca00c2b9 | 114 | |
6800d9a5 | 115 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c |
ca00c2b9 JN |
116 | :doc: atomic plane helpers |
117 | ||
6800d9a5 | 118 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c |
ca00c2b9 JN |
119 | :internal: |
120 | ||
121 | Output Probing | |
22554020 | 122 | -------------- |
ca00c2b9 JN |
123 | |
124 | This section covers output probing and related infrastructure like the | |
125 | hotplug interrupt storm detection and mitigation code. Note that the | |
126 | i915 driver still uses most of the common DRM helper code for output | |
127 | probing, so those sections fully apply. | |
128 | ||
129 | Hotplug | |
22554020 | 130 | ------- |
ca00c2b9 | 131 | |
6800d9a5 | 132 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c |
ca00c2b9 JN |
133 | :doc: Hotplug |
134 | ||
6800d9a5 | 135 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c |
ca00c2b9 JN |
136 | :internal: |
137 | ||
138 | High Definition Audio | |
22554020 | 139 | --------------------- |
ca00c2b9 | 140 | |
6800d9a5 | 141 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c |
ca00c2b9 JN |
142 | :doc: High Definition Audio over HDMI and Display Port |
143 | ||
6800d9a5 | 144 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c |
ca00c2b9 JN |
145 | :internal: |
146 | ||
147 | .. kernel-doc:: include/drm/i915_component.h | |
148 | :internal: | |
149 | ||
eacc8daf TI |
150 | Intel HDMI LPE Audio Support |
151 | ---------------------------- | |
152 | ||
6800d9a5 | 153 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c |
eacc8daf TI |
154 | :doc: LPE Audio integration for HDMI or DP playback |
155 | ||
6800d9a5 | 156 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c |
eacc8daf TI |
157 | :internal: |
158 | ||
ca00c2b9 | 159 | Panel Self Refresh PSR (PSR/SRD) |
22554020 | 160 | -------------------------------- |
ca00c2b9 | 161 | |
6800d9a5 | 162 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c |
ca00c2b9 JN |
163 | :doc: Panel Self Refresh (PSR/SRD) |
164 | ||
6800d9a5 | 165 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c |
ca00c2b9 JN |
166 | :internal: |
167 | ||
168 | Frame Buffer Compression (FBC) | |
22554020 | 169 | ------------------------------ |
ca00c2b9 | 170 | |
6800d9a5 | 171 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c |
ca00c2b9 JN |
172 | :doc: Frame Buffer Compression (FBC) |
173 | ||
6800d9a5 | 174 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c |
ca00c2b9 JN |
175 | :internal: |
176 | ||
177 | Display Refresh Rate Switching (DRRS) | |
22554020 | 178 | ------------------------------------- |
ca00c2b9 | 179 | |
6800d9a5 | 180 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c |
ca00c2b9 JN |
181 | :doc: Display Refresh Rate Switching (DRRS) |
182 | ||
6800d9a5 | 183 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c |
ca00c2b9 JN |
184 | :functions: intel_dp_set_drrs_state |
185 | ||
6800d9a5 | 186 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c |
ca00c2b9 JN |
187 | :functions: intel_edp_drrs_enable |
188 | ||
6800d9a5 | 189 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c |
ca00c2b9 JN |
190 | :functions: intel_edp_drrs_disable |
191 | ||
6800d9a5 | 192 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c |
ca00c2b9 JN |
193 | :functions: intel_edp_drrs_invalidate |
194 | ||
6800d9a5 | 195 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c |
ca00c2b9 JN |
196 | :functions: intel_edp_drrs_flush |
197 | ||
6800d9a5 | 198 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c |
ca00c2b9 JN |
199 | :functions: intel_dp_drrs_init |
200 | ||
201 | DPIO | |
22554020 | 202 | ---- |
ca00c2b9 | 203 | |
6800d9a5 | 204 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c |
ca00c2b9 JN |
205 | :doc: DPIO |
206 | ||
207 | CSR firmware support for DMC | |
22554020 | 208 | ---------------------------- |
ca00c2b9 | 209 | |
e66ae6ca | 210 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c |
ca00c2b9 JN |
211 | :doc: csr support for dmc |
212 | ||
e66ae6ca | 213 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c |
ca00c2b9 JN |
214 | :internal: |
215 | ||
216 | Video BIOS Table (VBT) | |
22554020 | 217 | ---------------------- |
ca00c2b9 | 218 | |
6800d9a5 | 219 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c |
ca00c2b9 JN |
220 | :doc: Video BIOS Table (VBT) |
221 | ||
6800d9a5 | 222 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c |
ca00c2b9 JN |
223 | :internal: |
224 | ||
6800d9a5 | 225 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h |
ca00c2b9 JN |
226 | :internal: |
227 | ||
7ff89ca2 VS |
228 | Display clocks |
229 | -------------- | |
230 | ||
6800d9a5 | 231 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c |
7ff89ca2 VS |
232 | :doc: CDCLK / RAWCLK |
233 | ||
6800d9a5 | 234 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c |
7ff89ca2 VS |
235 | :internal: |
236 | ||
294591cf ACO |
237 | Display PLLs |
238 | ------------ | |
239 | ||
6800d9a5 | 240 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c |
294591cf ACO |
241 | :doc: Display PLLs |
242 | ||
6800d9a5 | 243 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c |
294591cf ACO |
244 | :internal: |
245 | ||
6800d9a5 | 246 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h |
294591cf ACO |
247 | :internal: |
248 | ||
5dd85e72 AM |
249 | Display State Buffer |
250 | -------------------- | |
251 | ||
252 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c | |
253 | :doc: DSB | |
254 | ||
255 | .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c | |
256 | :internal: | |
257 | ||
ca00c2b9 | 258 | Memory Management and Command Submission |
22554020 | 259 | ======================================== |
ca00c2b9 JN |
260 | |
261 | This sections covers all things related to the GEM implementation in the | |
262 | i915 driver. | |
263 | ||
fd5ff5f6 KR |
264 | Intel GPU Basics |
265 | ---------------- | |
266 | ||
267 | An Intel GPU has multiple engines. There are several engine types. | |
268 | ||
269 | - RCS engine is for rendering 3D and performing compute, this is named | |
270 | `I915_EXEC_RENDER` in user space. | |
271 | - BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user | |
272 | space. | |
273 | - VCS is a video encode and decode engine, this is named `I915_EXEC_BSD` | |
274 | in user space | |
275 | - VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user | |
276 | space. | |
277 | - The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine; | |
278 | instead it is to be used by user space to specify a default rendering | |
279 | engine (for 3D) that may or may not be the same as RCS. | |
280 | ||
281 | The Intel GPU family is a family of integrated GPU's using Unified | |
282 | Memory Access. For having the GPU "do work", user space will feed the | |
283 | GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` | |
284 | or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will | |
285 | instruct the GPU to perform work (for example rendering) and that work | |
286 | needs memory from which to read and memory to which to write. All memory | |
287 | is encapsulated within GEM buffer objects (usually created with the ioctl | |
288 | `DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU | |
289 | to create will also list all GEM buffer objects that the batchbuffer reads | |
290 | and/or writes. For implementation details of memory management see | |
291 | `GEM BO Management Implementation Details`_. | |
292 | ||
293 | The i915 driver allows user space to create a context via the ioctl | |
294 | `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit | |
295 | integer. Such a context should be viewed by user-space as -loosely- | |
296 | analogous to the idea of a CPU process of an operating system. The i915 | |
297 | driver guarantees that commands issued to a fixed context are to be | |
298 | executed so that writes of a previously issued command are seen by | |
299 | reads of following commands. Actions issued between different contexts | |
300 | (even if from the same file descriptor) are NOT given that guarantee | |
301 | and the only way to synchronize across contexts (even from the same | |
302 | file descriptor) is through the use of fences. At least as far back as | |
303 | Gen4, also have that a context carries with it a GPU HW context; | |
304 | the HW context is essentially (most of atleast) the state of a GPU. | |
305 | In addition to the ordering guarantees, the kernel will restore GPU | |
306 | state via HW context when commands are issued to a context, this saves | |
307 | user space the need to restore (most of atleast) the GPU state at the | |
308 | start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer | |
309 | work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) | |
310 | to identify what context to use with the command. | |
311 | ||
312 | The GPU has its own memory management and address space. The kernel | |
313 | driver maintains the memory translation table for the GPU. For older | |
314 | GPUs (i.e. those before Gen8), there is a single global such translation | |
315 | table, a global Graphics Translation Table (GTT). For newer generation | |
316 | GPUs each context has its own translation table, called Per-Process | |
317 | Graphics Translation Table (PPGTT). Of important note, is that although | |
318 | PPGTT is named per-process it is actually per context. When user space | |
319 | submits a batchbuffer, the kernel walks the list of GEM buffer objects | |
320 | used by the batchbuffer and guarantees that not only is the memory of | |
321 | each such GEM buffer object resident but it is also present in the | |
322 | (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, | |
323 | then it is given an address. Two consequences of this are: the kernel | |
324 | needs to edit the batchbuffer submitted to write the correct value of | |
325 | the GPU address when a GEM BO is assigned a GPU address and the kernel | |
326 | might evict a different GEM BO from the (PP)GTT to make address room | |
327 | for another GEM BO. Consequently, the ioctls submitting a batchbuffer | |
328 | for execution also include a list of all locations within buffers that | |
329 | refer to GPU-addresses so that the kernel can edit the buffer correctly. | |
330 | This process is dubbed relocation. | |
331 | ||
ca69a3c6 JL |
332 | Locking Guidelines |
333 | ------------------ | |
334 | ||
335 | .. note:: | |
336 | This is a description of how the locking should be after | |
337 | refactoring is done. Does not necessarily reflect what the locking | |
338 | looks like while WIP. | |
339 | ||
340 | #. All locking rules and interface contracts with cross-driver interfaces | |
341 | (dma-buf, dma_fence) need to be followed. | |
342 | ||
343 | #. No struct_mutex anywhere in the code | |
344 | ||
345 | #. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx | |
346 | is to be hoisted at highest level and passed down within i915_gem_ctx | |
347 | in the call chain | |
348 | ||
349 | #. While holding lru/memory manager (buddy, drm_mm, whatever) locks | |
350 | system memory allocations are not allowed | |
351 | ||
352 | * Enforce this by priming lockdep (with fs_reclaim). If we | |
353 | allocate memory while holding these looks we get a rehash | |
354 | of the shrinker vs. struct_mutex saga, and that would be | |
355 | real bad. | |
356 | ||
357 | #. Do not nest different lru/memory manager locks within each other. | |
358 | Take them in turn to update memory allocations, relying on the object’s | |
359 | dma_resv ww_mutex to serialize against other operations. | |
360 | ||
361 | #. The suggestion for lru/memory managers locks is that they are small | |
362 | enough to be spinlocks. | |
363 | ||
364 | #. All features need to come with exhaustive kernel selftests and/or | |
365 | IGT tests when appropriate | |
366 | ||
367 | #. All LMEM uAPI paths need to be fully restartable (_interruptible() | |
368 | for all locks/waits/sleeps) | |
369 | ||
370 | * Error handling validation through signal injection. | |
371 | Still the best strategy we have for validating GEM uAPI | |
372 | corner cases. | |
373 | Must be excessively used in the IGT, and we need to check | |
374 | that we really have full path coverage of all error cases. | |
375 | ||
376 | * -EDEADLK handling with ww_mutex | |
377 | ||
fd5ff5f6 KR |
378 | GEM BO Management Implementation Details |
379 | ---------------------------------------- | |
380 | ||
83dc7f69 | 381 | .. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h |
fd5ff5f6 KR |
382 | :doc: Virtual Memory Address |
383 | ||
384 | Buffer Object Eviction | |
385 | ---------------------- | |
386 | ||
387 | This section documents the interface functions for evicting buffer | |
388 | objects to make space available in the virtual gpu address spaces. Note | |
389 | that this is mostly orthogonal to shrinking buffer objects caches, which | |
390 | has the goal to make main memory (shared with the gpu through the | |
391 | unified memory architecture) available. | |
392 | ||
393 | .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c | |
394 | :internal: | |
395 | ||
396 | Buffer Object Memory Shrinking | |
397 | ------------------------------ | |
398 | ||
399 | This section documents the interface function for shrinking memory usage | |
400 | of buffer object caches. Shrinking is used to make main memory | |
401 | available. Note that this is mostly orthogonal to evicting buffer | |
402 | objects, which has the goal to make space in gpu virtual address spaces. | |
403 | ||
8a6f43d4 | 404 | .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c |
fd5ff5f6 KR |
405 | :internal: |
406 | ||
ca00c2b9 | 407 | Batchbuffer Parsing |
22554020 | 408 | ------------------- |
ca00c2b9 JN |
409 | |
410 | .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c | |
411 | :doc: batch buffer command parser | |
412 | ||
413 | .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c | |
414 | :internal: | |
415 | ||
4d42db18 KR |
416 | User Batchbuffer Execution |
417 | -------------------------- | |
418 | ||
8a6f43d4 | 419 | .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c |
4d42db18 KR |
420 | :doc: User command execution |
421 | ||
ca00c2b9 | 422 | Logical Rings, Logical Ring Contexts and Execlists |
22554020 | 423 | -------------------------------------------------- |
ca00c2b9 | 424 | |
bcc8737d | 425 | .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c |
ca00c2b9 JN |
426 | :doc: Logical Rings, Logical Ring Contexts and Execlists |
427 | ||
ca00c2b9 | 428 | Global GTT views |
22554020 | 429 | ---------------- |
ca00c2b9 | 430 | |
83dc7f69 | 431 | .. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h |
ca00c2b9 JN |
432 | :doc: Global GTT views |
433 | ||
434 | .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c | |
435 | :internal: | |
436 | ||
437 | GTT Fences and Swizzling | |
22554020 | 438 | ------------------------ |
ca00c2b9 | 439 | |
ba69fb16 | 440 | .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c |
ca00c2b9 JN |
441 | :internal: |
442 | ||
443 | Global GTT Fence Handling | |
22554020 | 444 | ~~~~~~~~~~~~~~~~~~~~~~~~~ |
ca00c2b9 | 445 | |
ba69fb16 | 446 | .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c |
ca00c2b9 JN |
447 | :doc: fence register handling |
448 | ||
449 | Hardware Tiling and Swizzling Details | |
22554020 | 450 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
ca00c2b9 | 451 | |
ba69fb16 | 452 | .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c |
ca00c2b9 JN |
453 | :doc: tiling swizzling details |
454 | ||
455 | Object Tiling IOCTLs | |
22554020 | 456 | -------------------- |
ca00c2b9 | 457 | |
8a6f43d4 | 458 | .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c |
ca00c2b9 JN |
459 | :internal: |
460 | ||
8a6f43d4 | 461 | .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c |
ca00c2b9 JN |
462 | :doc: buffer object tiling |
463 | ||
493065e2 DCS |
464 | Microcontrollers |
465 | ================ | |
466 | ||
467 | Starting from gen9, three microcontrollers are available on the HW: the | |
468 | graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the | |
469 | display microcontroller (DMC). The driver is responsible for loading the | |
470 | firmwares on the microcontrollers; the GuC and HuC firmwares are transferred | |
471 | to WOPCM using the DMA engine, while the DMC firmware is written through MMIO. | |
472 | ||
fbe6f8f2 | 473 | WOPCM |
4072761b | 474 | ----- |
fbe6f8f2 YL |
475 | |
476 | WOPCM Layout | |
4072761b | 477 | ~~~~~~~~~~~~ |
fbe6f8f2 YL |
478 | |
479 | .. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c | |
480 | :doc: WOPCM Layout | |
481 | ||
ca00c2b9 | 482 | GuC |
4072761b | 483 | --- |
ca00c2b9 | 484 | |
218151e9 DCS |
485 | .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c |
486 | :doc: GuC | |
487 | ||
488 | GuC Firmware Layout | |
489 | ~~~~~~~~~~~~~~~~~~~ | |
199ddded | 490 | |
abf30f23 | 491 | .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h |
199ddded MW |
492 | :doc: Firmware Layout |
493 | ||
218151e9 DCS |
494 | GuC Memory Management |
495 | ~~~~~~~~~~~~~~~~~~~~~ | |
496 | ||
497 | .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c | |
498 | :doc: GuC Memory Management | |
499 | .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c | |
500 | :functions: intel_guc_allocate_vma | |
501 | ||
502 | ||
ca00c2b9 | 503 | GuC-specific firmware loader |
4072761b | 504 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
ca00c2b9 | 505 | |
dbbff8c3 | 506 | .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |
ca00c2b9 JN |
507 | :internal: |
508 | ||
509 | GuC-based command submission | |
4072761b | 510 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
ca00c2b9 | 511 | |
dbbff8c3 | 512 | .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c |
ca00c2b9 JN |
513 | :doc: GuC-based command submission |
514 | ||
493065e2 DCS |
515 | HuC |
516 | --- | |
0b23e2a6 DCS |
517 | .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c |
518 | :doc: HuC | |
519 | .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c | |
520 | :functions: intel_huc_auth | |
521 | ||
522 | HuC Memory Management | |
523 | ~~~~~~~~~~~~~~~~~~~~~ | |
524 | ||
525 | .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c | |
526 | :doc: HuC Memory Management | |
527 | ||
528 | HuC Firmware Layout | |
529 | ~~~~~~~~~~~~~~~~~~~ | |
530 | The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ | |
493065e2 DCS |
531 | |
532 | DMC | |
533 | --- | |
534 | See `CSR firmware support for DMC`_ | |
535 | ||
ca00c2b9 | 536 | Tracing |
22554020 | 537 | ======= |
ca00c2b9 JN |
538 | |
539 | This sections covers all things related to the tracepoints implemented | |
540 | in the i915 driver. | |
541 | ||
542 | i915_ppgtt_create and i915_ppgtt_release | |
22554020 | 543 | ---------------------------------------- |
ca00c2b9 JN |
544 | |
545 | .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h | |
546 | :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints | |
547 | ||
548 | i915_context_create and i915_context_free | |
22554020 | 549 | ----------------------------------------- |
ca00c2b9 JN |
550 | |
551 | .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h | |
552 | :doc: i915_context_create and i915_context_free tracepoints | |
553 | ||
16d98b31 RB |
554 | Perf |
555 | ==== | |
556 | ||
557 | Overview | |
558 | -------- | |
559 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
560 | :doc: i915 Perf Overview | |
561 | ||
562 | Comparison with Core Perf | |
563 | ------------------------- | |
564 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
565 | :doc: i915 Perf History and Comparison with Core Perf | |
566 | ||
567 | i915 Driver Entry Points | |
568 | ------------------------ | |
569 | ||
570 | This section covers the entrypoints exported outside of i915_perf.c to | |
571 | integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl. | |
572 | ||
573 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
574 | :functions: i915_perf_init | |
575 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
576 | :functions: i915_perf_fini | |
577 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
578 | :functions: i915_perf_register | |
579 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
580 | :functions: i915_perf_unregister | |
581 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
582 | :functions: i915_perf_open_ioctl | |
583 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
584 | :functions: i915_perf_release | |
f89823c2 LL |
585 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c |
586 | :functions: i915_perf_add_config_ioctl | |
587 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
588 | :functions: i915_perf_remove_config_ioctl | |
16d98b31 RB |
589 | |
590 | i915 Perf Stream | |
591 | ---------------- | |
592 | ||
593 | This section covers the stream-semantics-agnostic structures and functions | |
594 | for representing an i915 perf stream FD and associated file operations. | |
595 | ||
8c638802 | 596 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h |
16d98b31 | 597 | :functions: i915_perf_stream |
8c638802 | 598 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h |
16d98b31 RB |
599 | :functions: i915_perf_stream_ops |
600 | ||
601 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
602 | :functions: read_properties_unlocked | |
603 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
604 | :functions: i915_perf_open_ioctl_locked | |
605 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
606 | :functions: i915_perf_destroy_locked | |
607 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
608 | :functions: i915_perf_read | |
609 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
610 | :functions: i915_perf_ioctl | |
611 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
612 | :functions: i915_perf_enable_locked | |
613 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
614 | :functions: i915_perf_disable_locked | |
615 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
616 | :functions: i915_perf_poll | |
617 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
618 | :functions: i915_perf_poll_locked | |
619 | ||
620 | i915 Perf Observation Architecture Stream | |
621 | ----------------------------------------- | |
622 | ||
8c638802 | 623 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h |
16d98b31 RB |
624 | :functions: i915_oa_ops |
625 | ||
626 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
627 | :functions: i915_oa_stream_init | |
628 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
629 | :functions: i915_oa_read | |
630 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
631 | :functions: i915_oa_stream_enable | |
632 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
633 | :functions: i915_oa_stream_disable | |
634 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
635 | :functions: i915_oa_wait_unlocked | |
636 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
637 | :functions: i915_oa_poll_wait | |
638 | ||
639 | All i915 Perf Internals | |
640 | ----------------------- | |
641 | ||
642 | This section simply includes all currently documented i915 perf internals, in | |
643 | no particular order, but may include some more minor utilities or platform | |
644 | specific details than found in the more high-level sections. | |
645 | ||
646 | .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c | |
647 | :internal: | |
1aa920ea JN |
648 | |
649 | Style | |
650 | ===== | |
651 | ||
652 | The drm/i915 driver codebase has some style rules in addition to (and, in some | |
653 | cases, deviating from) the kernel coding style. | |
654 | ||
655 | Register macro definition style | |
656 | ------------------------------- | |
657 | ||
658 | The style guide for ``i915_reg.h``. | |
659 | ||
660 | .. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h | |
661 | :doc: The i915 register macro definition style guide |