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108b42b4 DH |
1 | ============================ |
2 | LINUX KERNEL MEMORY BARRIERS | |
3 | ============================ | |
4 | ||
5 | By: David Howells <dhowells@redhat.com> | |
90fddabf | 6 | Paul E. McKenney <paulmck@linux.vnet.ibm.com> |
e7720af5 PZ |
7 | Will Deacon <will.deacon@arm.com> |
8 | Peter Zijlstra <peterz@infradead.org> | |
108b42b4 | 9 | |
e7720af5 PZ |
10 | ========== |
11 | DISCLAIMER | |
12 | ========== | |
13 | ||
14 | This document is not a specification; it is intentionally (for the sake of | |
15 | brevity) and unintentionally (due to being human) incomplete. This document is | |
16 | meant as a guide to using the various memory barriers provided by Linux, but | |
17 | in case of any doubt (and there are many) please ask. | |
18 | ||
19 | To repeat, this document is not a specification of what Linux expects from | |
20 | hardware. | |
21 | ||
22 | ======== | |
23 | CONTENTS | |
24 | ======== | |
108b42b4 DH |
25 | |
26 | (*) Abstract memory access model. | |
27 | ||
28 | - Device operations. | |
29 | - Guarantees. | |
30 | ||
31 | (*) What are memory barriers? | |
32 | ||
33 | - Varieties of memory barrier. | |
34 | - What may not be assumed about memory barriers? | |
35 | - Data dependency barriers. | |
36 | - Control dependencies. | |
37 | - SMP barrier pairing. | |
38 | - Examples of memory barrier sequences. | |
670bd95e | 39 | - Read memory barriers vs load speculation. |
241e6663 | 40 | - Transitivity |
108b42b4 DH |
41 | |
42 | (*) Explicit kernel barriers. | |
43 | ||
44 | - Compiler barrier. | |
81fc6323 | 45 | - CPU memory barriers. |
108b42b4 DH |
46 | - MMIO write barrier. |
47 | ||
48 | (*) Implicit kernel memory barriers. | |
49 | ||
166bda71 | 50 | - Lock acquisition functions. |
108b42b4 | 51 | - Interrupt disabling functions. |
50fa610a | 52 | - Sleep and wake-up functions. |
108b42b4 DH |
53 | - Miscellaneous functions. |
54 | ||
166bda71 | 55 | (*) Inter-CPU acquiring barrier effects. |
108b42b4 | 56 | |
166bda71 SP |
57 | - Acquires vs memory accesses. |
58 | - Acquires vs I/O accesses. | |
108b42b4 DH |
59 | |
60 | (*) Where are memory barriers needed? | |
61 | ||
62 | - Interprocessor interaction. | |
63 | - Atomic operations. | |
64 | - Accessing devices. | |
65 | - Interrupts. | |
66 | ||
67 | (*) Kernel I/O barrier effects. | |
68 | ||
69 | (*) Assumed minimum execution ordering model. | |
70 | ||
71 | (*) The effects of the cpu cache. | |
72 | ||
73 | - Cache coherency. | |
74 | - Cache coherency vs DMA. | |
75 | - Cache coherency vs MMIO. | |
76 | ||
77 | (*) The things CPUs get up to. | |
78 | ||
79 | - And then there's the Alpha. | |
01e1cd6d | 80 | - Virtual Machine Guests. |
108b42b4 | 81 | |
90fddabf DH |
82 | (*) Example uses. |
83 | ||
84 | - Circular buffers. | |
85 | ||
108b42b4 DH |
86 | (*) References. |
87 | ||
88 | ||
89 | ============================ | |
90 | ABSTRACT MEMORY ACCESS MODEL | |
91 | ============================ | |
92 | ||
93 | Consider the following abstract model of the system: | |
94 | ||
95 | : : | |
96 | : : | |
97 | : : | |
98 | +-------+ : +--------+ : +-------+ | |
99 | | | : | | : | | | |
100 | | | : | | : | | | |
101 | | CPU 1 |<----->| Memory |<----->| CPU 2 | | |
102 | | | : | | : | | | |
103 | | | : | | : | | | |
104 | +-------+ : +--------+ : +-------+ | |
105 | ^ : ^ : ^ | |
106 | | : | : | | |
107 | | : | : | | |
108 | | : v : | | |
109 | | : +--------+ : | | |
110 | | : | | : | | |
111 | | : | | : | | |
112 | +---------->| Device |<----------+ | |
113 | : | | : | |
114 | : | | : | |
115 | : +--------+ : | |
116 | : : | |
117 | ||
118 | Each CPU executes a program that generates memory access operations. In the | |
119 | abstract CPU, memory operation ordering is very relaxed, and a CPU may actually | |
120 | perform the memory operations in any order it likes, provided program causality | |
121 | appears to be maintained. Similarly, the compiler may also arrange the | |
122 | instructions it emits in any order it likes, provided it doesn't affect the | |
123 | apparent operation of the program. | |
124 | ||
125 | So in the above diagram, the effects of the memory operations performed by a | |
126 | CPU are perceived by the rest of the system as the operations cross the | |
127 | interface between the CPU and rest of the system (the dotted lines). | |
128 | ||
129 | ||
130 | For example, consider the following sequence of events: | |
131 | ||
132 | CPU 1 CPU 2 | |
133 | =============== =============== | |
134 | { A == 1; B == 2 } | |
615cc2c9 AD |
135 | A = 3; x = B; |
136 | B = 4; y = A; | |
108b42b4 DH |
137 | |
138 | The set of accesses as seen by the memory system in the middle can be arranged | |
139 | in 24 different combinations: | |
140 | ||
8ab8b3e1 PK |
141 | STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4 |
142 | STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3 | |
143 | STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4 | |
144 | STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4 | |
145 | STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3 | |
146 | STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4 | |
147 | STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4 | |
108b42b4 DH |
148 | STORE B=4, ... |
149 | ... | |
150 | ||
151 | and can thus result in four different combinations of values: | |
152 | ||
8ab8b3e1 PK |
153 | x == 2, y == 1 |
154 | x == 2, y == 3 | |
155 | x == 4, y == 1 | |
156 | x == 4, y == 3 | |
108b42b4 DH |
157 | |
158 | ||
159 | Furthermore, the stores committed by a CPU to the memory system may not be | |
160 | perceived by the loads made by another CPU in the same order as the stores were | |
161 | committed. | |
162 | ||
163 | ||
164 | As a further example, consider this sequence of events: | |
165 | ||
166 | CPU 1 CPU 2 | |
167 | =============== =============== | |
3dbf0913 | 168 | { A == 1, B == 2, C == 3, P == &A, Q == &C } |
108b42b4 DH |
169 | B = 4; Q = P; |
170 | P = &B D = *Q; | |
171 | ||
172 | There is an obvious data dependency here, as the value loaded into D depends on | |
173 | the address retrieved from P by CPU 2. At the end of the sequence, any of the | |
174 | following results are possible: | |
175 | ||
176 | (Q == &A) and (D == 1) | |
177 | (Q == &B) and (D == 2) | |
178 | (Q == &B) and (D == 4) | |
179 | ||
180 | Note that CPU 2 will never try and load C into D because the CPU will load P | |
181 | into Q before issuing the load of *Q. | |
182 | ||
183 | ||
184 | DEVICE OPERATIONS | |
185 | ----------------- | |
186 | ||
187 | Some devices present their control interfaces as collections of memory | |
188 | locations, but the order in which the control registers are accessed is very | |
189 | important. For instance, imagine an ethernet card with a set of internal | |
190 | registers that are accessed through an address port register (A) and a data | |
191 | port register (D). To read internal register 5, the following code might then | |
192 | be used: | |
193 | ||
194 | *A = 5; | |
195 | x = *D; | |
196 | ||
197 | but this might show up as either of the following two sequences: | |
198 | ||
199 | STORE *A = 5, x = LOAD *D | |
200 | x = LOAD *D, STORE *A = 5 | |
201 | ||
202 | the second of which will almost certainly result in a malfunction, since it set | |
203 | the address _after_ attempting to read the register. | |
204 | ||
205 | ||
206 | GUARANTEES | |
207 | ---------- | |
208 | ||
209 | There are some minimal guarantees that may be expected of a CPU: | |
210 | ||
211 | (*) On any given CPU, dependent memory accesses will be issued in order, with | |
212 | respect to itself. This means that for: | |
213 | ||
f84cfbb0 | 214 | Q = READ_ONCE(P); smp_read_barrier_depends(); D = READ_ONCE(*Q); |
108b42b4 DH |
215 | |
216 | the CPU will issue the following memory operations: | |
217 | ||
218 | Q = LOAD P, D = LOAD *Q | |
219 | ||
2ecf8101 | 220 | and always in that order. On most systems, smp_read_barrier_depends() |
9af194ce | 221 | does nothing, but it is required for DEC Alpha. The READ_ONCE() |
f84cfbb0 CM |
222 | is required to prevent compiler mischief. Please note that you |
223 | should normally use something like rcu_dereference() instead of | |
224 | open-coding smp_read_barrier_depends(). | |
108b42b4 DH |
225 | |
226 | (*) Overlapping loads and stores within a particular CPU will appear to be | |
227 | ordered within that CPU. This means that for: | |
228 | ||
9af194ce | 229 | a = READ_ONCE(*X); WRITE_ONCE(*X, b); |
108b42b4 DH |
230 | |
231 | the CPU will only issue the following sequence of memory operations: | |
232 | ||
233 | a = LOAD *X, STORE *X = b | |
234 | ||
235 | And for: | |
236 | ||
9af194ce | 237 | WRITE_ONCE(*X, c); d = READ_ONCE(*X); |
108b42b4 DH |
238 | |
239 | the CPU will only issue: | |
240 | ||
241 | STORE *X = c, d = LOAD *X | |
242 | ||
fa00e7e1 | 243 | (Loads and stores overlap if they are targeted at overlapping pieces of |
108b42b4 DH |
244 | memory). |
245 | ||
246 | And there are a number of things that _must_ or _must_not_ be assumed: | |
247 | ||
9af194ce PM |
248 | (*) It _must_not_ be assumed that the compiler will do what you want |
249 | with memory references that are not protected by READ_ONCE() and | |
250 | WRITE_ONCE(). Without them, the compiler is within its rights to | |
251 | do all sorts of "creative" transformations, which are covered in | |
895f5542 | 252 | the COMPILER BARRIER section. |
2ecf8101 | 253 | |
108b42b4 DH |
254 | (*) It _must_not_ be assumed that independent loads and stores will be issued |
255 | in the order given. This means that for: | |
256 | ||
257 | X = *A; Y = *B; *D = Z; | |
258 | ||
259 | we may get any of the following sequences: | |
260 | ||
261 | X = LOAD *A, Y = LOAD *B, STORE *D = Z | |
262 | X = LOAD *A, STORE *D = Z, Y = LOAD *B | |
263 | Y = LOAD *B, X = LOAD *A, STORE *D = Z | |
264 | Y = LOAD *B, STORE *D = Z, X = LOAD *A | |
265 | STORE *D = Z, X = LOAD *A, Y = LOAD *B | |
266 | STORE *D = Z, Y = LOAD *B, X = LOAD *A | |
267 | ||
268 | (*) It _must_ be assumed that overlapping memory accesses may be merged or | |
269 | discarded. This means that for: | |
270 | ||
271 | X = *A; Y = *(A + 4); | |
272 | ||
273 | we may get any one of the following sequences: | |
274 | ||
275 | X = LOAD *A; Y = LOAD *(A + 4); | |
276 | Y = LOAD *(A + 4); X = LOAD *A; | |
277 | {X, Y} = LOAD {*A, *(A + 4) }; | |
278 | ||
279 | And for: | |
280 | ||
f191eec5 | 281 | *A = X; *(A + 4) = Y; |
108b42b4 | 282 | |
f191eec5 | 283 | we may get any of: |
108b42b4 | 284 | |
f191eec5 PM |
285 | STORE *A = X; STORE *(A + 4) = Y; |
286 | STORE *(A + 4) = Y; STORE *A = X; | |
287 | STORE {*A, *(A + 4) } = {X, Y}; | |
108b42b4 | 288 | |
432fbf3c PM |
289 | And there are anti-guarantees: |
290 | ||
291 | (*) These guarantees do not apply to bitfields, because compilers often | |
292 | generate code to modify these using non-atomic read-modify-write | |
293 | sequences. Do not attempt to use bitfields to synchronize parallel | |
294 | algorithms. | |
295 | ||
296 | (*) Even in cases where bitfields are protected by locks, all fields | |
297 | in a given bitfield must be protected by one lock. If two fields | |
298 | in a given bitfield are protected by different locks, the compiler's | |
299 | non-atomic read-modify-write sequences can cause an update to one | |
300 | field to corrupt the value of an adjacent field. | |
301 | ||
302 | (*) These guarantees apply only to properly aligned and sized scalar | |
303 | variables. "Properly sized" currently means variables that are | |
304 | the same size as "char", "short", "int" and "long". "Properly | |
305 | aligned" means the natural alignment, thus no constraints for | |
306 | "char", two-byte alignment for "short", four-byte alignment for | |
307 | "int", and either four-byte or eight-byte alignment for "long", | |
308 | on 32-bit and 64-bit systems, respectively. Note that these | |
309 | guarantees were introduced into the C11 standard, so beware when | |
310 | using older pre-C11 compilers (for example, gcc 4.6). The portion | |
311 | of the standard containing this guarantee is Section 3.14, which | |
312 | defines "memory location" as follows: | |
313 | ||
314 | memory location | |
315 | either an object of scalar type, or a maximal sequence | |
316 | of adjacent bit-fields all having nonzero width | |
317 | ||
318 | NOTE 1: Two threads of execution can update and access | |
319 | separate memory locations without interfering with | |
320 | each other. | |
321 | ||
322 | NOTE 2: A bit-field and an adjacent non-bit-field member | |
323 | are in separate memory locations. The same applies | |
324 | to two bit-fields, if one is declared inside a nested | |
325 | structure declaration and the other is not, or if the two | |
326 | are separated by a zero-length bit-field declaration, | |
327 | or if they are separated by a non-bit-field member | |
328 | declaration. It is not safe to concurrently update two | |
329 | bit-fields in the same structure if all members declared | |
330 | between them are also bit-fields, no matter what the | |
331 | sizes of those intervening bit-fields happen to be. | |
332 | ||
108b42b4 DH |
333 | |
334 | ========================= | |
335 | WHAT ARE MEMORY BARRIERS? | |
336 | ========================= | |
337 | ||
338 | As can be seen above, independent memory operations are effectively performed | |
339 | in random order, but this can be a problem for CPU-CPU interaction and for I/O. | |
340 | What is required is some way of intervening to instruct the compiler and the | |
341 | CPU to restrict the order. | |
342 | ||
343 | Memory barriers are such interventions. They impose a perceived partial | |
2b94895b DH |
344 | ordering over the memory operations on either side of the barrier. |
345 | ||
346 | Such enforcement is important because the CPUs and other devices in a system | |
81fc6323 | 347 | can use a variety of tricks to improve performance, including reordering, |
2b94895b DH |
348 | deferral and combination of memory operations; speculative loads; speculative |
349 | branch prediction and various types of caching. Memory barriers are used to | |
350 | override or suppress these tricks, allowing the code to sanely control the | |
351 | interaction of multiple CPUs and/or devices. | |
108b42b4 DH |
352 | |
353 | ||
354 | VARIETIES OF MEMORY BARRIER | |
355 | --------------------------- | |
356 | ||
357 | Memory barriers come in four basic varieties: | |
358 | ||
359 | (1) Write (or store) memory barriers. | |
360 | ||
361 | A write memory barrier gives a guarantee that all the STORE operations | |
362 | specified before the barrier will appear to happen before all the STORE | |
363 | operations specified after the barrier with respect to the other | |
364 | components of the system. | |
365 | ||
366 | A write barrier is a partial ordering on stores only; it is not required | |
367 | to have any effect on loads. | |
368 | ||
6bc39274 | 369 | A CPU can be viewed as committing a sequence of store operations to the |
108b42b4 DH |
370 | memory system as time progresses. All stores before a write barrier will |
371 | occur in the sequence _before_ all the stores after the write barrier. | |
372 | ||
373 | [!] Note that write barriers should normally be paired with read or data | |
374 | dependency barriers; see the "SMP barrier pairing" subsection. | |
375 | ||
376 | ||
377 | (2) Data dependency barriers. | |
378 | ||
379 | A data dependency barrier is a weaker form of read barrier. In the case | |
380 | where two loads are performed such that the second depends on the result | |
381 | of the first (eg: the first load retrieves the address to which the second | |
382 | load will be directed), a data dependency barrier would be required to | |
383 | make sure that the target of the second load is updated before the address | |
384 | obtained by the first load is accessed. | |
385 | ||
386 | A data dependency barrier is a partial ordering on interdependent loads | |
387 | only; it is not required to have any effect on stores, independent loads | |
388 | or overlapping loads. | |
389 | ||
390 | As mentioned in (1), the other CPUs in the system can be viewed as | |
391 | committing sequences of stores to the memory system that the CPU being | |
392 | considered can then perceive. A data dependency barrier issued by the CPU | |
393 | under consideration guarantees that for any load preceding it, if that | |
394 | load touches one of a sequence of stores from another CPU, then by the | |
395 | time the barrier completes, the effects of all the stores prior to that | |
396 | touched by the load will be perceptible to any loads issued after the data | |
397 | dependency barrier. | |
398 | ||
399 | See the "Examples of memory barrier sequences" subsection for diagrams | |
400 | showing the ordering constraints. | |
401 | ||
402 | [!] Note that the first load really has to have a _data_ dependency and | |
403 | not a control dependency. If the address for the second load is dependent | |
404 | on the first load, but the dependency is through a conditional rather than | |
405 | actually loading the address itself, then it's a _control_ dependency and | |
406 | a full read barrier or better is required. See the "Control dependencies" | |
407 | subsection for more information. | |
408 | ||
409 | [!] Note that data dependency barriers should normally be paired with | |
410 | write barriers; see the "SMP barrier pairing" subsection. | |
411 | ||
412 | ||
413 | (3) Read (or load) memory barriers. | |
414 | ||
415 | A read barrier is a data dependency barrier plus a guarantee that all the | |
416 | LOAD operations specified before the barrier will appear to happen before | |
417 | all the LOAD operations specified after the barrier with respect to the | |
418 | other components of the system. | |
419 | ||
420 | A read barrier is a partial ordering on loads only; it is not required to | |
421 | have any effect on stores. | |
422 | ||
423 | Read memory barriers imply data dependency barriers, and so can substitute | |
424 | for them. | |
425 | ||
426 | [!] Note that read barriers should normally be paired with write barriers; | |
427 | see the "SMP barrier pairing" subsection. | |
428 | ||
429 | ||
430 | (4) General memory barriers. | |
431 | ||
670bd95e DH |
432 | A general memory barrier gives a guarantee that all the LOAD and STORE |
433 | operations specified before the barrier will appear to happen before all | |
434 | the LOAD and STORE operations specified after the barrier with respect to | |
435 | the other components of the system. | |
436 | ||
437 | A general memory barrier is a partial ordering over both loads and stores. | |
108b42b4 DH |
438 | |
439 | General memory barriers imply both read and write memory barriers, and so | |
440 | can substitute for either. | |
441 | ||
442 | ||
443 | And a couple of implicit varieties: | |
444 | ||
2e4f5382 | 445 | (5) ACQUIRE operations. |
108b42b4 DH |
446 | |
447 | This acts as a one-way permeable barrier. It guarantees that all memory | |
2e4f5382 PZ |
448 | operations after the ACQUIRE operation will appear to happen after the |
449 | ACQUIRE operation with respect to the other components of the system. | |
787df638 DB |
450 | ACQUIRE operations include LOCK operations and both smp_load_acquire() |
451 | and smp_cond_acquire() operations. The later builds the necessary ACQUIRE | |
452 | semantics from relying on a control dependency and smp_rmb(). | |
108b42b4 | 453 | |
2e4f5382 PZ |
454 | Memory operations that occur before an ACQUIRE operation may appear to |
455 | happen after it completes. | |
108b42b4 | 456 | |
2e4f5382 PZ |
457 | An ACQUIRE operation should almost always be paired with a RELEASE |
458 | operation. | |
108b42b4 DH |
459 | |
460 | ||
2e4f5382 | 461 | (6) RELEASE operations. |
108b42b4 DH |
462 | |
463 | This also acts as a one-way permeable barrier. It guarantees that all | |
2e4f5382 PZ |
464 | memory operations before the RELEASE operation will appear to happen |
465 | before the RELEASE operation with respect to the other components of the | |
466 | system. RELEASE operations include UNLOCK operations and | |
467 | smp_store_release() operations. | |
108b42b4 | 468 | |
2e4f5382 | 469 | Memory operations that occur after a RELEASE operation may appear to |
108b42b4 DH |
470 | happen before it completes. |
471 | ||
2e4f5382 PZ |
472 | The use of ACQUIRE and RELEASE operations generally precludes the need |
473 | for other sorts of memory barrier (but note the exceptions mentioned in | |
474 | the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE | |
475 | pair is -not- guaranteed to act as a full memory barrier. However, after | |
476 | an ACQUIRE on a given variable, all memory accesses preceding any prior | |
477 | RELEASE on that same variable are guaranteed to be visible. In other | |
478 | words, within a given variable's critical section, all accesses of all | |
479 | previous critical sections for that variable are guaranteed to have | |
480 | completed. | |
17eb88e0 | 481 | |
2e4f5382 PZ |
482 | This means that ACQUIRE acts as a minimal "acquire" operation and |
483 | RELEASE acts as a minimal "release" operation. | |
108b42b4 DH |
484 | |
485 | ||
486 | Memory barriers are only required where there's a possibility of interaction | |
487 | between two CPUs or between a CPU and a device. If it can be guaranteed that | |
488 | there won't be any such interaction in any particular piece of code, then | |
489 | memory barriers are unnecessary in that piece of code. | |
490 | ||
491 | ||
492 | Note that these are the _minimum_ guarantees. Different architectures may give | |
493 | more substantial guarantees, but they may _not_ be relied upon outside of arch | |
494 | specific code. | |
495 | ||
496 | ||
497 | WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS? | |
498 | ---------------------------------------------- | |
499 | ||
500 | There are certain things that the Linux kernel memory barriers do not guarantee: | |
501 | ||
502 | (*) There is no guarantee that any of the memory accesses specified before a | |
503 | memory barrier will be _complete_ by the completion of a memory barrier | |
504 | instruction; the barrier can be considered to draw a line in that CPU's | |
505 | access queue that accesses of the appropriate type may not cross. | |
506 | ||
507 | (*) There is no guarantee that issuing a memory barrier on one CPU will have | |
508 | any direct effect on another CPU or any other hardware in the system. The | |
509 | indirect effect will be the order in which the second CPU sees the effects | |
510 | of the first CPU's accesses occur, but see the next point: | |
511 | ||
6bc39274 | 512 | (*) There is no guarantee that a CPU will see the correct order of effects |
108b42b4 DH |
513 | from a second CPU's accesses, even _if_ the second CPU uses a memory |
514 | barrier, unless the first CPU _also_ uses a matching memory barrier (see | |
515 | the subsection on "SMP Barrier Pairing"). | |
516 | ||
517 | (*) There is no guarantee that some intervening piece of off-the-CPU | |
518 | hardware[*] will not reorder the memory accesses. CPU cache coherency | |
519 | mechanisms should propagate the indirect effects of a memory barrier | |
520 | between CPUs, but might not do so in order. | |
521 | ||
522 | [*] For information on bus mastering DMA and coherency please read: | |
523 | ||
4b5ff469 | 524 | Documentation/PCI/pci.txt |
395cf969 | 525 | Documentation/DMA-API-HOWTO.txt |
108b42b4 DH |
526 | Documentation/DMA-API.txt |
527 | ||
528 | ||
529 | DATA DEPENDENCY BARRIERS | |
530 | ------------------------ | |
531 | ||
532 | The usage requirements of data dependency barriers are a little subtle, and | |
533 | it's not always obvious that they're needed. To illustrate, consider the | |
534 | following sequence of events: | |
535 | ||
2ecf8101 PM |
536 | CPU 1 CPU 2 |
537 | =============== =============== | |
3dbf0913 | 538 | { A == 1, B == 2, C == 3, P == &A, Q == &C } |
108b42b4 DH |
539 | B = 4; |
540 | <write barrier> | |
9af194ce PM |
541 | WRITE_ONCE(P, &B) |
542 | Q = READ_ONCE(P); | |
2ecf8101 | 543 | D = *Q; |
108b42b4 DH |
544 | |
545 | There's a clear data dependency here, and it would seem that by the end of the | |
546 | sequence, Q must be either &A or &B, and that: | |
547 | ||
548 | (Q == &A) implies (D == 1) | |
549 | (Q == &B) implies (D == 4) | |
550 | ||
81fc6323 | 551 | But! CPU 2's perception of P may be updated _before_ its perception of B, thus |
108b42b4 DH |
552 | leading to the following situation: |
553 | ||
554 | (Q == &B) and (D == 2) ???? | |
555 | ||
556 | Whilst this may seem like a failure of coherency or causality maintenance, it | |
557 | isn't, and this behaviour can be observed on certain real CPUs (such as the DEC | |
558 | Alpha). | |
559 | ||
2b94895b DH |
560 | To deal with this, a data dependency barrier or better must be inserted |
561 | between the address load and the data load: | |
108b42b4 | 562 | |
2ecf8101 PM |
563 | CPU 1 CPU 2 |
564 | =============== =============== | |
3dbf0913 | 565 | { A == 1, B == 2, C == 3, P == &A, Q == &C } |
108b42b4 DH |
566 | B = 4; |
567 | <write barrier> | |
9af194ce PM |
568 | WRITE_ONCE(P, &B); |
569 | Q = READ_ONCE(P); | |
2ecf8101 PM |
570 | <data dependency barrier> |
571 | D = *Q; | |
108b42b4 DH |
572 | |
573 | This enforces the occurrence of one of the two implications, and prevents the | |
574 | third possibility from arising. | |
575 | ||
92a84dd2 PM |
576 | A data-dependency barrier must also order against dependent writes: |
577 | ||
578 | CPU 1 CPU 2 | |
579 | =============== =============== | |
580 | { A == 1, B == 2, C = 3, P == &A, Q == &C } | |
581 | B = 4; | |
582 | <write barrier> | |
583 | WRITE_ONCE(P, &B); | |
584 | Q = READ_ONCE(P); | |
585 | <data dependency barrier> | |
586 | *Q = 5; | |
587 | ||
588 | The data-dependency barrier must order the read into Q with the store | |
589 | into *Q. This prohibits this outcome: | |
590 | ||
591 | (Q == B) && (B == 4) | |
592 | ||
593 | Please note that this pattern should be rare. After all, the whole point | |
594 | of dependency ordering is to -prevent- writes to the data structure, along | |
595 | with the expensive cache misses associated with those writes. This pattern | |
596 | can be used to record rare error conditions and the like, and the ordering | |
597 | prevents such records from being lost. | |
598 | ||
599 | ||
108b42b4 DH |
600 | [!] Note that this extremely counterintuitive situation arises most easily on |
601 | machines with split caches, so that, for example, one cache bank processes | |
602 | even-numbered cache lines and the other bank processes odd-numbered cache | |
603 | lines. The pointer P might be stored in an odd-numbered cache line, and the | |
604 | variable B might be stored in an even-numbered cache line. Then, if the | |
605 | even-numbered bank of the reading CPU's cache is extremely busy while the | |
606 | odd-numbered bank is idle, one can see the new value of the pointer P (&B), | |
6bc39274 | 607 | but the old value of the variable B (2). |
108b42b4 DH |
608 | |
609 | ||
2ecf8101 PM |
610 | The data dependency barrier is very important to the RCU system, |
611 | for example. See rcu_assign_pointer() and rcu_dereference() in | |
612 | include/linux/rcupdate.h. This permits the current target of an RCU'd | |
613 | pointer to be replaced with a new modified target, without the replacement | |
614 | target appearing to be incompletely initialised. | |
108b42b4 DH |
615 | |
616 | See also the subsection on "Cache Coherency" for a more thorough example. | |
617 | ||
618 | ||
619 | CONTROL DEPENDENCIES | |
620 | -------------------- | |
621 | ||
ff382810 PM |
622 | A load-load control dependency requires a full read memory barrier, not |
623 | simply a data dependency barrier to make it work correctly. Consider the | |
624 | following bit of code: | |
108b42b4 | 625 | |
9af194ce | 626 | q = READ_ONCE(a); |
18c03c61 PZ |
627 | if (q) { |
628 | <data dependency barrier> /* BUG: No data dependency!!! */ | |
9af194ce | 629 | p = READ_ONCE(b); |
45c8a36a | 630 | } |
108b42b4 DH |
631 | |
632 | This will not have the desired effect because there is no actual data | |
2ecf8101 PM |
633 | dependency, but rather a control dependency that the CPU may short-circuit |
634 | by attempting to predict the outcome in advance, so that other CPUs see | |
635 | the load from b as having happened before the load from a. In such a | |
636 | case what's actually required is: | |
108b42b4 | 637 | |
9af194ce | 638 | q = READ_ONCE(a); |
18c03c61 | 639 | if (q) { |
45c8a36a | 640 | <read barrier> |
9af194ce | 641 | p = READ_ONCE(b); |
45c8a36a | 642 | } |
18c03c61 PZ |
643 | |
644 | However, stores are not speculated. This means that ordering -is- provided | |
ff382810 | 645 | for load-store control dependencies, as in the following example: |
18c03c61 | 646 | |
105ff3cb | 647 | q = READ_ONCE(a); |
18c03c61 | 648 | if (q) { |
9af194ce | 649 | WRITE_ONCE(b, p); |
18c03c61 PZ |
650 | } |
651 | ||
5af4692a | 652 | Control dependencies pair normally with other types of barriers. That |
105ff3cb LT |
653 | said, please note that READ_ONCE() is not optional! Without the |
654 | READ_ONCE(), the compiler might combine the load from 'a' with other | |
655 | loads from 'a', and the store to 'b' with other stores to 'b', with | |
656 | possible highly counterintuitive effects on ordering. | |
18c03c61 PZ |
657 | |
658 | Worse yet, if the compiler is able to prove (say) that the value of | |
659 | variable 'a' is always non-zero, it would be well within its rights | |
660 | to optimize the original example by eliminating the "if" statement | |
661 | as follows: | |
662 | ||
663 | q = a; | |
2456d2a6 PM |
664 | b = p; /* BUG: Compiler and CPU can both reorder!!! */ |
665 | ||
105ff3cb | 666 | So don't leave out the READ_ONCE(). |
18c03c61 | 667 | |
2456d2a6 PM |
668 | It is tempting to try to enforce ordering on identical stores on both |
669 | branches of the "if" statement as follows: | |
18c03c61 | 670 | |
105ff3cb | 671 | q = READ_ONCE(a); |
18c03c61 | 672 | if (q) { |
9b2b3bf5 | 673 | barrier(); |
9af194ce | 674 | WRITE_ONCE(b, p); |
18c03c61 PZ |
675 | do_something(); |
676 | } else { | |
9b2b3bf5 | 677 | barrier(); |
9af194ce | 678 | WRITE_ONCE(b, p); |
18c03c61 PZ |
679 | do_something_else(); |
680 | } | |
681 | ||
2456d2a6 PM |
682 | Unfortunately, current compilers will transform this as follows at high |
683 | optimization levels: | |
18c03c61 | 684 | |
105ff3cb | 685 | q = READ_ONCE(a); |
2456d2a6 | 686 | barrier(); |
9af194ce | 687 | WRITE_ONCE(b, p); /* BUG: No ordering vs. load from a!!! */ |
18c03c61 | 688 | if (q) { |
9af194ce | 689 | /* WRITE_ONCE(b, p); -- moved up, BUG!!! */ |
18c03c61 PZ |
690 | do_something(); |
691 | } else { | |
9af194ce | 692 | /* WRITE_ONCE(b, p); -- moved up, BUG!!! */ |
18c03c61 PZ |
693 | do_something_else(); |
694 | } | |
695 | ||
2456d2a6 PM |
696 | Now there is no conditional between the load from 'a' and the store to |
697 | 'b', which means that the CPU is within its rights to reorder them: | |
698 | The conditional is absolutely required, and must be present in the | |
699 | assembly code even after all compiler optimizations have been applied. | |
700 | Therefore, if you need ordering in this example, you need explicit | |
701 | memory barriers, for example, smp_store_release(): | |
18c03c61 | 702 | |
9af194ce | 703 | q = READ_ONCE(a); |
2456d2a6 PM |
704 | if (q) { |
705 | smp_store_release(&b, p); | |
18c03c61 PZ |
706 | do_something(); |
707 | } else { | |
2456d2a6 | 708 | smp_store_release(&b, p); |
18c03c61 PZ |
709 | do_something_else(); |
710 | } | |
711 | ||
2456d2a6 PM |
712 | In contrast, without explicit memory barriers, two-legged-if control |
713 | ordering is guaranteed only when the stores differ, for example: | |
714 | ||
105ff3cb | 715 | q = READ_ONCE(a); |
2456d2a6 | 716 | if (q) { |
9af194ce | 717 | WRITE_ONCE(b, p); |
2456d2a6 PM |
718 | do_something(); |
719 | } else { | |
9af194ce | 720 | WRITE_ONCE(b, r); |
2456d2a6 PM |
721 | do_something_else(); |
722 | } | |
723 | ||
105ff3cb LT |
724 | The initial READ_ONCE() is still required to prevent the compiler from |
725 | proving the value of 'a'. | |
18c03c61 PZ |
726 | |
727 | In addition, you need to be careful what you do with the local variable 'q', | |
728 | otherwise the compiler might be able to guess the value and again remove | |
729 | the needed conditional. For example: | |
730 | ||
105ff3cb | 731 | q = READ_ONCE(a); |
18c03c61 | 732 | if (q % MAX) { |
9af194ce | 733 | WRITE_ONCE(b, p); |
18c03c61 PZ |
734 | do_something(); |
735 | } else { | |
9af194ce | 736 | WRITE_ONCE(b, r); |
18c03c61 PZ |
737 | do_something_else(); |
738 | } | |
739 | ||
740 | If MAX is defined to be 1, then the compiler knows that (q % MAX) is | |
741 | equal to zero, in which case the compiler is within its rights to | |
742 | transform the above code into the following: | |
743 | ||
105ff3cb | 744 | q = READ_ONCE(a); |
9af194ce | 745 | WRITE_ONCE(b, p); |
18c03c61 PZ |
746 | do_something_else(); |
747 | ||
2456d2a6 PM |
748 | Given this transformation, the CPU is not required to respect the ordering |
749 | between the load from variable 'a' and the store to variable 'b'. It is | |
750 | tempting to add a barrier(), but this does not help. The conditional | |
751 | is gone, and the barrier won't bring it back. Therefore, if you are | |
752 | relying on this ordering, you should make sure that MAX is greater than | |
753 | one, perhaps as follows: | |
18c03c61 | 754 | |
105ff3cb | 755 | q = READ_ONCE(a); |
18c03c61 PZ |
756 | BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */ |
757 | if (q % MAX) { | |
9af194ce | 758 | WRITE_ONCE(b, p); |
18c03c61 PZ |
759 | do_something(); |
760 | } else { | |
9af194ce | 761 | WRITE_ONCE(b, r); |
18c03c61 PZ |
762 | do_something_else(); |
763 | } | |
764 | ||
2456d2a6 PM |
765 | Please note once again that the stores to 'b' differ. If they were |
766 | identical, as noted earlier, the compiler could pull this store outside | |
767 | of the 'if' statement. | |
768 | ||
8b19d1de PM |
769 | You must also be careful not to rely too much on boolean short-circuit |
770 | evaluation. Consider this example: | |
771 | ||
105ff3cb | 772 | q = READ_ONCE(a); |
57aecae9 | 773 | if (q || 1 > 0) |
9af194ce | 774 | WRITE_ONCE(b, 1); |
8b19d1de | 775 | |
5af4692a PM |
776 | Because the first condition cannot fault and the second condition is |
777 | always true, the compiler can transform this example as following, | |
778 | defeating control dependency: | |
8b19d1de | 779 | |
105ff3cb | 780 | q = READ_ONCE(a); |
9af194ce | 781 | WRITE_ONCE(b, 1); |
8b19d1de PM |
782 | |
783 | This example underscores the need to ensure that the compiler cannot | |
9af194ce | 784 | out-guess your code. More generally, although READ_ONCE() does force |
8b19d1de PM |
785 | the compiler to actually emit code for a given load, it does not force |
786 | the compiler to use the results. | |
787 | ||
18c03c61 | 788 | Finally, control dependencies do -not- provide transitivity. This is |
5646f7ac PM |
789 | demonstrated by two related examples, with the initial values of |
790 | x and y both being zero: | |
18c03c61 PZ |
791 | |
792 | CPU 0 CPU 1 | |
5af4692a | 793 | ======================= ======================= |
105ff3cb | 794 | r1 = READ_ONCE(x); r2 = READ_ONCE(y); |
5646f7ac | 795 | if (r1 > 0) if (r2 > 0) |
9af194ce | 796 | WRITE_ONCE(y, 1); WRITE_ONCE(x, 1); |
18c03c61 PZ |
797 | |
798 | assert(!(r1 == 1 && r2 == 1)); | |
799 | ||
800 | The above two-CPU example will never trigger the assert(). However, | |
801 | if control dependencies guaranteed transitivity (which they do not), | |
5646f7ac | 802 | then adding the following CPU would guarantee a related assertion: |
18c03c61 | 803 | |
5646f7ac PM |
804 | CPU 2 |
805 | ===================== | |
9af194ce | 806 | WRITE_ONCE(x, 2); |
5646f7ac PM |
807 | |
808 | assert(!(r1 == 2 && r2 == 1 && x == 2)); /* FAILS!!! */ | |
18c03c61 | 809 | |
5646f7ac PM |
810 | But because control dependencies do -not- provide transitivity, the above |
811 | assertion can fail after the combined three-CPU example completes. If you | |
812 | need the three-CPU example to provide ordering, you will need smp_mb() | |
813 | between the loads and stores in the CPU 0 and CPU 1 code fragments, | |
5af4692a PM |
814 | that is, just before or just after the "if" statements. Furthermore, |
815 | the original two-CPU example is very fragile and should be avoided. | |
18c03c61 | 816 | |
5646f7ac PM |
817 | These two examples are the LB and WWC litmus tests from this paper: |
818 | http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this | |
819 | site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html. | |
18c03c61 PZ |
820 | |
821 | In summary: | |
822 | ||
823 | (*) Control dependencies can order prior loads against later stores. | |
824 | However, they do -not- guarantee any other sort of ordering: | |
825 | Not prior loads against later loads, nor prior stores against | |
826 | later anything. If you need these other forms of ordering, | |
d87510c5 | 827 | use smp_rmb(), smp_wmb(), or, in the case of prior stores and |
18c03c61 PZ |
828 | later loads, smp_mb(). |
829 | ||
7817b799 PM |
830 | (*) If both legs of the "if" statement begin with identical stores to |
831 | the same variable, then those stores must be ordered, either by | |
832 | preceding both of them with smp_mb() or by using smp_store_release() | |
833 | to carry out the stores. Please note that it is -not- sufficient | |
a5052657 PM |
834 | to use barrier() at beginning of each leg of the "if" statement |
835 | because, as shown by the example above, optimizing compilers can | |
836 | destroy the control dependency while respecting the letter of the | |
837 | barrier() law. | |
9b2b3bf5 | 838 | |
18c03c61 | 839 | (*) Control dependencies require at least one run-time conditional |
586dd56a | 840 | between the prior load and the subsequent store, and this |
9af194ce PM |
841 | conditional must involve the prior load. If the compiler is able |
842 | to optimize the conditional away, it will have also optimized | |
105ff3cb LT |
843 | away the ordering. Careful use of READ_ONCE() and WRITE_ONCE() |
844 | can help to preserve the needed conditional. | |
18c03c61 PZ |
845 | |
846 | (*) Control dependencies require that the compiler avoid reordering the | |
105ff3cb LT |
847 | dependency into nonexistence. Careful use of READ_ONCE() or |
848 | atomic{,64}_read() can help to preserve your control dependency. | |
895f5542 | 849 | Please see the COMPILER BARRIER section for more information. |
18c03c61 | 850 | |
ff382810 PM |
851 | (*) Control dependencies pair normally with other types of barriers. |
852 | ||
18c03c61 PZ |
853 | (*) Control dependencies do -not- provide transitivity. If you |
854 | need transitivity, use smp_mb(). | |
108b42b4 DH |
855 | |
856 | ||
857 | SMP BARRIER PAIRING | |
858 | ------------------- | |
859 | ||
860 | When dealing with CPU-CPU interactions, certain types of memory barrier should | |
861 | always be paired. A lack of appropriate pairing is almost certainly an error. | |
862 | ||
ff382810 PM |
863 | General barriers pair with each other, though they also pair with most |
864 | other types of barriers, albeit without transitivity. An acquire barrier | |
865 | pairs with a release barrier, but both may also pair with other barriers, | |
866 | including of course general barriers. A write barrier pairs with a data | |
867 | dependency barrier, a control dependency, an acquire barrier, a release | |
868 | barrier, a read barrier, or a general barrier. Similarly a read barrier, | |
869 | control dependency, or a data dependency barrier pairs with a write | |
870 | barrier, an acquire barrier, a release barrier, or a general barrier: | |
108b42b4 | 871 | |
2ecf8101 PM |
872 | CPU 1 CPU 2 |
873 | =============== =============== | |
9af194ce | 874 | WRITE_ONCE(a, 1); |
108b42b4 | 875 | <write barrier> |
9af194ce | 876 | WRITE_ONCE(b, 2); x = READ_ONCE(b); |
2ecf8101 | 877 | <read barrier> |
9af194ce | 878 | y = READ_ONCE(a); |
108b42b4 DH |
879 | |
880 | Or: | |
881 | ||
2ecf8101 PM |
882 | CPU 1 CPU 2 |
883 | =============== =============================== | |
108b42b4 DH |
884 | a = 1; |
885 | <write barrier> | |
9af194ce | 886 | WRITE_ONCE(b, &a); x = READ_ONCE(b); |
2ecf8101 PM |
887 | <data dependency barrier> |
888 | y = *x; | |
108b42b4 | 889 | |
ff382810 PM |
890 | Or even: |
891 | ||
892 | CPU 1 CPU 2 | |
893 | =============== =============================== | |
9af194ce | 894 | r1 = READ_ONCE(y); |
ff382810 | 895 | <general barrier> |
9af194ce | 896 | WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) { |
ff382810 | 897 | <implicit control dependency> |
9af194ce | 898 | WRITE_ONCE(y, 1); |
ff382810 PM |
899 | } |
900 | ||
901 | assert(r1 == 0 || r2 == 0); | |
902 | ||
108b42b4 DH |
903 | Basically, the read barrier always has to be there, even though it can be of |
904 | the "weaker" type. | |
905 | ||
670bd95e | 906 | [!] Note that the stores before the write barrier would normally be expected to |
81fc6323 | 907 | match the loads after the read barrier or the data dependency barrier, and vice |
670bd95e DH |
908 | versa: |
909 | ||
2ecf8101 PM |
910 | CPU 1 CPU 2 |
911 | =================== =================== | |
9af194ce PM |
912 | WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c); |
913 | WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d); | |
2ecf8101 | 914 | <write barrier> \ <read barrier> |
9af194ce PM |
915 | WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a); |
916 | WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b); | |
670bd95e | 917 | |
108b42b4 DH |
918 | |
919 | EXAMPLES OF MEMORY BARRIER SEQUENCES | |
920 | ------------------------------------ | |
921 | ||
81fc6323 | 922 | Firstly, write barriers act as partial orderings on store operations. |
108b42b4 DH |
923 | Consider the following sequence of events: |
924 | ||
925 | CPU 1 | |
926 | ======================= | |
927 | STORE A = 1 | |
928 | STORE B = 2 | |
929 | STORE C = 3 | |
930 | <write barrier> | |
931 | STORE D = 4 | |
932 | STORE E = 5 | |
933 | ||
934 | This sequence of events is committed to the memory coherence system in an order | |
935 | that the rest of the system might perceive as the unordered set of { STORE A, | |
80f7228b | 936 | STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E |
108b42b4 DH |
937 | }: |
938 | ||
939 | +-------+ : : | |
940 | | | +------+ | |
941 | | |------>| C=3 | } /\ | |
81fc6323 JP |
942 | | | : +------+ }----- \ -----> Events perceptible to |
943 | | | : | A=1 | } \/ the rest of the system | |
108b42b4 DH |
944 | | | : +------+ } |
945 | | CPU 1 | : | B=2 | } | |
946 | | | +------+ } | |
947 | | | wwwwwwwwwwwwwwww } <--- At this point the write barrier | |
948 | | | +------+ } requires all stores prior to the | |
949 | | | : | E=5 | } barrier to be committed before | |
81fc6323 | 950 | | | : +------+ } further stores may take place |
108b42b4 DH |
951 | | |------>| D=4 | } |
952 | | | +------+ | |
953 | +-------+ : : | |
954 | | | |
670bd95e DH |
955 | | Sequence in which stores are committed to the |
956 | | memory system by CPU 1 | |
108b42b4 DH |
957 | V |
958 | ||
959 | ||
81fc6323 | 960 | Secondly, data dependency barriers act as partial orderings on data-dependent |
108b42b4 DH |
961 | loads. Consider the following sequence of events: |
962 | ||
963 | CPU 1 CPU 2 | |
964 | ======================= ======================= | |
c14038c3 | 965 | { B = 7; X = 9; Y = 8; C = &Y } |
108b42b4 DH |
966 | STORE A = 1 |
967 | STORE B = 2 | |
968 | <write barrier> | |
969 | STORE C = &B LOAD X | |
970 | STORE D = 4 LOAD C (gets &B) | |
971 | LOAD *C (reads B) | |
972 | ||
973 | Without intervention, CPU 2 may perceive the events on CPU 1 in some | |
974 | effectively random order, despite the write barrier issued by CPU 1: | |
975 | ||
976 | +-------+ : : : : | |
977 | | | +------+ +-------+ | Sequence of update | |
978 | | |------>| B=2 |----- --->| Y->8 | | of perception on | |
979 | | | : +------+ \ +-------+ | CPU 2 | |
980 | | CPU 1 | : | A=1 | \ --->| C->&Y | V | |
981 | | | +------+ | +-------+ | |
982 | | | wwwwwwwwwwwwwwww | : : | |
983 | | | +------+ | : : | |
984 | | | : | C=&B |--- | : : +-------+ | |
985 | | | : +------+ \ | +-------+ | | | |
986 | | |------>| D=4 | ----------->| C->&B |------>| | | |
987 | | | +------+ | +-------+ | | | |
988 | +-------+ : : | : : | | | |
989 | | : : | | | |
990 | | : : | CPU 2 | | |
991 | | +-------+ | | | |
992 | Apparently incorrect ---> | | B->7 |------>| | | |
993 | perception of B (!) | +-------+ | | | |
994 | | : : | | | |
995 | | +-------+ | | | |
996 | The load of X holds ---> \ | X->9 |------>| | | |
997 | up the maintenance \ +-------+ | | | |
998 | of coherence of B ----->| B->2 | +-------+ | |
999 | +-------+ | |
1000 | : : | |
1001 | ||
1002 | ||
1003 | In the above example, CPU 2 perceives that B is 7, despite the load of *C | |
670e9f34 | 1004 | (which would be B) coming after the LOAD of C. |
108b42b4 DH |
1005 | |
1006 | If, however, a data dependency barrier were to be placed between the load of C | |
c14038c3 DH |
1007 | and the load of *C (ie: B) on CPU 2: |
1008 | ||
1009 | CPU 1 CPU 2 | |
1010 | ======================= ======================= | |
1011 | { B = 7; X = 9; Y = 8; C = &Y } | |
1012 | STORE A = 1 | |
1013 | STORE B = 2 | |
1014 | <write barrier> | |
1015 | STORE C = &B LOAD X | |
1016 | STORE D = 4 LOAD C (gets &B) | |
1017 | <data dependency barrier> | |
1018 | LOAD *C (reads B) | |
1019 | ||
1020 | then the following will occur: | |
108b42b4 DH |
1021 | |
1022 | +-------+ : : : : | |
1023 | | | +------+ +-------+ | |
1024 | | |------>| B=2 |----- --->| Y->8 | | |
1025 | | | : +------+ \ +-------+ | |
1026 | | CPU 1 | : | A=1 | \ --->| C->&Y | | |
1027 | | | +------+ | +-------+ | |
1028 | | | wwwwwwwwwwwwwwww | : : | |
1029 | | | +------+ | : : | |
1030 | | | : | C=&B |--- | : : +-------+ | |
1031 | | | : +------+ \ | +-------+ | | | |
1032 | | |------>| D=4 | ----------->| C->&B |------>| | | |
1033 | | | +------+ | +-------+ | | | |
1034 | +-------+ : : | : : | | | |
1035 | | : : | | | |
1036 | | : : | CPU 2 | | |
1037 | | +-------+ | | | |
670bd95e DH |
1038 | | | X->9 |------>| | |
1039 | | +-------+ | | | |
1040 | Makes sure all effects ---> \ ddddddddddddddddd | | | |
1041 | prior to the store of C \ +-------+ | | | |
1042 | are perceptible to ----->| B->2 |------>| | | |
1043 | subsequent loads +-------+ | | | |
108b42b4 DH |
1044 | : : +-------+ |
1045 | ||
1046 | ||
1047 | And thirdly, a read barrier acts as a partial order on loads. Consider the | |
1048 | following sequence of events: | |
1049 | ||
1050 | CPU 1 CPU 2 | |
1051 | ======================= ======================= | |
670bd95e | 1052 | { A = 0, B = 9 } |
108b42b4 | 1053 | STORE A=1 |
108b42b4 | 1054 | <write barrier> |
670bd95e | 1055 | STORE B=2 |
108b42b4 | 1056 | LOAD B |
670bd95e | 1057 | LOAD A |
108b42b4 DH |
1058 | |
1059 | Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in | |
1060 | some effectively random order, despite the write barrier issued by CPU 1: | |
1061 | ||
670bd95e DH |
1062 | +-------+ : : : : |
1063 | | | +------+ +-------+ | |
1064 | | |------>| A=1 |------ --->| A->0 | | |
1065 | | | +------+ \ +-------+ | |
1066 | | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 | | |
1067 | | | +------+ | +-------+ | |
1068 | | |------>| B=2 |--- | : : | |
1069 | | | +------+ \ | : : +-------+ | |
1070 | +-------+ : : \ | +-------+ | | | |
1071 | ---------->| B->2 |------>| | | |
1072 | | +-------+ | CPU 2 | | |
1073 | | | A->0 |------>| | | |
1074 | | +-------+ | | | |
1075 | | : : +-------+ | |
1076 | \ : : | |
1077 | \ +-------+ | |
1078 | ---->| A->1 | | |
1079 | +-------+ | |
1080 | : : | |
108b42b4 | 1081 | |
670bd95e | 1082 | |
6bc39274 | 1083 | If, however, a read barrier were to be placed between the load of B and the |
670bd95e DH |
1084 | load of A on CPU 2: |
1085 | ||
1086 | CPU 1 CPU 2 | |
1087 | ======================= ======================= | |
1088 | { A = 0, B = 9 } | |
1089 | STORE A=1 | |
1090 | <write barrier> | |
1091 | STORE B=2 | |
1092 | LOAD B | |
1093 | <read barrier> | |
1094 | LOAD A | |
1095 | ||
1096 | then the partial ordering imposed by CPU 1 will be perceived correctly by CPU | |
1097 | 2: | |
1098 | ||
1099 | +-------+ : : : : | |
1100 | | | +------+ +-------+ | |
1101 | | |------>| A=1 |------ --->| A->0 | | |
1102 | | | +------+ \ +-------+ | |
1103 | | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 | | |
1104 | | | +------+ | +-------+ | |
1105 | | |------>| B=2 |--- | : : | |
1106 | | | +------+ \ | : : +-------+ | |
1107 | +-------+ : : \ | +-------+ | | | |
1108 | ---------->| B->2 |------>| | | |
1109 | | +-------+ | CPU 2 | | |
1110 | | : : | | | |
1111 | | : : | | | |
1112 | At this point the read ----> \ rrrrrrrrrrrrrrrrr | | | |
1113 | barrier causes all effects \ +-------+ | | | |
1114 | prior to the storage of B ---->| A->1 |------>| | | |
1115 | to be perceptible to CPU 2 +-------+ | | | |
1116 | : : +-------+ | |
1117 | ||
1118 | ||
1119 | To illustrate this more completely, consider what could happen if the code | |
1120 | contained a load of A either side of the read barrier: | |
1121 | ||
1122 | CPU 1 CPU 2 | |
1123 | ======================= ======================= | |
1124 | { A = 0, B = 9 } | |
1125 | STORE A=1 | |
1126 | <write barrier> | |
1127 | STORE B=2 | |
1128 | LOAD B | |
1129 | LOAD A [first load of A] | |
1130 | <read barrier> | |
1131 | LOAD A [second load of A] | |
1132 | ||
1133 | Even though the two loads of A both occur after the load of B, they may both | |
1134 | come up with different values: | |
1135 | ||
1136 | +-------+ : : : : | |
1137 | | | +------+ +-------+ | |
1138 | | |------>| A=1 |------ --->| A->0 | | |
1139 | | | +------+ \ +-------+ | |
1140 | | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 | | |
1141 | | | +------+ | +-------+ | |
1142 | | |------>| B=2 |--- | : : | |
1143 | | | +------+ \ | : : +-------+ | |
1144 | +-------+ : : \ | +-------+ | | | |
1145 | ---------->| B->2 |------>| | | |
1146 | | +-------+ | CPU 2 | | |
1147 | | : : | | | |
1148 | | : : | | | |
1149 | | +-------+ | | | |
1150 | | | A->0 |------>| 1st | | |
1151 | | +-------+ | | | |
1152 | At this point the read ----> \ rrrrrrrrrrrrrrrrr | | | |
1153 | barrier causes all effects \ +-------+ | | | |
1154 | prior to the storage of B ---->| A->1 |------>| 2nd | | |
1155 | to be perceptible to CPU 2 +-------+ | | | |
1156 | : : +-------+ | |
1157 | ||
1158 | ||
1159 | But it may be that the update to A from CPU 1 becomes perceptible to CPU 2 | |
1160 | before the read barrier completes anyway: | |
1161 | ||
1162 | +-------+ : : : : | |
1163 | | | +------+ +-------+ | |
1164 | | |------>| A=1 |------ --->| A->0 | | |
1165 | | | +------+ \ +-------+ | |
1166 | | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 | | |
1167 | | | +------+ | +-------+ | |
1168 | | |------>| B=2 |--- | : : | |
1169 | | | +------+ \ | : : +-------+ | |
1170 | +-------+ : : \ | +-------+ | | | |
1171 | ---------->| B->2 |------>| | | |
1172 | | +-------+ | CPU 2 | | |
1173 | | : : | | | |
1174 | \ : : | | | |
1175 | \ +-------+ | | | |
1176 | ---->| A->1 |------>| 1st | | |
1177 | +-------+ | | | |
1178 | rrrrrrrrrrrrrrrrr | | | |
1179 | +-------+ | | | |
1180 | | A->1 |------>| 2nd | | |
1181 | +-------+ | | | |
1182 | : : +-------+ | |
1183 | ||
1184 | ||
1185 | The guarantee is that the second load will always come up with A == 1 if the | |
1186 | load of B came up with B == 2. No such guarantee exists for the first load of | |
1187 | A; that may come up with either A == 0 or A == 1. | |
1188 | ||
1189 | ||
1190 | READ MEMORY BARRIERS VS LOAD SPECULATION | |
1191 | ---------------------------------------- | |
1192 | ||
1193 | Many CPUs speculate with loads: that is they see that they will need to load an | |
1194 | item from memory, and they find a time where they're not using the bus for any | |
1195 | other loads, and so do the load in advance - even though they haven't actually | |
1196 | got to that point in the instruction execution flow yet. This permits the | |
1197 | actual load instruction to potentially complete immediately because the CPU | |
1198 | already has the value to hand. | |
1199 | ||
1200 | It may turn out that the CPU didn't actually need the value - perhaps because a | |
1201 | branch circumvented the load - in which case it can discard the value or just | |
1202 | cache it for later use. | |
1203 | ||
1204 | Consider: | |
1205 | ||
e0edc78f | 1206 | CPU 1 CPU 2 |
670bd95e | 1207 | ======================= ======================= |
e0edc78f IM |
1208 | LOAD B |
1209 | DIVIDE } Divide instructions generally | |
1210 | DIVIDE } take a long time to perform | |
1211 | LOAD A | |
670bd95e DH |
1212 | |
1213 | Which might appear as this: | |
1214 | ||
1215 | : : +-------+ | |
1216 | +-------+ | | | |
1217 | --->| B->2 |------>| | | |
1218 | +-------+ | CPU 2 | | |
1219 | : :DIVIDE | | | |
1220 | +-------+ | | | |
1221 | The CPU being busy doing a ---> --->| A->0 |~~~~ | | | |
1222 | division speculates on the +-------+ ~ | | | |
1223 | LOAD of A : : ~ | | | |
1224 | : :DIVIDE | | | |
1225 | : : ~ | | | |
1226 | Once the divisions are complete --> : : ~-->| | | |
1227 | the CPU can then perform the : : | | | |
1228 | LOAD with immediate effect : : +-------+ | |
1229 | ||
1230 | ||
1231 | Placing a read barrier or a data dependency barrier just before the second | |
1232 | load: | |
1233 | ||
e0edc78f | 1234 | CPU 1 CPU 2 |
670bd95e | 1235 | ======================= ======================= |
e0edc78f IM |
1236 | LOAD B |
1237 | DIVIDE | |
1238 | DIVIDE | |
670bd95e | 1239 | <read barrier> |
e0edc78f | 1240 | LOAD A |
670bd95e DH |
1241 | |
1242 | will force any value speculatively obtained to be reconsidered to an extent | |
1243 | dependent on the type of barrier used. If there was no change made to the | |
1244 | speculated memory location, then the speculated value will just be used: | |
1245 | ||
1246 | : : +-------+ | |
1247 | +-------+ | | | |
1248 | --->| B->2 |------>| | | |
1249 | +-------+ | CPU 2 | | |
1250 | : :DIVIDE | | | |
1251 | +-------+ | | | |
1252 | The CPU being busy doing a ---> --->| A->0 |~~~~ | | | |
1253 | division speculates on the +-------+ ~ | | | |
1254 | LOAD of A : : ~ | | | |
1255 | : :DIVIDE | | | |
1256 | : : ~ | | | |
1257 | : : ~ | | | |
1258 | rrrrrrrrrrrrrrrr~ | | | |
1259 | : : ~ | | | |
1260 | : : ~-->| | | |
1261 | : : | | | |
1262 | : : +-------+ | |
1263 | ||
1264 | ||
1265 | but if there was an update or an invalidation from another CPU pending, then | |
1266 | the speculation will be cancelled and the value reloaded: | |
1267 | ||
1268 | : : +-------+ | |
1269 | +-------+ | | | |
1270 | --->| B->2 |------>| | | |
1271 | +-------+ | CPU 2 | | |
1272 | : :DIVIDE | | | |
1273 | +-------+ | | | |
1274 | The CPU being busy doing a ---> --->| A->0 |~~~~ | | | |
1275 | division speculates on the +-------+ ~ | | | |
1276 | LOAD of A : : ~ | | | |
1277 | : :DIVIDE | | | |
1278 | : : ~ | | | |
1279 | : : ~ | | | |
1280 | rrrrrrrrrrrrrrrrr | | | |
1281 | +-------+ | | | |
1282 | The speculation is discarded ---> --->| A->1 |------>| | | |
1283 | and an updated value is +-------+ | | | |
1284 | retrieved : : +-------+ | |
108b42b4 DH |
1285 | |
1286 | ||
241e6663 PM |
1287 | TRANSITIVITY |
1288 | ------------ | |
1289 | ||
1290 | Transitivity is a deeply intuitive notion about ordering that is not | |
1291 | always provided by real computer systems. The following example | |
f36fe1e7 | 1292 | demonstrates transitivity: |
241e6663 PM |
1293 | |
1294 | CPU 1 CPU 2 CPU 3 | |
1295 | ======================= ======================= ======================= | |
1296 | { X = 0, Y = 0 } | |
1297 | STORE X=1 LOAD X STORE Y=1 | |
1298 | <general barrier> <general barrier> | |
1299 | LOAD Y LOAD X | |
1300 | ||
1301 | Suppose that CPU 2's load from X returns 1 and its load from Y returns 0. | |
1302 | This indicates that CPU 2's load from X in some sense follows CPU 1's | |
1303 | store to X and that CPU 2's load from Y in some sense preceded CPU 3's | |
1304 | store to Y. The question is then "Can CPU 3's load from X return 0?" | |
1305 | ||
1306 | Because CPU 2's load from X in some sense came after CPU 1's store, it | |
1307 | is natural to expect that CPU 3's load from X must therefore return 1. | |
1308 | This expectation is an example of transitivity: if a load executing on | |
1309 | CPU A follows a load from the same variable executing on CPU B, then | |
1310 | CPU A's load must either return the same value that CPU B's load did, | |
1311 | or must return some later value. | |
1312 | ||
1313 | In the Linux kernel, use of general memory barriers guarantees | |
1314 | transitivity. Therefore, in the above example, if CPU 2's load from X | |
1315 | returns 1 and its load from Y returns 0, then CPU 3's load from X must | |
1316 | also return 1. | |
1317 | ||
1318 | However, transitivity is -not- guaranteed for read or write barriers. | |
1319 | For example, suppose that CPU 2's general barrier in the above example | |
1320 | is changed to a read barrier as shown below: | |
1321 | ||
1322 | CPU 1 CPU 2 CPU 3 | |
1323 | ======================= ======================= ======================= | |
1324 | { X = 0, Y = 0 } | |
1325 | STORE X=1 LOAD X STORE Y=1 | |
1326 | <read barrier> <general barrier> | |
1327 | LOAD Y LOAD X | |
1328 | ||
1329 | This substitution destroys transitivity: in this example, it is perfectly | |
1330 | legal for CPU 2's load from X to return 1, its load from Y to return 0, | |
1331 | and CPU 3's load from X to return 0. | |
1332 | ||
1333 | The key point is that although CPU 2's read barrier orders its pair | |
1334 | of loads, it does not guarantee to order CPU 1's store. Therefore, if | |
1335 | this example runs on a system where CPUs 1 and 2 share a store buffer | |
1336 | or a level of cache, CPU 2 might have early access to CPU 1's writes. | |
1337 | General barriers are therefore required to ensure that all CPUs agree | |
1338 | on the combined order of CPU 1's and CPU 2's accesses. | |
1339 | ||
c535cc92 PM |
1340 | General barriers provide "global transitivity", so that all CPUs will |
1341 | agree on the order of operations. In contrast, a chain of release-acquire | |
1342 | pairs provides only "local transitivity", so that only those CPUs on | |
1343 | the chain are guaranteed to agree on the combined order of the accesses. | |
1344 | For example, switching to C code in deference to Herman Hollerith: | |
1345 | ||
1346 | int u, v, x, y, z; | |
1347 | ||
1348 | void cpu0(void) | |
1349 | { | |
1350 | r0 = smp_load_acquire(&x); | |
1351 | WRITE_ONCE(u, 1); | |
1352 | smp_store_release(&y, 1); | |
1353 | } | |
1354 | ||
1355 | void cpu1(void) | |
1356 | { | |
1357 | r1 = smp_load_acquire(&y); | |
1358 | r4 = READ_ONCE(v); | |
1359 | r5 = READ_ONCE(u); | |
1360 | smp_store_release(&z, 1); | |
1361 | } | |
1362 | ||
1363 | void cpu2(void) | |
1364 | { | |
1365 | r2 = smp_load_acquire(&z); | |
1366 | smp_store_release(&x, 1); | |
1367 | } | |
1368 | ||
1369 | void cpu3(void) | |
1370 | { | |
1371 | WRITE_ONCE(v, 1); | |
1372 | smp_mb(); | |
1373 | r3 = READ_ONCE(u); | |
1374 | } | |
1375 | ||
1376 | Because cpu0(), cpu1(), and cpu2() participate in a local transitive | |
1377 | chain of smp_store_release()/smp_load_acquire() pairs, the following | |
1378 | outcome is prohibited: | |
1379 | ||
1380 | r0 == 1 && r1 == 1 && r2 == 1 | |
1381 | ||
1382 | Furthermore, because of the release-acquire relationship between cpu0() | |
1383 | and cpu1(), cpu1() must see cpu0()'s writes, so that the following | |
1384 | outcome is prohibited: | |
1385 | ||
1386 | r1 == 1 && r5 == 0 | |
1387 | ||
1388 | However, the transitivity of release-acquire is local to the participating | |
1389 | CPUs and does not apply to cpu3(). Therefore, the following outcome | |
1390 | is possible: | |
1391 | ||
1392 | r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 | |
1393 | ||
37ef0341 PM |
1394 | As an aside, the following outcome is also possible: |
1395 | ||
1396 | r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1 | |
1397 | ||
c535cc92 PM |
1398 | Although cpu0(), cpu1(), and cpu2() will see their respective reads and |
1399 | writes in order, CPUs not involved in the release-acquire chain might | |
1400 | well disagree on the order. This disagreement stems from the fact that | |
1401 | the weak memory-barrier instructions used to implement smp_load_acquire() | |
1402 | and smp_store_release() are not required to order prior stores against | |
1403 | subsequent loads in all cases. This means that cpu3() can see cpu0()'s | |
1404 | store to u as happening -after- cpu1()'s load from v, even though | |
1405 | both cpu0() and cpu1() agree that these two operations occurred in the | |
1406 | intended order. | |
1407 | ||
1408 | However, please keep in mind that smp_load_acquire() is not magic. | |
1409 | In particular, it simply reads from its argument with ordering. It does | |
1410 | -not- ensure that any particular value will be read. Therefore, the | |
1411 | following outcome is possible: | |
1412 | ||
1413 | r0 == 0 && r1 == 0 && r2 == 0 && r5 == 0 | |
1414 | ||
1415 | Note that this outcome can happen even on a mythical sequentially | |
1416 | consistent system where nothing is ever reordered. | |
1417 | ||
1418 | To reiterate, if your code requires global transitivity, use general | |
1419 | barriers throughout. | |
241e6663 PM |
1420 | |
1421 | ||
108b42b4 DH |
1422 | ======================== |
1423 | EXPLICIT KERNEL BARRIERS | |
1424 | ======================== | |
1425 | ||
1426 | The Linux kernel has a variety of different barriers that act at different | |
1427 | levels: | |
1428 | ||
1429 | (*) Compiler barrier. | |
1430 | ||
1431 | (*) CPU memory barriers. | |
1432 | ||
1433 | (*) MMIO write barrier. | |
1434 | ||
1435 | ||
1436 | COMPILER BARRIER | |
1437 | ---------------- | |
1438 | ||
1439 | The Linux kernel has an explicit compiler barrier function that prevents the | |
1440 | compiler from moving the memory accesses either side of it to the other side: | |
1441 | ||
1442 | barrier(); | |
1443 | ||
9af194ce PM |
1444 | This is a general barrier -- there are no read-read or write-write |
1445 | variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be | |
1446 | thought of as weak forms of barrier() that affect only the specific | |
1447 | accesses flagged by the READ_ONCE() or WRITE_ONCE(). | |
108b42b4 | 1448 | |
692118da PM |
1449 | The barrier() function has the following effects: |
1450 | ||
1451 | (*) Prevents the compiler from reordering accesses following the | |
1452 | barrier() to precede any accesses preceding the barrier(). | |
1453 | One example use for this property is to ease communication between | |
1454 | interrupt-handler code and the code that was interrupted. | |
1455 | ||
1456 | (*) Within a loop, forces the compiler to load the variables used | |
1457 | in that loop's conditional on each pass through that loop. | |
1458 | ||
9af194ce PM |
1459 | The READ_ONCE() and WRITE_ONCE() functions can prevent any number of |
1460 | optimizations that, while perfectly safe in single-threaded code, can | |
1461 | be fatal in concurrent code. Here are some examples of these sorts | |
1462 | of optimizations: | |
692118da | 1463 | |
449f7413 PM |
1464 | (*) The compiler is within its rights to reorder loads and stores |
1465 | to the same variable, and in some cases, the CPU is within its | |
1466 | rights to reorder loads to the same variable. This means that | |
1467 | the following code: | |
1468 | ||
1469 | a[0] = x; | |
1470 | a[1] = x; | |
1471 | ||
1472 | Might result in an older value of x stored in a[1] than in a[0]. | |
1473 | Prevent both the compiler and the CPU from doing this as follows: | |
1474 | ||
9af194ce PM |
1475 | a[0] = READ_ONCE(x); |
1476 | a[1] = READ_ONCE(x); | |
449f7413 | 1477 | |
9af194ce PM |
1478 | In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for |
1479 | accesses from multiple CPUs to a single variable. | |
449f7413 | 1480 | |
692118da PM |
1481 | (*) The compiler is within its rights to merge successive loads from |
1482 | the same variable. Such merging can cause the compiler to "optimize" | |
1483 | the following code: | |
1484 | ||
1485 | while (tmp = a) | |
1486 | do_something_with(tmp); | |
1487 | ||
1488 | into the following code, which, although in some sense legitimate | |
1489 | for single-threaded code, is almost certainly not what the developer | |
1490 | intended: | |
1491 | ||
1492 | if (tmp = a) | |
1493 | for (;;) | |
1494 | do_something_with(tmp); | |
1495 | ||
9af194ce | 1496 | Use READ_ONCE() to prevent the compiler from doing this to you: |
692118da | 1497 | |
9af194ce | 1498 | while (tmp = READ_ONCE(a)) |
692118da PM |
1499 | do_something_with(tmp); |
1500 | ||
1501 | (*) The compiler is within its rights to reload a variable, for example, | |
1502 | in cases where high register pressure prevents the compiler from | |
1503 | keeping all data of interest in registers. The compiler might | |
1504 | therefore optimize the variable 'tmp' out of our previous example: | |
1505 | ||
1506 | while (tmp = a) | |
1507 | do_something_with(tmp); | |
1508 | ||
1509 | This could result in the following code, which is perfectly safe in | |
1510 | single-threaded code, but can be fatal in concurrent code: | |
1511 | ||
1512 | while (a) | |
1513 | do_something_with(a); | |
1514 | ||
1515 | For example, the optimized version of this code could result in | |
1516 | passing a zero to do_something_with() in the case where the variable | |
1517 | a was modified by some other CPU between the "while" statement and | |
1518 | the call to do_something_with(). | |
1519 | ||
9af194ce | 1520 | Again, use READ_ONCE() to prevent the compiler from doing this: |
692118da | 1521 | |
9af194ce | 1522 | while (tmp = READ_ONCE(a)) |
692118da PM |
1523 | do_something_with(tmp); |
1524 | ||
1525 | Note that if the compiler runs short of registers, it might save | |
1526 | tmp onto the stack. The overhead of this saving and later restoring | |
1527 | is why compilers reload variables. Doing so is perfectly safe for | |
1528 | single-threaded code, so you need to tell the compiler about cases | |
1529 | where it is not safe. | |
1530 | ||
1531 | (*) The compiler is within its rights to omit a load entirely if it knows | |
1532 | what the value will be. For example, if the compiler can prove that | |
1533 | the value of variable 'a' is always zero, it can optimize this code: | |
1534 | ||
1535 | while (tmp = a) | |
1536 | do_something_with(tmp); | |
1537 | ||
1538 | Into this: | |
1539 | ||
1540 | do { } while (0); | |
1541 | ||
9af194ce PM |
1542 | This transformation is a win for single-threaded code because it |
1543 | gets rid of a load and a branch. The problem is that the compiler | |
1544 | will carry out its proof assuming that the current CPU is the only | |
1545 | one updating variable 'a'. If variable 'a' is shared, then the | |
1546 | compiler's proof will be erroneous. Use READ_ONCE() to tell the | |
1547 | compiler that it doesn't know as much as it thinks it does: | |
692118da | 1548 | |
9af194ce | 1549 | while (tmp = READ_ONCE(a)) |
692118da PM |
1550 | do_something_with(tmp); |
1551 | ||
1552 | But please note that the compiler is also closely watching what you | |
9af194ce | 1553 | do with the value after the READ_ONCE(). For example, suppose you |
692118da PM |
1554 | do the following and MAX is a preprocessor macro with the value 1: |
1555 | ||
9af194ce | 1556 | while ((tmp = READ_ONCE(a)) % MAX) |
692118da PM |
1557 | do_something_with(tmp); |
1558 | ||
1559 | Then the compiler knows that the result of the "%" operator applied | |
1560 | to MAX will always be zero, again allowing the compiler to optimize | |
1561 | the code into near-nonexistence. (It will still load from the | |
1562 | variable 'a'.) | |
1563 | ||
1564 | (*) Similarly, the compiler is within its rights to omit a store entirely | |
1565 | if it knows that the variable already has the value being stored. | |
1566 | Again, the compiler assumes that the current CPU is the only one | |
1567 | storing into the variable, which can cause the compiler to do the | |
1568 | wrong thing for shared variables. For example, suppose you have | |
1569 | the following: | |
1570 | ||
1571 | a = 0; | |
65f95ff2 | 1572 | ... Code that does not store to variable a ... |
692118da PM |
1573 | a = 0; |
1574 | ||
1575 | The compiler sees that the value of variable 'a' is already zero, so | |
1576 | it might well omit the second store. This would come as a fatal | |
1577 | surprise if some other CPU might have stored to variable 'a' in the | |
1578 | meantime. | |
1579 | ||
9af194ce | 1580 | Use WRITE_ONCE() to prevent the compiler from making this sort of |
692118da PM |
1581 | wrong guess: |
1582 | ||
9af194ce | 1583 | WRITE_ONCE(a, 0); |
65f95ff2 | 1584 | ... Code that does not store to variable a ... |
9af194ce | 1585 | WRITE_ONCE(a, 0); |
692118da PM |
1586 | |
1587 | (*) The compiler is within its rights to reorder memory accesses unless | |
1588 | you tell it not to. For example, consider the following interaction | |
1589 | between process-level code and an interrupt handler: | |
1590 | ||
1591 | void process_level(void) | |
1592 | { | |
1593 | msg = get_message(); | |
1594 | flag = true; | |
1595 | } | |
1596 | ||
1597 | void interrupt_handler(void) | |
1598 | { | |
1599 | if (flag) | |
1600 | process_message(msg); | |
1601 | } | |
1602 | ||
df5cbb27 | 1603 | There is nothing to prevent the compiler from transforming |
692118da PM |
1604 | process_level() to the following, in fact, this might well be a |
1605 | win for single-threaded code: | |
1606 | ||
1607 | void process_level(void) | |
1608 | { | |
1609 | flag = true; | |
1610 | msg = get_message(); | |
1611 | } | |
1612 | ||
1613 | If the interrupt occurs between these two statement, then | |
9af194ce | 1614 | interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE() |
692118da PM |
1615 | to prevent this as follows: |
1616 | ||
1617 | void process_level(void) | |
1618 | { | |
9af194ce PM |
1619 | WRITE_ONCE(msg, get_message()); |
1620 | WRITE_ONCE(flag, true); | |
692118da PM |
1621 | } |
1622 | ||
1623 | void interrupt_handler(void) | |
1624 | { | |
9af194ce PM |
1625 | if (READ_ONCE(flag)) |
1626 | process_message(READ_ONCE(msg)); | |
692118da PM |
1627 | } |
1628 | ||
9af194ce PM |
1629 | Note that the READ_ONCE() and WRITE_ONCE() wrappers in |
1630 | interrupt_handler() are needed if this interrupt handler can itself | |
1631 | be interrupted by something that also accesses 'flag' and 'msg', | |
1632 | for example, a nested interrupt or an NMI. Otherwise, READ_ONCE() | |
1633 | and WRITE_ONCE() are not needed in interrupt_handler() other than | |
1634 | for documentation purposes. (Note also that nested interrupts | |
1635 | do not typically occur in modern Linux kernels, in fact, if an | |
1636 | interrupt handler returns with interrupts enabled, you will get a | |
1637 | WARN_ONCE() splat.) | |
1638 | ||
1639 | You should assume that the compiler can move READ_ONCE() and | |
1640 | WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(), | |
1641 | barrier(), or similar primitives. | |
1642 | ||
1643 | This effect could also be achieved using barrier(), but READ_ONCE() | |
1644 | and WRITE_ONCE() are more selective: With READ_ONCE() and | |
1645 | WRITE_ONCE(), the compiler need only forget the contents of the | |
1646 | indicated memory locations, while with barrier() the compiler must | |
1647 | discard the value of all memory locations that it has currented | |
1648 | cached in any machine registers. Of course, the compiler must also | |
1649 | respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur, | |
1650 | though the CPU of course need not do so. | |
692118da PM |
1651 | |
1652 | (*) The compiler is within its rights to invent stores to a variable, | |
1653 | as in the following example: | |
1654 | ||
1655 | if (a) | |
1656 | b = a; | |
1657 | else | |
1658 | b = 42; | |
1659 | ||
1660 | The compiler might save a branch by optimizing this as follows: | |
1661 | ||
1662 | b = 42; | |
1663 | if (a) | |
1664 | b = a; | |
1665 | ||
1666 | In single-threaded code, this is not only safe, but also saves | |
1667 | a branch. Unfortunately, in concurrent code, this optimization | |
1668 | could cause some other CPU to see a spurious value of 42 -- even | |
1669 | if variable 'a' was never zero -- when loading variable 'b'. | |
9af194ce | 1670 | Use WRITE_ONCE() to prevent this as follows: |
692118da PM |
1671 | |
1672 | if (a) | |
9af194ce | 1673 | WRITE_ONCE(b, a); |
692118da | 1674 | else |
9af194ce | 1675 | WRITE_ONCE(b, 42); |
692118da PM |
1676 | |
1677 | The compiler can also invent loads. These are usually less | |
1678 | damaging, but they can result in cache-line bouncing and thus in | |
9af194ce | 1679 | poor performance and scalability. Use READ_ONCE() to prevent |
692118da PM |
1680 | invented loads. |
1681 | ||
1682 | (*) For aligned memory locations whose size allows them to be accessed | |
1683 | with a single memory-reference instruction, prevents "load tearing" | |
1684 | and "store tearing," in which a single large access is replaced by | |
1685 | multiple smaller accesses. For example, given an architecture having | |
1686 | 16-bit store instructions with 7-bit immediate fields, the compiler | |
1687 | might be tempted to use two 16-bit store-immediate instructions to | |
1688 | implement the following 32-bit store: | |
1689 | ||
1690 | p = 0x00010002; | |
1691 | ||
1692 | Please note that GCC really does use this sort of optimization, | |
1693 | which is not surprising given that it would likely take more | |
1694 | than two instructions to build the constant and then store it. | |
1695 | This optimization can therefore be a win in single-threaded code. | |
1696 | In fact, a recent bug (since fixed) caused GCC to incorrectly use | |
1697 | this optimization in a volatile store. In the absence of such bugs, | |
9af194ce | 1698 | use of WRITE_ONCE() prevents store tearing in the following example: |
692118da | 1699 | |
9af194ce | 1700 | WRITE_ONCE(p, 0x00010002); |
692118da PM |
1701 | |
1702 | Use of packed structures can also result in load and store tearing, | |
1703 | as in this example: | |
1704 | ||
1705 | struct __attribute__((__packed__)) foo { | |
1706 | short a; | |
1707 | int b; | |
1708 | short c; | |
1709 | }; | |
1710 | struct foo foo1, foo2; | |
1711 | ... | |
1712 | ||
1713 | foo2.a = foo1.a; | |
1714 | foo2.b = foo1.b; | |
1715 | foo2.c = foo1.c; | |
1716 | ||
9af194ce PM |
1717 | Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no |
1718 | volatile markings, the compiler would be well within its rights to | |
1719 | implement these three assignment statements as a pair of 32-bit | |
1720 | loads followed by a pair of 32-bit stores. This would result in | |
1721 | load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE() | |
1722 | and WRITE_ONCE() again prevent tearing in this example: | |
692118da PM |
1723 | |
1724 | foo2.a = foo1.a; | |
9af194ce | 1725 | WRITE_ONCE(foo2.b, READ_ONCE(foo1.b)); |
692118da PM |
1726 | foo2.c = foo1.c; |
1727 | ||
9af194ce PM |
1728 | All that aside, it is never necessary to use READ_ONCE() and |
1729 | WRITE_ONCE() on a variable that has been marked volatile. For example, | |
1730 | because 'jiffies' is marked volatile, it is never necessary to | |
1731 | say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and | |
1732 | WRITE_ONCE() are implemented as volatile casts, which has no effect when | |
1733 | its argument is already marked volatile. | |
692118da PM |
1734 | |
1735 | Please note that these compiler barriers have no direct effect on the CPU, | |
1736 | which may then reorder things however it wishes. | |
108b42b4 DH |
1737 | |
1738 | ||
1739 | CPU MEMORY BARRIERS | |
1740 | ------------------- | |
1741 | ||
1742 | The Linux kernel has eight basic CPU memory barriers: | |
1743 | ||
1744 | TYPE MANDATORY SMP CONDITIONAL | |
1745 | =============== ======================= =========================== | |
1746 | GENERAL mb() smp_mb() | |
1747 | WRITE wmb() smp_wmb() | |
1748 | READ rmb() smp_rmb() | |
1749 | DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends() | |
1750 | ||
1751 | ||
73f10281 | 1752 | All memory barriers except the data dependency barriers imply a compiler |
0b6fa347 | 1753 | barrier. Data dependencies do not impose any additional compiler ordering. |
73f10281 | 1754 | |
9af194ce PM |
1755 | Aside: In the case of data dependencies, the compiler would be expected |
1756 | to issue the loads in the correct order (eg. `a[b]` would have to load | |
1757 | the value of b before loading a[b]), however there is no guarantee in | |
1758 | the C specification that the compiler may not speculate the value of b | |
1759 | (eg. is equal to 1) and load a before b (eg. tmp = a[1]; if (b != 1) | |
0b6fa347 SP |
1760 | tmp = a[b]; ). There is also the problem of a compiler reloading b after |
1761 | having loaded a[b], thus having a newer copy of b than a[b]. A consensus | |
9af194ce PM |
1762 | has not yet been reached about these problems, however the READ_ONCE() |
1763 | macro is a good place to start looking. | |
108b42b4 DH |
1764 | |
1765 | SMP memory barriers are reduced to compiler barriers on uniprocessor compiled | |
81fc6323 | 1766 | systems because it is assumed that a CPU will appear to be self-consistent, |
108b42b4 | 1767 | and will order overlapping accesses correctly with respect to itself. |
6a65d263 | 1768 | However, see the subsection on "Virtual Machine Guests" below. |
108b42b4 DH |
1769 | |
1770 | [!] Note that SMP memory barriers _must_ be used to control the ordering of | |
1771 | references to shared memory on SMP systems, though the use of locking instead | |
1772 | is sufficient. | |
1773 | ||
1774 | Mandatory barriers should not be used to control SMP effects, since mandatory | |
6a65d263 MT |
1775 | barriers impose unnecessary overhead on both SMP and UP systems. They may, |
1776 | however, be used to control MMIO effects on accesses through relaxed memory I/O | |
1777 | windows. These barriers are required even on non-SMP systems as they affect | |
1778 | the order in which memory operations appear to a device by prohibiting both the | |
1779 | compiler and the CPU from reordering them. | |
108b42b4 DH |
1780 | |
1781 | ||
1782 | There are some more advanced barrier functions: | |
1783 | ||
b92b8b35 | 1784 | (*) smp_store_mb(var, value) |
108b42b4 | 1785 | |
75b2bd55 | 1786 | This assigns the value to the variable and then inserts a full memory |
2d142e59 DB |
1787 | barrier after it. It isn't guaranteed to insert anything more than a |
1788 | compiler barrier in a UP compilation. | |
108b42b4 DH |
1789 | |
1790 | ||
1b15611e PZ |
1791 | (*) smp_mb__before_atomic(); |
1792 | (*) smp_mb__after_atomic(); | |
108b42b4 | 1793 | |
1b15611e PZ |
1794 | These are for use with atomic (such as add, subtract, increment and |
1795 | decrement) functions that don't return a value, especially when used for | |
1796 | reference counting. These functions do not imply memory barriers. | |
1797 | ||
1798 | These are also used for atomic bitop functions that do not return a | |
1799 | value (such as set_bit and clear_bit). | |
108b42b4 DH |
1800 | |
1801 | As an example, consider a piece of code that marks an object as being dead | |
1802 | and then decrements the object's reference count: | |
1803 | ||
1804 | obj->dead = 1; | |
1b15611e | 1805 | smp_mb__before_atomic(); |
108b42b4 DH |
1806 | atomic_dec(&obj->ref_count); |
1807 | ||
1808 | This makes sure that the death mark on the object is perceived to be set | |
1809 | *before* the reference counter is decremented. | |
1810 | ||
1811 | See Documentation/atomic_ops.txt for more information. See the "Atomic | |
1812 | operations" subsection for information on where to use these. | |
1813 | ||
1814 | ||
ad2ad5d3 | 1815 | (*) lockless_dereference(); |
0b6fa347 | 1816 | |
ad2ad5d3 PM |
1817 | This can be thought of as a pointer-fetch wrapper around the |
1818 | smp_read_barrier_depends() data-dependency barrier. | |
1819 | ||
1820 | This is also similar to rcu_dereference(), but in cases where | |
1821 | object lifetime is handled by some mechanism other than RCU, for | |
1822 | example, when the objects removed only when the system goes down. | |
1823 | In addition, lockless_dereference() is used in some data structures | |
1824 | that can be used both with and without RCU. | |
1825 | ||
1826 | ||
1077fa36 AD |
1827 | (*) dma_wmb(); |
1828 | (*) dma_rmb(); | |
1829 | ||
1830 | These are for use with consistent memory to guarantee the ordering | |
1831 | of writes or reads of shared memory accessible to both the CPU and a | |
1832 | DMA capable device. | |
1833 | ||
1834 | For example, consider a device driver that shares memory with a device | |
1835 | and uses a descriptor status value to indicate if the descriptor belongs | |
1836 | to the device or the CPU, and a doorbell to notify it when new | |
1837 | descriptors are available: | |
1838 | ||
1839 | if (desc->status != DEVICE_OWN) { | |
1840 | /* do not read data until we own descriptor */ | |
1841 | dma_rmb(); | |
1842 | ||
1843 | /* read/modify data */ | |
1844 | read_data = desc->data; | |
1845 | desc->data = write_data; | |
1846 | ||
1847 | /* flush modifications before status update */ | |
1848 | dma_wmb(); | |
1849 | ||
1850 | /* assign ownership */ | |
1851 | desc->status = DEVICE_OWN; | |
1852 | ||
1853 | /* force memory to sync before notifying device via MMIO */ | |
1854 | wmb(); | |
1855 | ||
1856 | /* notify device of new descriptors */ | |
1857 | writel(DESC_NOTIFY, doorbell); | |
1858 | } | |
1859 | ||
1860 | The dma_rmb() allows us guarantee the device has released ownership | |
7a458007 | 1861 | before we read the data from the descriptor, and the dma_wmb() allows |
1077fa36 AD |
1862 | us to guarantee the data is written to the descriptor before the device |
1863 | can see it now has ownership. The wmb() is needed to guarantee that the | |
1864 | cache coherent memory writes have completed before attempting a write to | |
1865 | the cache incoherent MMIO region. | |
1866 | ||
1867 | See Documentation/DMA-API.txt for more information on consistent memory. | |
1868 | ||
108b42b4 DH |
1869 | MMIO WRITE BARRIER |
1870 | ------------------ | |
1871 | ||
1872 | The Linux kernel also has a special barrier for use with memory-mapped I/O | |
1873 | writes: | |
1874 | ||
1875 | mmiowb(); | |
1876 | ||
1877 | This is a variation on the mandatory write barrier that causes writes to weakly | |
1878 | ordered I/O regions to be partially ordered. Its effects may go beyond the | |
1879 | CPU->Hardware interface and actually affect the hardware at some level. | |
1880 | ||
166bda71 | 1881 | See the subsection "Acquires vs I/O accesses" for more information. |
108b42b4 DH |
1882 | |
1883 | ||
1884 | =============================== | |
1885 | IMPLICIT KERNEL MEMORY BARRIERS | |
1886 | =============================== | |
1887 | ||
1888 | Some of the other functions in the linux kernel imply memory barriers, amongst | |
670bd95e | 1889 | which are locking and scheduling functions. |
108b42b4 DH |
1890 | |
1891 | This specification is a _minimum_ guarantee; any particular architecture may | |
1892 | provide more substantial guarantees, but these may not be relied upon outside | |
1893 | of arch specific code. | |
1894 | ||
1895 | ||
166bda71 SP |
1896 | LOCK ACQUISITION FUNCTIONS |
1897 | -------------------------- | |
108b42b4 DH |
1898 | |
1899 | The Linux kernel has a number of locking constructs: | |
1900 | ||
1901 | (*) spin locks | |
1902 | (*) R/W spin locks | |
1903 | (*) mutexes | |
1904 | (*) semaphores | |
1905 | (*) R/W semaphores | |
108b42b4 | 1906 | |
2e4f5382 | 1907 | In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations |
108b42b4 DH |
1908 | for each construct. These operations all imply certain barriers: |
1909 | ||
2e4f5382 | 1910 | (1) ACQUIRE operation implication: |
108b42b4 | 1911 | |
2e4f5382 PZ |
1912 | Memory operations issued after the ACQUIRE will be completed after the |
1913 | ACQUIRE operation has completed. | |
108b42b4 | 1914 | |
8dd853d7 PM |
1915 | Memory operations issued before the ACQUIRE may be completed after |
1916 | the ACQUIRE operation has completed. An smp_mb__before_spinlock(), | |
d956028e | 1917 | combined with a following ACQUIRE, orders prior stores against |
0b6fa347 | 1918 | subsequent loads and stores. Note that this is weaker than smp_mb()! |
d956028e | 1919 | The smp_mb__before_spinlock() primitive is free on many architectures. |
108b42b4 | 1920 | |
2e4f5382 | 1921 | (2) RELEASE operation implication: |
108b42b4 | 1922 | |
2e4f5382 PZ |
1923 | Memory operations issued before the RELEASE will be completed before the |
1924 | RELEASE operation has completed. | |
108b42b4 | 1925 | |
2e4f5382 PZ |
1926 | Memory operations issued after the RELEASE may be completed before the |
1927 | RELEASE operation has completed. | |
108b42b4 | 1928 | |
2e4f5382 | 1929 | (3) ACQUIRE vs ACQUIRE implication: |
108b42b4 | 1930 | |
2e4f5382 PZ |
1931 | All ACQUIRE operations issued before another ACQUIRE operation will be |
1932 | completed before that ACQUIRE operation. | |
108b42b4 | 1933 | |
2e4f5382 | 1934 | (4) ACQUIRE vs RELEASE implication: |
108b42b4 | 1935 | |
2e4f5382 PZ |
1936 | All ACQUIRE operations issued before a RELEASE operation will be |
1937 | completed before the RELEASE operation. | |
108b42b4 | 1938 | |
2e4f5382 | 1939 | (5) Failed conditional ACQUIRE implication: |
108b42b4 | 1940 | |
2e4f5382 PZ |
1941 | Certain locking variants of the ACQUIRE operation may fail, either due to |
1942 | being unable to get the lock immediately, or due to receiving an unblocked | |
108b42b4 DH |
1943 | signal whilst asleep waiting for the lock to become available. Failed |
1944 | locks do not imply any sort of barrier. | |
1945 | ||
2e4f5382 PZ |
1946 | [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only |
1947 | one-way barriers is that the effects of instructions outside of a critical | |
1948 | section may seep into the inside of the critical section. | |
108b42b4 | 1949 | |
2e4f5382 PZ |
1950 | An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier |
1951 | because it is possible for an access preceding the ACQUIRE to happen after the | |
1952 | ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and | |
1953 | the two accesses can themselves then cross: | |
670bd95e DH |
1954 | |
1955 | *A = a; | |
2e4f5382 PZ |
1956 | ACQUIRE M |
1957 | RELEASE M | |
670bd95e DH |
1958 | *B = b; |
1959 | ||
1960 | may occur as: | |
1961 | ||
2e4f5382 | 1962 | ACQUIRE M, STORE *B, STORE *A, RELEASE M |
17eb88e0 | 1963 | |
8dd853d7 PM |
1964 | When the ACQUIRE and RELEASE are a lock acquisition and release, |
1965 | respectively, this same reordering can occur if the lock's ACQUIRE and | |
1966 | RELEASE are to the same lock variable, but only from the perspective of | |
1967 | another CPU not holding that lock. In short, a ACQUIRE followed by an | |
1968 | RELEASE may -not- be assumed to be a full memory barrier. | |
1969 | ||
12d560f4 PM |
1970 | Similarly, the reverse case of a RELEASE followed by an ACQUIRE does |
1971 | not imply a full memory barrier. Therefore, the CPU's execution of the | |
1972 | critical sections corresponding to the RELEASE and the ACQUIRE can cross, | |
1973 | so that: | |
17eb88e0 PM |
1974 | |
1975 | *A = a; | |
2e4f5382 PZ |
1976 | RELEASE M |
1977 | ACQUIRE N | |
17eb88e0 PM |
1978 | *B = b; |
1979 | ||
1980 | could occur as: | |
1981 | ||
2e4f5382 | 1982 | ACQUIRE N, STORE *B, STORE *A, RELEASE M |
17eb88e0 | 1983 | |
8dd853d7 PM |
1984 | It might appear that this reordering could introduce a deadlock. |
1985 | However, this cannot happen because if such a deadlock threatened, | |
1986 | the RELEASE would simply complete, thereby avoiding the deadlock. | |
1987 | ||
1988 | Why does this work? | |
1989 | ||
1990 | One key point is that we are only talking about the CPU doing | |
1991 | the reordering, not the compiler. If the compiler (or, for | |
1992 | that matter, the developer) switched the operations, deadlock | |
1993 | -could- occur. | |
1994 | ||
1995 | But suppose the CPU reordered the operations. In this case, | |
1996 | the unlock precedes the lock in the assembly code. The CPU | |
1997 | simply elected to try executing the later lock operation first. | |
1998 | If there is a deadlock, this lock operation will simply spin (or | |
1999 | try to sleep, but more on that later). The CPU will eventually | |
2000 | execute the unlock operation (which preceded the lock operation | |
2001 | in the assembly code), which will unravel the potential deadlock, | |
2002 | allowing the lock operation to succeed. | |
2003 | ||
2004 | But what if the lock is a sleeplock? In that case, the code will | |
2005 | try to enter the scheduler, where it will eventually encounter | |
2006 | a memory barrier, which will force the earlier unlock operation | |
2007 | to complete, again unraveling the deadlock. There might be | |
2008 | a sleep-unlock race, but the locking primitive needs to resolve | |
2009 | such races properly in any case. | |
2010 | ||
108b42b4 DH |
2011 | Locks and semaphores may not provide any guarantee of ordering on UP compiled |
2012 | systems, and so cannot be counted on in such a situation to actually achieve | |
2013 | anything at all - especially with respect to I/O accesses - unless combined | |
2014 | with interrupt disabling operations. | |
2015 | ||
2016 | See also the section on "Inter-CPU locking barrier effects". | |
2017 | ||
2018 | ||
2019 | As an example, consider the following: | |
2020 | ||
2021 | *A = a; | |
2022 | *B = b; | |
2e4f5382 | 2023 | ACQUIRE |
108b42b4 DH |
2024 | *C = c; |
2025 | *D = d; | |
2e4f5382 | 2026 | RELEASE |
108b42b4 DH |
2027 | *E = e; |
2028 | *F = f; | |
2029 | ||
2030 | The following sequence of events is acceptable: | |
2031 | ||
2e4f5382 | 2032 | ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE |
108b42b4 DH |
2033 | |
2034 | [+] Note that {*F,*A} indicates a combined access. | |
2035 | ||
2036 | But none of the following are: | |
2037 | ||
2e4f5382 PZ |
2038 | {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E |
2039 | *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F | |
2040 | *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F | |
2041 | *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E | |
108b42b4 DH |
2042 | |
2043 | ||
2044 | ||
2045 | INTERRUPT DISABLING FUNCTIONS | |
2046 | ----------------------------- | |
2047 | ||
2e4f5382 PZ |
2048 | Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts |
2049 | (RELEASE equivalent) will act as compiler barriers only. So if memory or I/O | |
108b42b4 DH |
2050 | barriers are required in such a situation, they must be provided from some |
2051 | other means. | |
2052 | ||
2053 | ||
50fa610a DH |
2054 | SLEEP AND WAKE-UP FUNCTIONS |
2055 | --------------------------- | |
2056 | ||
2057 | Sleeping and waking on an event flagged in global data can be viewed as an | |
2058 | interaction between two pieces of data: the task state of the task waiting for | |
2059 | the event and the global data used to indicate the event. To make sure that | |
2060 | these appear to happen in the right order, the primitives to begin the process | |
2061 | of going to sleep, and the primitives to initiate a wake up imply certain | |
2062 | barriers. | |
2063 | ||
2064 | Firstly, the sleeper normally follows something like this sequence of events: | |
2065 | ||
2066 | for (;;) { | |
2067 | set_current_state(TASK_UNINTERRUPTIBLE); | |
2068 | if (event_indicated) | |
2069 | break; | |
2070 | schedule(); | |
2071 | } | |
2072 | ||
2073 | A general memory barrier is interpolated automatically by set_current_state() | |
2074 | after it has altered the task state: | |
2075 | ||
2076 | CPU 1 | |
2077 | =============================== | |
2078 | set_current_state(); | |
b92b8b35 | 2079 | smp_store_mb(); |
50fa610a DH |
2080 | STORE current->state |
2081 | <general barrier> | |
2082 | LOAD event_indicated | |
2083 | ||
2084 | set_current_state() may be wrapped by: | |
2085 | ||
2086 | prepare_to_wait(); | |
2087 | prepare_to_wait_exclusive(); | |
2088 | ||
2089 | which therefore also imply a general memory barrier after setting the state. | |
2090 | The whole sequence above is available in various canned forms, all of which | |
2091 | interpolate the memory barrier in the right place: | |
2092 | ||
2093 | wait_event(); | |
2094 | wait_event_interruptible(); | |
2095 | wait_event_interruptible_exclusive(); | |
2096 | wait_event_interruptible_timeout(); | |
2097 | wait_event_killable(); | |
2098 | wait_event_timeout(); | |
2099 | wait_on_bit(); | |
2100 | wait_on_bit_lock(); | |
2101 | ||
2102 | ||
2103 | Secondly, code that performs a wake up normally follows something like this: | |
2104 | ||
2105 | event_indicated = 1; | |
2106 | wake_up(&event_wait_queue); | |
2107 | ||
2108 | or: | |
2109 | ||
2110 | event_indicated = 1; | |
2111 | wake_up_process(event_daemon); | |
2112 | ||
0b6fa347 SP |
2113 | A write memory barrier is implied by wake_up() and co. if and only if they |
2114 | wake something up. The barrier occurs before the task state is cleared, and so | |
2115 | sits between the STORE to indicate the event and the STORE to set TASK_RUNNING: | |
50fa610a DH |
2116 | |
2117 | CPU 1 CPU 2 | |
2118 | =============================== =============================== | |
2119 | set_current_state(); STORE event_indicated | |
b92b8b35 | 2120 | smp_store_mb(); wake_up(); |
50fa610a DH |
2121 | STORE current->state <write barrier> |
2122 | <general barrier> STORE current->state | |
2123 | LOAD event_indicated | |
2124 | ||
5726ce06 PM |
2125 | To repeat, this write memory barrier is present if and only if something |
2126 | is actually awakened. To see this, consider the following sequence of | |
2127 | events, where X and Y are both initially zero: | |
2128 | ||
2129 | CPU 1 CPU 2 | |
2130 | =============================== =============================== | |
2131 | X = 1; STORE event_indicated | |
2132 | smp_mb(); wake_up(); | |
2133 | Y = 1; wait_event(wq, Y == 1); | |
2134 | wake_up(); load from Y sees 1, no memory barrier | |
2135 | load from X might see 0 | |
2136 | ||
2137 | In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed | |
2138 | to see 1. | |
2139 | ||
50fa610a DH |
2140 | The available waker functions include: |
2141 | ||
2142 | complete(); | |
2143 | wake_up(); | |
2144 | wake_up_all(); | |
2145 | wake_up_bit(); | |
2146 | wake_up_interruptible(); | |
2147 | wake_up_interruptible_all(); | |
2148 | wake_up_interruptible_nr(); | |
2149 | wake_up_interruptible_poll(); | |
2150 | wake_up_interruptible_sync(); | |
2151 | wake_up_interruptible_sync_poll(); | |
2152 | wake_up_locked(); | |
2153 | wake_up_locked_poll(); | |
2154 | wake_up_nr(); | |
2155 | wake_up_poll(); | |
2156 | wake_up_process(); | |
2157 | ||
2158 | ||
2159 | [!] Note that the memory barriers implied by the sleeper and the waker do _not_ | |
2160 | order multiple stores before the wake-up with respect to loads of those stored | |
2161 | values after the sleeper has called set_current_state(). For instance, if the | |
2162 | sleeper does: | |
2163 | ||
2164 | set_current_state(TASK_INTERRUPTIBLE); | |
2165 | if (event_indicated) | |
2166 | break; | |
2167 | __set_current_state(TASK_RUNNING); | |
2168 | do_something(my_data); | |
2169 | ||
2170 | and the waker does: | |
2171 | ||
2172 | my_data = value; | |
2173 | event_indicated = 1; | |
2174 | wake_up(&event_wait_queue); | |
2175 | ||
2176 | there's no guarantee that the change to event_indicated will be perceived by | |
2177 | the sleeper as coming after the change to my_data. In such a circumstance, the | |
2178 | code on both sides must interpolate its own memory barriers between the | |
2179 | separate data accesses. Thus the above sleeper ought to do: | |
2180 | ||
2181 | set_current_state(TASK_INTERRUPTIBLE); | |
2182 | if (event_indicated) { | |
2183 | smp_rmb(); | |
2184 | do_something(my_data); | |
2185 | } | |
2186 | ||
2187 | and the waker should do: | |
2188 | ||
2189 | my_data = value; | |
2190 | smp_wmb(); | |
2191 | event_indicated = 1; | |
2192 | wake_up(&event_wait_queue); | |
2193 | ||
2194 | ||
108b42b4 DH |
2195 | MISCELLANEOUS FUNCTIONS |
2196 | ----------------------- | |
2197 | ||
2198 | Other functions that imply barriers: | |
2199 | ||
2200 | (*) schedule() and similar imply full memory barriers. | |
2201 | ||
108b42b4 | 2202 | |
2e4f5382 PZ |
2203 | =================================== |
2204 | INTER-CPU ACQUIRING BARRIER EFFECTS | |
2205 | =================================== | |
108b42b4 DH |
2206 | |
2207 | On SMP systems locking primitives give a more substantial form of barrier: one | |
2208 | that does affect memory access ordering on other CPUs, within the context of | |
2209 | conflict on any particular lock. | |
2210 | ||
2211 | ||
2e4f5382 PZ |
2212 | ACQUIRES VS MEMORY ACCESSES |
2213 | --------------------------- | |
108b42b4 | 2214 | |
79afecfa | 2215 | Consider the following: the system has a pair of spinlocks (M) and (Q), and |
108b42b4 DH |
2216 | three CPUs; then should the following sequence of events occur: |
2217 | ||
2218 | CPU 1 CPU 2 | |
2219 | =============================== =============================== | |
9af194ce | 2220 | WRITE_ONCE(*A, a); WRITE_ONCE(*E, e); |
2e4f5382 | 2221 | ACQUIRE M ACQUIRE Q |
9af194ce PM |
2222 | WRITE_ONCE(*B, b); WRITE_ONCE(*F, f); |
2223 | WRITE_ONCE(*C, c); WRITE_ONCE(*G, g); | |
2e4f5382 | 2224 | RELEASE M RELEASE Q |
9af194ce | 2225 | WRITE_ONCE(*D, d); WRITE_ONCE(*H, h); |
108b42b4 | 2226 | |
81fc6323 | 2227 | Then there is no guarantee as to what order CPU 3 will see the accesses to *A |
108b42b4 | 2228 | through *H occur in, other than the constraints imposed by the separate locks |
0b6fa347 | 2229 | on the separate CPUs. It might, for example, see: |
108b42b4 | 2230 | |
2e4f5382 | 2231 | *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M |
108b42b4 DH |
2232 | |
2233 | But it won't see any of: | |
2234 | ||
2e4f5382 PZ |
2235 | *B, *C or *D preceding ACQUIRE M |
2236 | *A, *B or *C following RELEASE M | |
2237 | *F, *G or *H preceding ACQUIRE Q | |
2238 | *E, *F or *G following RELEASE Q | |
108b42b4 DH |
2239 | |
2240 | ||
108b42b4 | 2241 | |
2e4f5382 PZ |
2242 | ACQUIRES VS I/O ACCESSES |
2243 | ------------------------ | |
108b42b4 DH |
2244 | |
2245 | Under certain circumstances (especially involving NUMA), I/O accesses within | |
2246 | two spinlocked sections on two different CPUs may be seen as interleaved by the | |
2247 | PCI bridge, because the PCI bridge does not necessarily participate in the | |
2248 | cache-coherence protocol, and is therefore incapable of issuing the required | |
2249 | read memory barriers. | |
2250 | ||
2251 | For example: | |
2252 | ||
2253 | CPU 1 CPU 2 | |
2254 | =============================== =============================== | |
2255 | spin_lock(Q) | |
2256 | writel(0, ADDR) | |
2257 | writel(1, DATA); | |
2258 | spin_unlock(Q); | |
2259 | spin_lock(Q); | |
2260 | writel(4, ADDR); | |
2261 | writel(5, DATA); | |
2262 | spin_unlock(Q); | |
2263 | ||
2264 | may be seen by the PCI bridge as follows: | |
2265 | ||
2266 | STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5 | |
2267 | ||
2268 | which would probably cause the hardware to malfunction. | |
2269 | ||
2270 | ||
2271 | What is necessary here is to intervene with an mmiowb() before dropping the | |
2272 | spinlock, for example: | |
2273 | ||
2274 | CPU 1 CPU 2 | |
2275 | =============================== =============================== | |
2276 | spin_lock(Q) | |
2277 | writel(0, ADDR) | |
2278 | writel(1, DATA); | |
2279 | mmiowb(); | |
2280 | spin_unlock(Q); | |
2281 | spin_lock(Q); | |
2282 | writel(4, ADDR); | |
2283 | writel(5, DATA); | |
2284 | mmiowb(); | |
2285 | spin_unlock(Q); | |
2286 | ||
81fc6323 JP |
2287 | this will ensure that the two stores issued on CPU 1 appear at the PCI bridge |
2288 | before either of the stores issued on CPU 2. | |
108b42b4 DH |
2289 | |
2290 | ||
81fc6323 JP |
2291 | Furthermore, following a store by a load from the same device obviates the need |
2292 | for the mmiowb(), because the load forces the store to complete before the load | |
108b42b4 DH |
2293 | is performed: |
2294 | ||
2295 | CPU 1 CPU 2 | |
2296 | =============================== =============================== | |
2297 | spin_lock(Q) | |
2298 | writel(0, ADDR) | |
2299 | a = readl(DATA); | |
2300 | spin_unlock(Q); | |
2301 | spin_lock(Q); | |
2302 | writel(4, ADDR); | |
2303 | b = readl(DATA); | |
2304 | spin_unlock(Q); | |
2305 | ||
2306 | ||
2307 | See Documentation/DocBook/deviceiobook.tmpl for more information. | |
2308 | ||
2309 | ||
2310 | ================================= | |
2311 | WHERE ARE MEMORY BARRIERS NEEDED? | |
2312 | ================================= | |
2313 | ||
2314 | Under normal operation, memory operation reordering is generally not going to | |
2315 | be a problem as a single-threaded linear piece of code will still appear to | |
50fa610a | 2316 | work correctly, even if it's in an SMP kernel. There are, however, four |
108b42b4 DH |
2317 | circumstances in which reordering definitely _could_ be a problem: |
2318 | ||
2319 | (*) Interprocessor interaction. | |
2320 | ||
2321 | (*) Atomic operations. | |
2322 | ||
81fc6323 | 2323 | (*) Accessing devices. |
108b42b4 DH |
2324 | |
2325 | (*) Interrupts. | |
2326 | ||
2327 | ||
2328 | INTERPROCESSOR INTERACTION | |
2329 | -------------------------- | |
2330 | ||
2331 | When there's a system with more than one processor, more than one CPU in the | |
2332 | system may be working on the same data set at the same time. This can cause | |
2333 | synchronisation problems, and the usual way of dealing with them is to use | |
2334 | locks. Locks, however, are quite expensive, and so it may be preferable to | |
2335 | operate without the use of a lock if at all possible. In such a case | |
2336 | operations that affect both CPUs may have to be carefully ordered to prevent | |
2337 | a malfunction. | |
2338 | ||
2339 | Consider, for example, the R/W semaphore slow path. Here a waiting process is | |
2340 | queued on the semaphore, by virtue of it having a piece of its stack linked to | |
2341 | the semaphore's list of waiting processes: | |
2342 | ||
2343 | struct rw_semaphore { | |
2344 | ... | |
2345 | spinlock_t lock; | |
2346 | struct list_head waiters; | |
2347 | }; | |
2348 | ||
2349 | struct rwsem_waiter { | |
2350 | struct list_head list; | |
2351 | struct task_struct *task; | |
2352 | }; | |
2353 | ||
2354 | To wake up a particular waiter, the up_read() or up_write() functions have to: | |
2355 | ||
2356 | (1) read the next pointer from this waiter's record to know as to where the | |
2357 | next waiter record is; | |
2358 | ||
81fc6323 | 2359 | (2) read the pointer to the waiter's task structure; |
108b42b4 DH |
2360 | |
2361 | (3) clear the task pointer to tell the waiter it has been given the semaphore; | |
2362 | ||
2363 | (4) call wake_up_process() on the task; and | |
2364 | ||
2365 | (5) release the reference held on the waiter's task struct. | |
2366 | ||
81fc6323 | 2367 | In other words, it has to perform this sequence of events: |
108b42b4 DH |
2368 | |
2369 | LOAD waiter->list.next; | |
2370 | LOAD waiter->task; | |
2371 | STORE waiter->task; | |
2372 | CALL wakeup | |
2373 | RELEASE task | |
2374 | ||
2375 | and if any of these steps occur out of order, then the whole thing may | |
2376 | malfunction. | |
2377 | ||
2378 | Once it has queued itself and dropped the semaphore lock, the waiter does not | |
2379 | get the lock again; it instead just waits for its task pointer to be cleared | |
2380 | before proceeding. Since the record is on the waiter's stack, this means that | |
2381 | if the task pointer is cleared _before_ the next pointer in the list is read, | |
2382 | another CPU might start processing the waiter and might clobber the waiter's | |
2383 | stack before the up*() function has a chance to read the next pointer. | |
2384 | ||
2385 | Consider then what might happen to the above sequence of events: | |
2386 | ||
2387 | CPU 1 CPU 2 | |
2388 | =============================== =============================== | |
2389 | down_xxx() | |
2390 | Queue waiter | |
2391 | Sleep | |
2392 | up_yyy() | |
2393 | LOAD waiter->task; | |
2394 | STORE waiter->task; | |
2395 | Woken up by other event | |
2396 | <preempt> | |
2397 | Resume processing | |
2398 | down_xxx() returns | |
2399 | call foo() | |
2400 | foo() clobbers *waiter | |
2401 | </preempt> | |
2402 | LOAD waiter->list.next; | |
2403 | --- OOPS --- | |
2404 | ||
2405 | This could be dealt with using the semaphore lock, but then the down_xxx() | |
2406 | function has to needlessly get the spinlock again after being woken up. | |
2407 | ||
2408 | The way to deal with this is to insert a general SMP memory barrier: | |
2409 | ||
2410 | LOAD waiter->list.next; | |
2411 | LOAD waiter->task; | |
2412 | smp_mb(); | |
2413 | STORE waiter->task; | |
2414 | CALL wakeup | |
2415 | RELEASE task | |
2416 | ||
2417 | In this case, the barrier makes a guarantee that all memory accesses before the | |
2418 | barrier will appear to happen before all the memory accesses after the barrier | |
2419 | with respect to the other CPUs on the system. It does _not_ guarantee that all | |
2420 | the memory accesses before the barrier will be complete by the time the barrier | |
2421 | instruction itself is complete. | |
2422 | ||
2423 | On a UP system - where this wouldn't be a problem - the smp_mb() is just a | |
2424 | compiler barrier, thus making sure the compiler emits the instructions in the | |
6bc39274 DH |
2425 | right order without actually intervening in the CPU. Since there's only one |
2426 | CPU, that CPU's dependency ordering logic will take care of everything else. | |
108b42b4 DH |
2427 | |
2428 | ||
2429 | ATOMIC OPERATIONS | |
2430 | ----------------- | |
2431 | ||
dbc8700e DH |
2432 | Whilst they are technically interprocessor interaction considerations, atomic |
2433 | operations are noted specially as some of them imply full memory barriers and | |
2434 | some don't, but they're very heavily relied on as a group throughout the | |
2435 | kernel. | |
2436 | ||
2437 | Any atomic operation that modifies some state in memory and returns information | |
2438 | about the state (old or new) implies an SMP-conditional general memory barrier | |
26333576 NP |
2439 | (smp_mb()) on each side of the actual operation (with the exception of |
2440 | explicit lock operations, described later). These include: | |
108b42b4 DH |
2441 | |
2442 | xchg(); | |
fb2b5819 | 2443 | atomic_xchg(); atomic_long_xchg(); |
fb2b5819 PM |
2444 | atomic_inc_return(); atomic_long_inc_return(); |
2445 | atomic_dec_return(); atomic_long_dec_return(); | |
2446 | atomic_add_return(); atomic_long_add_return(); | |
2447 | atomic_sub_return(); atomic_long_sub_return(); | |
2448 | atomic_inc_and_test(); atomic_long_inc_and_test(); | |
2449 | atomic_dec_and_test(); atomic_long_dec_and_test(); | |
2450 | atomic_sub_and_test(); atomic_long_sub_and_test(); | |
2451 | atomic_add_negative(); atomic_long_add_negative(); | |
dbc8700e DH |
2452 | test_and_set_bit(); |
2453 | test_and_clear_bit(); | |
2454 | test_and_change_bit(); | |
2455 | ||
ed2de9f7 WD |
2456 | /* when succeeds */ |
2457 | cmpxchg(); | |
2458 | atomic_cmpxchg(); atomic_long_cmpxchg(); | |
fb2b5819 PM |
2459 | atomic_add_unless(); atomic_long_add_unless(); |
2460 | ||
2e4f5382 | 2461 | These are used for such things as implementing ACQUIRE-class and RELEASE-class |
dbc8700e DH |
2462 | operations and adjusting reference counters towards object destruction, and as |
2463 | such the implicit memory barrier effects are necessary. | |
108b42b4 | 2464 | |
108b42b4 | 2465 | |
81fc6323 | 2466 | The following operations are potential problems as they do _not_ imply memory |
2e4f5382 | 2467 | barriers, but might be used for implementing such things as RELEASE-class |
dbc8700e | 2468 | operations: |
108b42b4 | 2469 | |
dbc8700e | 2470 | atomic_set(); |
108b42b4 DH |
2471 | set_bit(); |
2472 | clear_bit(); | |
2473 | change_bit(); | |
dbc8700e DH |
2474 | |
2475 | With these the appropriate explicit memory barrier should be used if necessary | |
1b15611e | 2476 | (smp_mb__before_atomic() for instance). |
108b42b4 DH |
2477 | |
2478 | ||
dbc8700e | 2479 | The following also do _not_ imply memory barriers, and so may require explicit |
1b15611e | 2480 | memory barriers under some circumstances (smp_mb__before_atomic() for |
81fc6323 | 2481 | instance): |
108b42b4 DH |
2482 | |
2483 | atomic_add(); | |
2484 | atomic_sub(); | |
2485 | atomic_inc(); | |
2486 | atomic_dec(); | |
2487 | ||
2488 | If they're used for statistics generation, then they probably don't need memory | |
2489 | barriers, unless there's a coupling between statistical data. | |
2490 | ||
2491 | If they're used for reference counting on an object to control its lifetime, | |
2492 | they probably don't need memory barriers because either the reference count | |
2493 | will be adjusted inside a locked section, or the caller will already hold | |
2494 | sufficient references to make the lock, and thus a memory barrier unnecessary. | |
2495 | ||
2496 | If they're used for constructing a lock of some description, then they probably | |
2497 | do need memory barriers as a lock primitive generally has to do things in a | |
2498 | specific order. | |
2499 | ||
108b42b4 | 2500 | Basically, each usage case has to be carefully considered as to whether memory |
dbc8700e DH |
2501 | barriers are needed or not. |
2502 | ||
26333576 NP |
2503 | The following operations are special locking primitives: |
2504 | ||
2505 | test_and_set_bit_lock(); | |
2506 | clear_bit_unlock(); | |
2507 | __clear_bit_unlock(); | |
2508 | ||
0b6fa347 SP |
2509 | These implement ACQUIRE-class and RELEASE-class operations. These should be |
2510 | used in preference to other operations when implementing locking primitives, | |
2511 | because their implementations can be optimised on many architectures. | |
26333576 | 2512 | |
dbc8700e DH |
2513 | [!] Note that special memory barrier primitives are available for these |
2514 | situations because on some CPUs the atomic instructions used imply full memory | |
2515 | barriers, and so barrier instructions are superfluous in conjunction with them, | |
2516 | and in such cases the special barrier primitives will be no-ops. | |
108b42b4 DH |
2517 | |
2518 | See Documentation/atomic_ops.txt for more information. | |
2519 | ||
2520 | ||
2521 | ACCESSING DEVICES | |
2522 | ----------------- | |
2523 | ||
2524 | Many devices can be memory mapped, and so appear to the CPU as if they're just | |
2525 | a set of memory locations. To control such a device, the driver usually has to | |
2526 | make the right memory accesses in exactly the right order. | |
2527 | ||
2528 | However, having a clever CPU or a clever compiler creates a potential problem | |
2529 | in that the carefully sequenced accesses in the driver code won't reach the | |
2530 | device in the requisite order if the CPU or the compiler thinks it is more | |
2531 | efficient to reorder, combine or merge accesses - something that would cause | |
2532 | the device to malfunction. | |
2533 | ||
2534 | Inside of the Linux kernel, I/O should be done through the appropriate accessor | |
2535 | routines - such as inb() or writel() - which know how to make such accesses | |
2536 | appropriately sequential. Whilst this, for the most part, renders the explicit | |
2537 | use of memory barriers unnecessary, there are a couple of situations where they | |
2538 | might be needed: | |
2539 | ||
2540 | (1) On some systems, I/O stores are not strongly ordered across all CPUs, and | |
2541 | so for _all_ general drivers locks should be used and mmiowb() must be | |
2542 | issued prior to unlocking the critical section. | |
2543 | ||
2544 | (2) If the accessor functions are used to refer to an I/O memory window with | |
2545 | relaxed memory access properties, then _mandatory_ memory barriers are | |
2546 | required to enforce ordering. | |
2547 | ||
2548 | See Documentation/DocBook/deviceiobook.tmpl for more information. | |
2549 | ||
2550 | ||
2551 | INTERRUPTS | |
2552 | ---------- | |
2553 | ||
2554 | A driver may be interrupted by its own interrupt service routine, and thus the | |
2555 | two parts of the driver may interfere with each other's attempts to control or | |
2556 | access the device. | |
2557 | ||
2558 | This may be alleviated - at least in part - by disabling local interrupts (a | |
2559 | form of locking), such that the critical operations are all contained within | |
2560 | the interrupt-disabled section in the driver. Whilst the driver's interrupt | |
2561 | routine is executing, the driver's core may not run on the same CPU, and its | |
2562 | interrupt is not permitted to happen again until the current interrupt has been | |
2563 | handled, thus the interrupt handler does not need to lock against that. | |
2564 | ||
2565 | However, consider a driver that was talking to an ethernet card that sports an | |
2566 | address register and a data register. If that driver's core talks to the card | |
2567 | under interrupt-disablement and then the driver's interrupt handler is invoked: | |
2568 | ||
2569 | LOCAL IRQ DISABLE | |
2570 | writew(ADDR, 3); | |
2571 | writew(DATA, y); | |
2572 | LOCAL IRQ ENABLE | |
2573 | <interrupt> | |
2574 | writew(ADDR, 4); | |
2575 | q = readw(DATA); | |
2576 | </interrupt> | |
2577 | ||
2578 | The store to the data register might happen after the second store to the | |
2579 | address register if ordering rules are sufficiently relaxed: | |
2580 | ||
2581 | STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA | |
2582 | ||
2583 | ||
2584 | If ordering rules are relaxed, it must be assumed that accesses done inside an | |
2585 | interrupt disabled section may leak outside of it and may interleave with | |
2586 | accesses performed in an interrupt - and vice versa - unless implicit or | |
2587 | explicit barriers are used. | |
2588 | ||
2589 | Normally this won't be a problem because the I/O accesses done inside such | |
2590 | sections will include synchronous load operations on strictly ordered I/O | |
0b6fa347 | 2591 | registers that form implicit I/O barriers. If this isn't sufficient then an |
108b42b4 DH |
2592 | mmiowb() may need to be used explicitly. |
2593 | ||
2594 | ||
2595 | A similar situation may occur between an interrupt routine and two routines | |
0b6fa347 | 2596 | running on separate CPUs that communicate with each other. If such a case is |
108b42b4 DH |
2597 | likely, then interrupt-disabling locks should be used to guarantee ordering. |
2598 | ||
2599 | ||
2600 | ========================== | |
2601 | KERNEL I/O BARRIER EFFECTS | |
2602 | ========================== | |
2603 | ||
2604 | When accessing I/O memory, drivers should use the appropriate accessor | |
2605 | functions: | |
2606 | ||
2607 | (*) inX(), outX(): | |
2608 | ||
2609 | These are intended to talk to I/O space rather than memory space, but | |
0b6fa347 SP |
2610 | that's primarily a CPU-specific concept. The i386 and x86_64 processors |
2611 | do indeed have special I/O space access cycles and instructions, but many | |
108b42b4 DH |
2612 | CPUs don't have such a concept. |
2613 | ||
81fc6323 JP |
2614 | The PCI bus, amongst others, defines an I/O space concept which - on such |
2615 | CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O | |
6bc39274 DH |
2616 | space. However, it may also be mapped as a virtual I/O space in the CPU's |
2617 | memory map, particularly on those CPUs that don't support alternate I/O | |
2618 | spaces. | |
108b42b4 DH |
2619 | |
2620 | Accesses to this space may be fully synchronous (as on i386), but | |
2621 | intermediary bridges (such as the PCI host bridge) may not fully honour | |
2622 | that. | |
2623 | ||
2624 | They are guaranteed to be fully ordered with respect to each other. | |
2625 | ||
2626 | They are not guaranteed to be fully ordered with respect to other types of | |
2627 | memory and I/O operation. | |
2628 | ||
2629 | (*) readX(), writeX(): | |
2630 | ||
2631 | Whether these are guaranteed to be fully ordered and uncombined with | |
2632 | respect to each other on the issuing CPU depends on the characteristics | |
0b6fa347 | 2633 | defined for the memory window through which they're accessing. On later |
108b42b4 DH |
2634 | i386 architecture machines, for example, this is controlled by way of the |
2635 | MTRR registers. | |
2636 | ||
81fc6323 | 2637 | Ordinarily, these will be guaranteed to be fully ordered and uncombined, |
108b42b4 DH |
2638 | provided they're not accessing a prefetchable device. |
2639 | ||
2640 | However, intermediary hardware (such as a PCI bridge) may indulge in | |
2641 | deferral if it so wishes; to flush a store, a load from the same location | |
2642 | is preferred[*], but a load from the same device or from configuration | |
2643 | space should suffice for PCI. | |
2644 | ||
2645 | [*] NOTE! attempting to load from the same location as was written to may | |
e0edc78f IM |
2646 | cause a malfunction - consider the 16550 Rx/Tx serial registers for |
2647 | example. | |
108b42b4 DH |
2648 | |
2649 | Used with prefetchable I/O memory, an mmiowb() barrier may be required to | |
2650 | force stores to be ordered. | |
2651 | ||
2652 | Please refer to the PCI specification for more information on interactions | |
2653 | between PCI transactions. | |
2654 | ||
a8e0aead WD |
2655 | (*) readX_relaxed(), writeX_relaxed() |
2656 | ||
2657 | These are similar to readX() and writeX(), but provide weaker memory | |
0b6fa347 | 2658 | ordering guarantees. Specifically, they do not guarantee ordering with |
a8e0aead | 2659 | respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee |
0b6fa347 SP |
2660 | ordering with respect to LOCK or UNLOCK operations. If the latter is |
2661 | required, an mmiowb() barrier can be used. Note that relaxed accesses to | |
a8e0aead WD |
2662 | the same peripheral are guaranteed to be ordered with respect to each |
2663 | other. | |
108b42b4 DH |
2664 | |
2665 | (*) ioreadX(), iowriteX() | |
2666 | ||
81fc6323 | 2667 | These will perform appropriately for the type of access they're actually |
108b42b4 DH |
2668 | doing, be it inX()/outX() or readX()/writeX(). |
2669 | ||
2670 | ||
2671 | ======================================== | |
2672 | ASSUMED MINIMUM EXECUTION ORDERING MODEL | |
2673 | ======================================== | |
2674 | ||
2675 | It has to be assumed that the conceptual CPU is weakly-ordered but that it will | |
2676 | maintain the appearance of program causality with respect to itself. Some CPUs | |
2677 | (such as i386 or x86_64) are more constrained than others (such as powerpc or | |
2678 | frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside | |
2679 | of arch-specific code. | |
2680 | ||
2681 | This means that it must be considered that the CPU will execute its instruction | |
2682 | stream in any order it feels like - or even in parallel - provided that if an | |
81fc6323 | 2683 | instruction in the stream depends on an earlier instruction, then that |
108b42b4 DH |
2684 | earlier instruction must be sufficiently complete[*] before the later |
2685 | instruction may proceed; in other words: provided that the appearance of | |
2686 | causality is maintained. | |
2687 | ||
2688 | [*] Some instructions have more than one effect - such as changing the | |
2689 | condition codes, changing registers or changing memory - and different | |
2690 | instructions may depend on different effects. | |
2691 | ||
2692 | A CPU may also discard any instruction sequence that winds up having no | |
2693 | ultimate effect. For example, if two adjacent instructions both load an | |
2694 | immediate value into the same register, the first may be discarded. | |
2695 | ||
2696 | ||
2697 | Similarly, it has to be assumed that compiler might reorder the instruction | |
2698 | stream in any way it sees fit, again provided the appearance of causality is | |
2699 | maintained. | |
2700 | ||
2701 | ||
2702 | ============================ | |
2703 | THE EFFECTS OF THE CPU CACHE | |
2704 | ============================ | |
2705 | ||
2706 | The way cached memory operations are perceived across the system is affected to | |
2707 | a certain extent by the caches that lie between CPUs and memory, and by the | |
2708 | memory coherence system that maintains the consistency of state in the system. | |
2709 | ||
2710 | As far as the way a CPU interacts with another part of the system through the | |
2711 | caches goes, the memory system has to include the CPU's caches, and memory | |
2712 | barriers for the most part act at the interface between the CPU and its cache | |
2713 | (memory barriers logically act on the dotted line in the following diagram): | |
2714 | ||
2715 | <--- CPU ---> : <----------- Memory -----------> | |
2716 | : | |
2717 | +--------+ +--------+ : +--------+ +-----------+ | |
2718 | | | | | : | | | | +--------+ | |
e0edc78f IM |
2719 | | CPU | | Memory | : | CPU | | | | | |
2720 | | Core |--->| Access |----->| Cache |<-->| | | | | |
108b42b4 | 2721 | | | | Queue | : | | | |--->| Memory | |
e0edc78f IM |
2722 | | | | | : | | | | | | |
2723 | +--------+ +--------+ : +--------+ | | | | | |
108b42b4 DH |
2724 | : | Cache | +--------+ |
2725 | : | Coherency | | |
2726 | : | Mechanism | +--------+ | |
2727 | +--------+ +--------+ : +--------+ | | | | | |
2728 | | | | | : | | | | | | | |
2729 | | CPU | | Memory | : | CPU | | |--->| Device | | |
e0edc78f IM |
2730 | | Core |--->| Access |----->| Cache |<-->| | | | |
2731 | | | | Queue | : | | | | | | | |
108b42b4 DH |
2732 | | | | | : | | | | +--------+ |
2733 | +--------+ +--------+ : +--------+ +-----------+ | |
2734 | : | |
2735 | : | |
2736 | ||
2737 | Although any particular load or store may not actually appear outside of the | |
2738 | CPU that issued it since it may have been satisfied within the CPU's own cache, | |
2739 | it will still appear as if the full memory access had taken place as far as the | |
2740 | other CPUs are concerned since the cache coherency mechanisms will migrate the | |
2741 | cacheline over to the accessing CPU and propagate the effects upon conflict. | |
2742 | ||
2743 | The CPU core may execute instructions in any order it deems fit, provided the | |
2744 | expected program causality appears to be maintained. Some of the instructions | |
2745 | generate load and store operations which then go into the queue of memory | |
2746 | accesses to be performed. The core may place these in the queue in any order | |
2747 | it wishes, and continue execution until it is forced to wait for an instruction | |
2748 | to complete. | |
2749 | ||
2750 | What memory barriers are concerned with is controlling the order in which | |
2751 | accesses cross from the CPU side of things to the memory side of things, and | |
2752 | the order in which the effects are perceived to happen by the other observers | |
2753 | in the system. | |
2754 | ||
2755 | [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see | |
2756 | their own loads and stores as if they had happened in program order. | |
2757 | ||
2758 | [!] MMIO or other device accesses may bypass the cache system. This depends on | |
2759 | the properties of the memory window through which devices are accessed and/or | |
2760 | the use of any special device communication instructions the CPU may have. | |
2761 | ||
2762 | ||
2763 | CACHE COHERENCY | |
2764 | --------------- | |
2765 | ||
2766 | Life isn't quite as simple as it may appear above, however: for while the | |
2767 | caches are expected to be coherent, there's no guarantee that that coherency | |
2768 | will be ordered. This means that whilst changes made on one CPU will | |
2769 | eventually become visible on all CPUs, there's no guarantee that they will | |
2770 | become apparent in the same order on those other CPUs. | |
2771 | ||
2772 | ||
81fc6323 JP |
2773 | Consider dealing with a system that has a pair of CPUs (1 & 2), each of which |
2774 | has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D): | |
108b42b4 DH |
2775 | |
2776 | : | |
2777 | : +--------+ | |
2778 | : +---------+ | | | |
2779 | +--------+ : +--->| Cache A |<------->| | | |
2780 | | | : | +---------+ | | | |
2781 | | CPU 1 |<---+ | | | |
2782 | | | : | +---------+ | | | |
2783 | +--------+ : +--->| Cache B |<------->| | | |
2784 | : +---------+ | | | |
2785 | : | Memory | | |
2786 | : +---------+ | System | | |
2787 | +--------+ : +--->| Cache C |<------->| | | |
2788 | | | : | +---------+ | | | |
2789 | | CPU 2 |<---+ | | | |
2790 | | | : | +---------+ | | | |
2791 | +--------+ : +--->| Cache D |<------->| | | |
2792 | : +---------+ | | | |
2793 | : +--------+ | |
2794 | : | |
2795 | ||
2796 | Imagine the system has the following properties: | |
2797 | ||
2798 | (*) an odd-numbered cache line may be in cache A, cache C or it may still be | |
2799 | resident in memory; | |
2800 | ||
2801 | (*) an even-numbered cache line may be in cache B, cache D or it may still be | |
2802 | resident in memory; | |
2803 | ||
2804 | (*) whilst the CPU core is interrogating one cache, the other cache may be | |
2805 | making use of the bus to access the rest of the system - perhaps to | |
2806 | displace a dirty cacheline or to do a speculative load; | |
2807 | ||
2808 | (*) each cache has a queue of operations that need to be applied to that cache | |
2809 | to maintain coherency with the rest of the system; | |
2810 | ||
2811 | (*) the coherency queue is not flushed by normal loads to lines already | |
2812 | present in the cache, even though the contents of the queue may | |
81fc6323 | 2813 | potentially affect those loads. |
108b42b4 DH |
2814 | |
2815 | Imagine, then, that two writes are made on the first CPU, with a write barrier | |
2816 | between them to guarantee that they will appear to reach that CPU's caches in | |
2817 | the requisite order: | |
2818 | ||
2819 | CPU 1 CPU 2 COMMENT | |
2820 | =============== =============== ======================================= | |
2821 | u == 0, v == 1 and p == &u, q == &u | |
2822 | v = 2; | |
81fc6323 | 2823 | smp_wmb(); Make sure change to v is visible before |
108b42b4 DH |
2824 | change to p |
2825 | <A:modify v=2> v is now in cache A exclusively | |
2826 | p = &v; | |
2827 | <B:modify p=&v> p is now in cache B exclusively | |
2828 | ||
2829 | The write memory barrier forces the other CPUs in the system to perceive that | |
2830 | the local CPU's caches have apparently been updated in the correct order. But | |
81fc6323 | 2831 | now imagine that the second CPU wants to read those values: |
108b42b4 DH |
2832 | |
2833 | CPU 1 CPU 2 COMMENT | |
2834 | =============== =============== ======================================= | |
2835 | ... | |
2836 | q = p; | |
2837 | x = *q; | |
2838 | ||
81fc6323 | 2839 | The above pair of reads may then fail to happen in the expected order, as the |
108b42b4 DH |
2840 | cacheline holding p may get updated in one of the second CPU's caches whilst |
2841 | the update to the cacheline holding v is delayed in the other of the second | |
2842 | CPU's caches by some other cache event: | |
2843 | ||
2844 | CPU 1 CPU 2 COMMENT | |
2845 | =============== =============== ======================================= | |
2846 | u == 0, v == 1 and p == &u, q == &u | |
2847 | v = 2; | |
2848 | smp_wmb(); | |
2849 | <A:modify v=2> <C:busy> | |
2850 | <C:queue v=2> | |
79afecfa | 2851 | p = &v; q = p; |
108b42b4 DH |
2852 | <D:request p> |
2853 | <B:modify p=&v> <D:commit p=&v> | |
e0edc78f | 2854 | <D:read p> |
108b42b4 DH |
2855 | x = *q; |
2856 | <C:read *q> Reads from v before v updated in cache | |
2857 | <C:unbusy> | |
2858 | <C:commit v=2> | |
2859 | ||
2860 | Basically, whilst both cachelines will be updated on CPU 2 eventually, there's | |
2861 | no guarantee that, without intervention, the order of update will be the same | |
2862 | as that committed on CPU 1. | |
2863 | ||
2864 | ||
2865 | To intervene, we need to interpolate a data dependency barrier or a read | |
2866 | barrier between the loads. This will force the cache to commit its coherency | |
2867 | queue before processing any further requests: | |
2868 | ||
2869 | CPU 1 CPU 2 COMMENT | |
2870 | =============== =============== ======================================= | |
2871 | u == 0, v == 1 and p == &u, q == &u | |
2872 | v = 2; | |
2873 | smp_wmb(); | |
2874 | <A:modify v=2> <C:busy> | |
2875 | <C:queue v=2> | |
3fda982c | 2876 | p = &v; q = p; |
108b42b4 DH |
2877 | <D:request p> |
2878 | <B:modify p=&v> <D:commit p=&v> | |
e0edc78f | 2879 | <D:read p> |
108b42b4 DH |
2880 | smp_read_barrier_depends() |
2881 | <C:unbusy> | |
2882 | <C:commit v=2> | |
2883 | x = *q; | |
2884 | <C:read *q> Reads from v after v updated in cache | |
2885 | ||
2886 | ||
2887 | This sort of problem can be encountered on DEC Alpha processors as they have a | |
2888 | split cache that improves performance by making better use of the data bus. | |
2889 | Whilst most CPUs do imply a data dependency barrier on the read when a memory | |
2890 | access depends on a read, not all do, so it may not be relied on. | |
2891 | ||
2892 | Other CPUs may also have split caches, but must coordinate between the various | |
3f6dee9b | 2893 | cachelets for normal memory accesses. The semantics of the Alpha removes the |
81fc6323 | 2894 | need for coordination in the absence of memory barriers. |
108b42b4 DH |
2895 | |
2896 | ||
2897 | CACHE COHERENCY VS DMA | |
2898 | ---------------------- | |
2899 | ||
2900 | Not all systems maintain cache coherency with respect to devices doing DMA. In | |
2901 | such cases, a device attempting DMA may obtain stale data from RAM because | |
2902 | dirty cache lines may be resident in the caches of various CPUs, and may not | |
2903 | have been written back to RAM yet. To deal with this, the appropriate part of | |
2904 | the kernel must flush the overlapping bits of cache on each CPU (and maybe | |
2905 | invalidate them as well). | |
2906 | ||
2907 | In addition, the data DMA'd to RAM by a device may be overwritten by dirty | |
2908 | cache lines being written back to RAM from a CPU's cache after the device has | |
81fc6323 JP |
2909 | installed its own data, or cache lines present in the CPU's cache may simply |
2910 | obscure the fact that RAM has been updated, until at such time as the cacheline | |
2911 | is discarded from the CPU's cache and reloaded. To deal with this, the | |
2912 | appropriate part of the kernel must invalidate the overlapping bits of the | |
108b42b4 DH |
2913 | cache on each CPU. |
2914 | ||
2915 | See Documentation/cachetlb.txt for more information on cache management. | |
2916 | ||
2917 | ||
2918 | CACHE COHERENCY VS MMIO | |
2919 | ----------------------- | |
2920 | ||
2921 | Memory mapped I/O usually takes place through memory locations that are part of | |
81fc6323 | 2922 | a window in the CPU's memory space that has different properties assigned than |
108b42b4 DH |
2923 | the usual RAM directed window. |
2924 | ||
2925 | Amongst these properties is usually the fact that such accesses bypass the | |
2926 | caching entirely and go directly to the device buses. This means MMIO accesses | |
2927 | may, in effect, overtake accesses to cached memory that were emitted earlier. | |
2928 | A memory barrier isn't sufficient in such a case, but rather the cache must be | |
2929 | flushed between the cached memory write and the MMIO access if the two are in | |
2930 | any way dependent. | |
2931 | ||
2932 | ||
2933 | ========================= | |
2934 | THE THINGS CPUS GET UP TO | |
2935 | ========================= | |
2936 | ||
2937 | A programmer might take it for granted that the CPU will perform memory | |
81fc6323 | 2938 | operations in exactly the order specified, so that if the CPU is, for example, |
108b42b4 DH |
2939 | given the following piece of code to execute: |
2940 | ||
9af194ce PM |
2941 | a = READ_ONCE(*A); |
2942 | WRITE_ONCE(*B, b); | |
2943 | c = READ_ONCE(*C); | |
2944 | d = READ_ONCE(*D); | |
2945 | WRITE_ONCE(*E, e); | |
108b42b4 | 2946 | |
81fc6323 | 2947 | they would then expect that the CPU will complete the memory operation for each |
108b42b4 DH |
2948 | instruction before moving on to the next one, leading to a definite sequence of |
2949 | operations as seen by external observers in the system: | |
2950 | ||
2951 | LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E. | |
2952 | ||
2953 | ||
2954 | Reality is, of course, much messier. With many CPUs and compilers, the above | |
2955 | assumption doesn't hold because: | |
2956 | ||
2957 | (*) loads are more likely to need to be completed immediately to permit | |
2958 | execution progress, whereas stores can often be deferred without a | |
2959 | problem; | |
2960 | ||
2961 | (*) loads may be done speculatively, and the result discarded should it prove | |
2962 | to have been unnecessary; | |
2963 | ||
81fc6323 JP |
2964 | (*) loads may be done speculatively, leading to the result having been fetched |
2965 | at the wrong time in the expected sequence of events; | |
108b42b4 DH |
2966 | |
2967 | (*) the order of the memory accesses may be rearranged to promote better use | |
2968 | of the CPU buses and caches; | |
2969 | ||
2970 | (*) loads and stores may be combined to improve performance when talking to | |
2971 | memory or I/O hardware that can do batched accesses of adjacent locations, | |
2972 | thus cutting down on transaction setup costs (memory and PCI devices may | |
2973 | both be able to do this); and | |
2974 | ||
2975 | (*) the CPU's data cache may affect the ordering, and whilst cache-coherency | |
2976 | mechanisms may alleviate this - once the store has actually hit the cache | |
2977 | - there's no guarantee that the coherency management will be propagated in | |
2978 | order to other CPUs. | |
2979 | ||
2980 | So what another CPU, say, might actually observe from the above piece of code | |
2981 | is: | |
2982 | ||
2983 | LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B | |
2984 | ||
2985 | (Where "LOAD {*C,*D}" is a combined load) | |
2986 | ||
2987 | ||
2988 | However, it is guaranteed that a CPU will be self-consistent: it will see its | |
2989 | _own_ accesses appear to be correctly ordered, without the need for a memory | |
2990 | barrier. For instance with the following code: | |
2991 | ||
9af194ce PM |
2992 | U = READ_ONCE(*A); |
2993 | WRITE_ONCE(*A, V); | |
2994 | WRITE_ONCE(*A, W); | |
2995 | X = READ_ONCE(*A); | |
2996 | WRITE_ONCE(*A, Y); | |
2997 | Z = READ_ONCE(*A); | |
108b42b4 DH |
2998 | |
2999 | and assuming no intervention by an external influence, it can be assumed that | |
3000 | the final result will appear to be: | |
3001 | ||
3002 | U == the original value of *A | |
3003 | X == W | |
3004 | Z == Y | |
3005 | *A == Y | |
3006 | ||
3007 | The code above may cause the CPU to generate the full sequence of memory | |
3008 | accesses: | |
3009 | ||
3010 | U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A | |
3011 | ||
3012 | in that order, but, without intervention, the sequence may have almost any | |
9af194ce PM |
3013 | combination of elements combined or discarded, provided the program's view |
3014 | of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE() | |
3015 | are -not- optional in the above example, as there are architectures | |
3016 | where a given CPU might reorder successive loads to the same location. | |
3017 | On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is | |
3018 | necessary to prevent this, for example, on Itanium the volatile casts | |
3019 | used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq | |
3020 | and st.rel instructions (respectively) that prevent such reordering. | |
108b42b4 DH |
3021 | |
3022 | The compiler may also combine, discard or defer elements of the sequence before | |
3023 | the CPU even sees them. | |
3024 | ||
3025 | For instance: | |
3026 | ||
3027 | *A = V; | |
3028 | *A = W; | |
3029 | ||
3030 | may be reduced to: | |
3031 | ||
3032 | *A = W; | |
3033 | ||
9af194ce | 3034 | since, without either a write barrier or an WRITE_ONCE(), it can be |
2ecf8101 | 3035 | assumed that the effect of the storage of V to *A is lost. Similarly: |
108b42b4 DH |
3036 | |
3037 | *A = Y; | |
3038 | Z = *A; | |
3039 | ||
9af194ce PM |
3040 | may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be |
3041 | reduced to: | |
108b42b4 DH |
3042 | |
3043 | *A = Y; | |
3044 | Z = Y; | |
3045 | ||
3046 | and the LOAD operation never appear outside of the CPU. | |
3047 | ||
3048 | ||
3049 | AND THEN THERE'S THE ALPHA | |
3050 | -------------------------- | |
3051 | ||
3052 | The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that, | |
3053 | some versions of the Alpha CPU have a split data cache, permitting them to have | |
81fc6323 | 3054 | two semantically-related cache lines updated at separate times. This is where |
108b42b4 DH |
3055 | the data dependency barrier really becomes necessary as this synchronises both |
3056 | caches with the memory coherence system, thus making it seem like pointer | |
3057 | changes vs new data occur in the right order. | |
3058 | ||
81fc6323 | 3059 | The Alpha defines the Linux kernel's memory barrier model. |
108b42b4 DH |
3060 | |
3061 | See the subsection on "Cache Coherency" above. | |
3062 | ||
0b6fa347 | 3063 | |
6a65d263 | 3064 | VIRTUAL MACHINE GUESTS |
3dbf0913 | 3065 | ---------------------- |
6a65d263 MT |
3066 | |
3067 | Guests running within virtual machines might be affected by SMP effects even if | |
3068 | the guest itself is compiled without SMP support. This is an artifact of | |
3069 | interfacing with an SMP host while running an UP kernel. Using mandatory | |
3070 | barriers for this use-case would be possible but is often suboptimal. | |
3071 | ||
3072 | To handle this case optimally, low-level virt_mb() etc macros are available. | |
3073 | These have the same effect as smp_mb() etc when SMP is enabled, but generate | |
0b6fa347 | 3074 | identical code for SMP and non-SMP systems. For example, virtual machine guests |
6a65d263 MT |
3075 | should use virt_mb() rather than smp_mb() when synchronizing against a |
3076 | (possibly SMP) host. | |
3077 | ||
3078 | These are equivalent to smp_mb() etc counterparts in all other respects, | |
3079 | in particular, they do not control MMIO effects: to control | |
3080 | MMIO effects, use mandatory barriers. | |
108b42b4 | 3081 | |
0b6fa347 | 3082 | |
90fddabf DH |
3083 | ============ |
3084 | EXAMPLE USES | |
3085 | ============ | |
3086 | ||
3087 | CIRCULAR BUFFERS | |
3088 | ---------------- | |
3089 | ||
3090 | Memory barriers can be used to implement circular buffering without the need | |
3091 | of a lock to serialise the producer with the consumer. See: | |
3092 | ||
3093 | Documentation/circular-buffers.txt | |
3094 | ||
3095 | for details. | |
3096 | ||
3097 | ||
108b42b4 DH |
3098 | ========== |
3099 | REFERENCES | |
3100 | ========== | |
3101 | ||
3102 | Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek, | |
3103 | Digital Press) | |
3104 | Chapter 5.2: Physical Address Space Characteristics | |
3105 | Chapter 5.4: Caches and Write Buffers | |
3106 | Chapter 5.5: Data Sharing | |
3107 | Chapter 5.6: Read/Write Ordering | |
3108 | ||
3109 | AMD64 Architecture Programmer's Manual Volume 2: System Programming | |
3110 | Chapter 7.1: Memory-Access Ordering | |
3111 | Chapter 7.4: Buffering and Combining Memory Writes | |
3112 | ||
3113 | IA-32 Intel Architecture Software Developer's Manual, Volume 3: | |
3114 | System Programming Guide | |
3115 | Chapter 7.1: Locked Atomic Operations | |
3116 | Chapter 7.2: Memory Ordering | |
3117 | Chapter 7.4: Serializing Instructions | |
3118 | ||
3119 | The SPARC Architecture Manual, Version 9 | |
3120 | Chapter 8: Memory Models | |
3121 | Appendix D: Formal Specification of the Memory Models | |
3122 | Appendix J: Programming with the Memory Models | |
3123 | ||
3124 | UltraSPARC Programmer Reference Manual | |
3125 | Chapter 5: Memory Accesses and Cacheability | |
3126 | Chapter 15: Sparc-V9 Memory Models | |
3127 | ||
3128 | UltraSPARC III Cu User's Manual | |
3129 | Chapter 9: Memory Models | |
3130 | ||
3131 | UltraSPARC IIIi Processor User's Manual | |
3132 | Chapter 8: Memory Models | |
3133 | ||
3134 | UltraSPARC Architecture 2005 | |
3135 | Chapter 9: Memory | |
3136 | Appendix D: Formal Specifications of the Memory Models | |
3137 | ||
3138 | UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005 | |
3139 | Chapter 8: Memory Models | |
3140 | Appendix F: Caches and Cache Coherency | |
3141 | ||
3142 | Solaris Internals, Core Kernel Architecture, p63-68: | |
3143 | Chapter 3.3: Hardware Considerations for Locks and | |
3144 | Synchronization | |
3145 | ||
3146 | Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching | |
3147 | for Kernel Programmers: | |
3148 | Chapter 13: Other Memory Models | |
3149 | ||
3150 | Intel Itanium Architecture Software Developer's Manual: Volume 1: | |
3151 | Section 2.6: Speculation | |
3152 | Section 4.4: Memory Access |