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1PINCTRL (PIN CONTROL) subsystem
2This document outlines the pin control subsystem in Linux
3
4This subsystem deals with:
5
6- Enumerating and naming controllable pins
7
8- Multiplexing of pins, pads, fingers (etc) see below for details
9
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10- Configuration of pins, pads, fingers (etc), such as software-controlled
11 biasing and driving mode specific pins, such as pull-up/down, open drain,
12 load capacitance etc.
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13
14Top-level interface
15===================
16
17Definition of PIN CONTROLLER:
18
19- A pin controller is a piece of hardware, usually a set of registers, that
20 can control PINs. It may be able to multiplex, bias, set load capacitance,
4dfb0bd7 21 set drive strength, etc. for individual pins or groups of pins.
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22
23Definition of PIN:
24
25- PINS are equal to pads, fingers, balls or whatever packaging input or
26 output line you want to control and these are denoted by unsigned integers
27 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28 there may be several such number spaces in a system. This pin space may
29 be sparse - i.e. there may be gaps in the space with numbers where no
30 pin exists.
31
336cdba0 32When a PIN CONTROLLER is instantiated, it will register a descriptor to the
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33pin control framework, and this descriptor contains an array of pin descriptors
34describing the pins handled by this specific pin controller.
35
36Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
37
38 A B C D E F G H
39
40 8 o o o o o o o o
41
42 7 o o o o o o o o
43
44 6 o o o o o o o o
45
46 5 o o o o o o o o
47
48 4 o o o o o o o o
49
50 3 o o o o o o o o
51
52 2 o o o o o o o o
53
54 1 o o o o o o o o
55
56To register a pin controller and name all the pins on this package we can do
57this in our driver:
58
59#include <linux/pinctrl/pinctrl.h>
60
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61const struct pinctrl_pin_desc foo_pins[] = {
62 PINCTRL_PIN(0, "A8"),
63 PINCTRL_PIN(1, "B8"),
64 PINCTRL_PIN(2, "C8"),
2744e8af 65 ...
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66 PINCTRL_PIN(61, "F1"),
67 PINCTRL_PIN(62, "G1"),
68 PINCTRL_PIN(63, "H1"),
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69};
70
71static struct pinctrl_desc foo_desc = {
72 .name = "foo",
73 .pins = foo_pins,
74 .npins = ARRAY_SIZE(foo_pins),
75 .maxpin = 63,
76 .owner = THIS_MODULE,
77};
78
79int __init foo_probe(void)
80{
81 struct pinctrl_dev *pctl;
82
83 pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
e2b86b84 84 if (!pctl)
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85 pr_err("could not register foo pin driver\n");
86}
87
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88To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
89selected drivers, you need to select them from your machine's Kconfig entry,
90since these are so tightly integrated with the machines they are used on.
91See for example arch/arm/mach-u300/Kconfig for an example.
92
4dfb0bd7 93Pins usually have fancier names than this. You can find these in the datasheet
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94for your chip. Notice that the core pinctrl.h file provides a fancy macro
95called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
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96the pins from 0 in the upper left corner to 63 in the lower right corner.
97This enumeration was arbitrarily chosen, in practice you need to think
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98through your numbering system so that it matches the layout of registers
99and such things in your driver, or the code may become complicated. You must
100also consider matching of offsets to the GPIO ranges that may be handled by
101the pin controller.
102
103For a padring with 467 pads, as opposed to actual pins, I used an enumeration
104like this, walking around the edge of the chip, which seems to be industry
105standard too (all these pads had names, too):
106
107
108 0 ..... 104
109 466 105
110 . .
111 . .
112 358 224
113 357 .... 225
114
115
116Pin groups
117==========
118
119Many controllers need to deal with groups of pins, so the pin controller
120subsystem has a mechanism for enumerating groups of pins and retrieving the
121actual enumerated pins that are part of a certain group.
122
123For example, say that we have a group of pins dealing with an SPI interface
124on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
125on { 24, 25 }.
126
127These two groups are presented to the pin control subsystem by implementing
128some generic pinctrl_ops like this:
129
130#include <linux/pinctrl/pinctrl.h>
131
132struct foo_group {
133 const char *name;
134 const unsigned int *pins;
135 const unsigned num_pins;
136};
137
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138static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
139static const unsigned int i2c0_pins[] = { 24, 25 };
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140
141static const struct foo_group foo_groups[] = {
142 {
143 .name = "spi0_grp",
144 .pins = spi0_pins,
145 .num_pins = ARRAY_SIZE(spi0_pins),
146 },
147 {
148 .name = "i2c0_grp",
149 .pins = i2c0_pins,
150 .num_pins = ARRAY_SIZE(i2c0_pins),
151 },
152};
153
154
d1e90e9e 155static int foo_get_groups_count(struct pinctrl_dev *pctldev)
2744e8af 156{
d1e90e9e 157 return ARRAY_SIZE(foo_groups);
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158}
159
160static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
161 unsigned selector)
162{
163 return foo_groups[selector].name;
164}
165
166static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
167 unsigned ** const pins,
168 unsigned * const num_pins)
169{
170 *pins = (unsigned *) foo_groups[selector].pins;
171 *num_pins = foo_groups[selector].num_pins;
172 return 0;
173}
174
175static struct pinctrl_ops foo_pctrl_ops = {
d1e90e9e 176 .get_groups_count = foo_get_groups_count,
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177 .get_group_name = foo_get_group_name,
178 .get_group_pins = foo_get_group_pins,
179};
180
181
182static struct pinctrl_desc foo_desc = {
183 ...
184 .pctlops = &foo_pctrl_ops,
185};
186
d1e90e9e 187The pin control subsystem will call the .get_groups_count() function to
4dfb0bd7 188determine the total number of legal selectors, then it will call the other functions
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189to retrieve the name and pins of the group. Maintaining the data structure of
190the groups is up to the driver, this is just a simple example - in practice you
191may need more entries in your group structure, for example specific register
192ranges associated with each group and so on.
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193
194
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195Pin configuration
196=================
197
4dfb0bd7 198Pins can sometimes be software-configured in various ways, mostly related
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199to their electronic properties when used as inputs or outputs. For example you
200may be able to make an output pin high impedance, or "tristate" meaning it is
201effectively disconnected. You may be able to connect an input pin to VDD or GND
202using a certain resistor value - pull up and pull down - so that the pin has a
203stable value when nothing is driving the rail it is connected to, or when it's
204unconnected.
205
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206Pin configuration can be programmed by adding configuration entries into the
207mapping table; see section "Board/machine configuration" below.
ae6b4d85 208
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209The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
210above, is entirely defined by the pin controller driver.
211
212The pin configuration driver implements callbacks for changing pin
213configuration in the pin controller ops like this:
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214
215#include <linux/pinctrl/pinctrl.h>
216#include <linux/pinctrl/pinconf.h>
217#include "platform_x_pindefs.h"
218
e6337c3c 219static int foo_pin_config_get(struct pinctrl_dev *pctldev,
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220 unsigned offset,
221 unsigned long *config)
222{
223 struct my_conftype conf;
224
225 ... Find setting for pin @ offset ...
226
227 *config = (unsigned long) conf;
228}
229
e6337c3c 230static int foo_pin_config_set(struct pinctrl_dev *pctldev,
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231 unsigned offset,
232 unsigned long config)
233{
234 struct my_conftype *conf = (struct my_conftype *) config;
235
236 switch (conf) {
237 case PLATFORM_X_PULL_UP:
238 ...
239 }
240 }
241}
242
e6337c3c 243static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
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244 unsigned selector,
245 unsigned long *config)
246{
247 ...
248}
249
e6337c3c 250static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
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251 unsigned selector,
252 unsigned long config)
253{
254 ...
255}
256
257static struct pinconf_ops foo_pconf_ops = {
258 .pin_config_get = foo_pin_config_get,
259 .pin_config_set = foo_pin_config_set,
260 .pin_config_group_get = foo_pin_config_group_get,
261 .pin_config_group_set = foo_pin_config_group_set,
262};
263
264/* Pin config operations are handled by some pin controller */
265static struct pinctrl_desc foo_desc = {
266 ...
267 .confops = &foo_pconf_ops,
268};
269
270Since some controllers have special logic for handling entire groups of pins
271they can exploit the special whole-group pin control function. The
272pin_config_group_set() callback is allowed to return the error code -EAGAIN,
273for groups it does not want to handle, or if it just wants to do some
274group-level handling and then fall through to iterate over all pins, in which
275case each individual pin will be treated by separate pin_config_set() calls as
276well.
277
278
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279Interaction with the GPIO subsystem
280===================================
281
282The GPIO drivers may want to perform operations of various types on the same
283physical pins that are also registered as pin controller pins.
284
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285First and foremost, the two subsystems can be used as completely orthogonal,
286see the section named "pin control requests from drivers" and
287"drivers needing both pin control and GPIOs" below for details. But in some
288situations a cross-subsystem mapping between pins and GPIOs is needed.
289
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290Since the pin controller subsystem have its pinspace local to the pin
291controller we need a mapping so that the pin control subsystem can figure out
292which pin controller handles control of a certain GPIO pin. Since a single
293pin controller may be muxing several GPIO ranges (typically SoCs that have
4dfb0bd7 294one set of pins, but internally several GPIO silicon blocks, each modelled as
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295a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
296instance like this:
297
298struct gpio_chip chip_a;
299struct gpio_chip chip_b;
300
301static struct pinctrl_gpio_range gpio_range_a = {
302 .name = "chip a",
303 .id = 0,
304 .base = 32,
3c739ad0 305 .pin_base = 32,
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306 .npins = 16,
307 .gc = &chip_a;
308};
309
3c739ad0 310static struct pinctrl_gpio_range gpio_range_b = {
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311 .name = "chip b",
312 .id = 0,
313 .base = 48,
3c739ad0 314 .pin_base = 64,
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315 .npins = 8,
316 .gc = &chip_b;
317};
318
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319{
320 struct pinctrl_dev *pctl;
321 ...
322 pinctrl_add_gpio_range(pctl, &gpio_range_a);
323 pinctrl_add_gpio_range(pctl, &gpio_range_b);
324}
325
326So this complex system has one pin controller handling two different
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327GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
328"chip b" have different .pin_base, which means a start pin number of the
329GPIO range.
330
331The GPIO range of "chip a" starts from the GPIO base of 32 and actual
332pin range also starts from 32. However "chip b" has different starting
333offset for the GPIO range and pin range. The GPIO range of "chip b" starts
334from GPIO number 48, while the pin range of "chip b" starts from 64.
2744e8af 335
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336We can convert a gpio number to actual pin number using this "pin_base".
337They are mapped in the global GPIO pin space at:
338
339chip a:
340 - GPIO range : [32 .. 47]
341 - pin range : [32 .. 47]
342chip b:
343 - GPIO range : [48 .. 55]
344 - pin range : [64 .. 71]
2744e8af 345
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346The above examples assume the mapping between the GPIOs and pins is
347linear. If the mapping is sparse or haphazard, an array of arbitrary pin
348numbers can be encoded in the range like this:
349
350static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
351
352static struct pinctrl_gpio_range gpio_range = {
353 .name = "chip",
354 .id = 0,
355 .base = 32,
356 .pins = &range_pins,
357 .npins = ARRAY_SIZE(range_pins),
358 .gc = &chip;
359};
360
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361In this case the pin_base property will be ignored. If the name of a pin
362group is known, the pins and npins elements of the above structure can be
363initialised using the function pinctrl_get_group_pins(), e.g. for pin
364group "foo":
365
366pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
30cf821e 367
2744e8af 368When GPIO-specific functions in the pin control subsystem are called, these
336cdba0 369ranges will be used to look up the appropriate pin controller by inspecting
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370and matching the pin to the pin ranges across all controllers. When a
371pin controller handling the matching range is found, GPIO-specific functions
372will be called on that specific pin controller.
373
374For all functionalities dealing with pin biasing, pin muxing etc, the pin
30cf821e 375controller subsystem will look up the corresponding pin number from the passed
4dfb0bd7 376in gpio number, and use the range's internals to retrieve a pin number. After
30cf821e 377that, the subsystem passes it on to the pin control driver, so the driver
4dfb0bd7 378will get a pin number into its handled number range. Further it is also passed
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379the range ID value, so that the pin controller knows which range it should
380deal with.
381
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382Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
383section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
384pinctrl and gpio drivers.
c31a00cd 385
30cf821e 386
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387PINMUX interfaces
388=================
389
390These calls use the pinmux_* naming prefix. No other calls should use that
391prefix.
392
393
394What is pinmuxing?
395==================
396
397PINMUX, also known as padmux, ballmux, alternate functions or mission modes
398is a way for chip vendors producing some kind of electrical packages to use
399a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
400functions, depending on the application. By "application" in this context
401we usually mean a way of soldering or wiring the package into an electronic
402system, even though the framework makes it possible to also change the function
403at runtime.
404
405Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
406
407 A B C D E F G H
408 +---+
409 8 | o | o o o o o o o
410 | |
411 7 | o | o o o o o o o
412 | |
413 6 | o | o o o o o o o
414 +---+---+
415 5 | o | o | o o o o o o
416 +---+---+ +---+
417 4 o o o o o o | o | o
418 | |
419 3 o o o o o o | o | o
420 | |
421 2 o o o o o o | o | o
422 +-------+-------+-------+---+---+
423 1 | o o | o o | o o | o | o |
424 +-------+-------+-------+---+---+
425
426This is not tetris. The game to think of is chess. Not all PGA/BGA packages
427are chessboard-like, big ones have "holes" in some arrangement according to
428different design patterns, but we're using this as a simple example. Of the
429pins you see some will be taken by things like a few VCC and GND to feed power
430to the chip, and quite a few will be taken by large ports like an external
431memory interface. The remaining pins will often be subject to pin multiplexing.
432
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433The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
434to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
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435pinctrl_register_pins() and a suitable data set as shown earlier.
436
437In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
438(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
439some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
440be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
441we cannot use the SPI port and I2C port at the same time. However in the inside
442of the package the silicon performing the SPI logic can alternatively be routed
443out on pins { G4, G3, G2, G1 }.
444
4dfb0bd7 445On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
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446special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
447consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
448{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
449port on pins { G4, G3, G2, G1 } of course.
450
451This way the silicon blocks present inside the chip can be multiplexed "muxed"
452out on different pin ranges. Often contemporary SoC (systems on chip) will
453contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
454different pins by pinmux settings.
455
456Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
457common to be able to use almost any pin as a GPIO pin if it is not currently
458in use by some other I/O port.
459
460
461Pinmux conventions
462==================
463
464The purpose of the pinmux functionality in the pin controller subsystem is to
465abstract and provide pinmux settings to the devices you choose to instantiate
466in your machine configuration. It is inspired by the clk, GPIO and regulator
467subsystems, so devices will request their mux setting, but it's also possible
468to request a single pin for e.g. GPIO.
469
470Definitions:
471
472- FUNCTIONS can be switched in and out by a driver residing with the pin
473 control subsystem in the drivers/pinctrl/* directory of the kernel. The
474 pin control driver knows the possible functions. In the example above you can
475 identify three pinmux functions, one for spi, one for i2c and one for mmc.
476
477- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
478 In this case the array could be something like: { spi0, i2c0, mmc0 }
479 for the three available functions.
480
481- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
482 function is *always* associated with a certain set of pin groups, could
483 be just a single one, but could also be many. In the example above the
484 function i2c is associated with the pins { A5, B5 }, enumerated as
485 { 24, 25 } in the controller pin space.
486
487 The Function spi is associated with pin groups { A8, A7, A6, A5 }
488 and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
489 { 38, 46, 54, 62 } respectively.
490
491 Group names must be unique per pin controller, no two groups on the same
492 controller may have the same name.
493
494- The combination of a FUNCTION and a PIN GROUP determine a certain function
495 for a certain set of pins. The knowledge of the functions and pin groups
496 and their machine-specific particulars are kept inside the pinmux driver,
497 from the outside only the enumerators are known, and the driver core can:
498
499 - Request the name of a function with a certain selector (>= 0)
500 - A list of groups associated with a certain function
501 - Request that a certain group in that list to be activated for a certain
502 function
503
504 As already described above, pin groups are in turn self-descriptive, so
505 the core will retrieve the actual pin range in a certain group from the
506 driver.
507
508- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
509 device by the board file, device tree or similar machine setup configuration
510 mechanism, similar to how regulators are connected to devices, usually by
511 name. Defining a pin controller, function and group thus uniquely identify
512 the set of pins to be used by a certain device. (If only one possible group
513 of pins is available for the function, no group name need to be supplied -
514 the core will simply select the first and only group available.)
515
516 In the example case we can define that this particular machine shall
517 use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
518 fi2c0 group gi2c0, on the primary pin controller, we get mappings
519 like these:
520
521 {
522 {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
523 {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
524 }
525
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526 Every map must be assigned a state name, pin controller, device and
527 function. The group is not compulsory - if it is omitted the first group
528 presented by the driver as applicable for the function will be selected,
529 which is useful for simple cases.
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530
531 It is possible to map several groups to the same combination of device,
532 pin controller and function. This is for cases where a certain function on
533 a certain pin controller may use different sets of pins in different
534 configurations.
535
536- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
537 PIN CONTROLLER are provided on a first-come first-serve basis, so if some
538 other device mux setting or GPIO pin request has already taken your physical
539 pin, you will be denied the use of it. To get (activate) a new setting, the
540 old one has to be put (deactivated) first.
541
542Sometimes the documentation and hardware registers will be oriented around
543pads (or "fingers") rather than pins - these are the soldering surfaces on the
544silicon inside the package, and may or may not match the actual number of
545pins/balls underneath the capsule. Pick some enumeration that makes sense to
546you. Define enumerators only for the pins you can control if that makes sense.
547
548Assumptions:
549
336cdba0 550We assume that the number of possible function maps to pin groups is limited by
2744e8af 551the hardware. I.e. we assume that there is no system where any function can be
4dfb0bd7 552mapped to any pin, like in a phone exchange. So the available pin groups for
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553a certain function will be limited to a few choices (say up to eight or so),
554not hundreds or any amount of choices. This is the characteristic we have found
555by inspecting available pinmux hardware, and a necessary assumption since we
556expect pinmux drivers to present *all* possible function vs pin group mappings
557to the subsystem.
558
559
560Pinmux drivers
561==============
562
563The pinmux core takes care of preventing conflicts on pins and calling
564the pin controller driver to execute different settings.
565
566It is the responsibility of the pinmux driver to impose further restrictions
4dfb0bd7 567(say for example infer electronic limitations due to load, etc.) to determine
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568whether or not the requested function can actually be allowed, and in case it
569is possible to perform the requested mux setting, poke the hardware so that
570this happens.
571
572Pinmux drivers are required to supply a few callback functions, some are
573optional. Usually the enable() and disable() functions are implemented,
574writing values into some certain registers to activate a certain mux setting
575for a certain pin.
576
577A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
578into some register named MUX to select a certain function with a certain
579group of pins would work something like this:
580
581#include <linux/pinctrl/pinctrl.h>
582#include <linux/pinctrl/pinmux.h>
583
584struct foo_group {
585 const char *name;
586 const unsigned int *pins;
587 const unsigned num_pins;
588};
589
590static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
591static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
592static const unsigned i2c0_pins[] = { 24, 25 };
593static const unsigned mmc0_1_pins[] = { 56, 57 };
594static const unsigned mmc0_2_pins[] = { 58, 59 };
595static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
596
597static const struct foo_group foo_groups[] = {
598 {
599 .name = "spi0_0_grp",
600 .pins = spi0_0_pins,
601 .num_pins = ARRAY_SIZE(spi0_0_pins),
602 },
603 {
604 .name = "spi0_1_grp",
605 .pins = spi0_1_pins,
606 .num_pins = ARRAY_SIZE(spi0_1_pins),
607 },
608 {
609 .name = "i2c0_grp",
610 .pins = i2c0_pins,
611 .num_pins = ARRAY_SIZE(i2c0_pins),
612 },
613 {
614 .name = "mmc0_1_grp",
615 .pins = mmc0_1_pins,
616 .num_pins = ARRAY_SIZE(mmc0_1_pins),
617 },
618 {
619 .name = "mmc0_2_grp",
620 .pins = mmc0_2_pins,
621 .num_pins = ARRAY_SIZE(mmc0_2_pins),
622 },
623 {
624 .name = "mmc0_3_grp",
625 .pins = mmc0_3_pins,
626 .num_pins = ARRAY_SIZE(mmc0_3_pins),
627 },
628};
629
630
d1e90e9e 631static int foo_get_groups_count(struct pinctrl_dev *pctldev)
2744e8af 632{
d1e90e9e 633 return ARRAY_SIZE(foo_groups);
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634}
635
636static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
637 unsigned selector)
638{
639 return foo_groups[selector].name;
640}
641
642static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
643 unsigned ** const pins,
644 unsigned * const num_pins)
645{
646 *pins = (unsigned *) foo_groups[selector].pins;
647 *num_pins = foo_groups[selector].num_pins;
648 return 0;
649}
650
651static struct pinctrl_ops foo_pctrl_ops = {
d1e90e9e 652 .get_groups_count = foo_get_groups_count,
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653 .get_group_name = foo_get_group_name,
654 .get_group_pins = foo_get_group_pins,
655};
656
657struct foo_pmx_func {
658 const char *name;
659 const char * const *groups;
660 const unsigned num_groups;
661};
662
eb181c35 663static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
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664static const char * const i2c0_groups[] = { "i2c0_grp" };
665static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
666 "mmc0_3_grp" };
667
668static const struct foo_pmx_func foo_functions[] = {
669 {
670 .name = "spi0",
671 .groups = spi0_groups,
672 .num_groups = ARRAY_SIZE(spi0_groups),
673 },
674 {
675 .name = "i2c0",
676 .groups = i2c0_groups,
677 .num_groups = ARRAY_SIZE(i2c0_groups),
678 },
679 {
680 .name = "mmc0",
681 .groups = mmc0_groups,
682 .num_groups = ARRAY_SIZE(mmc0_groups),
683 },
684};
685
d1e90e9e 686int foo_get_functions_count(struct pinctrl_dev *pctldev)
2744e8af 687{
d1e90e9e 688 return ARRAY_SIZE(foo_functions);
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689}
690
691const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
692{
336cdba0 693 return foo_functions[selector].name;
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694}
695
696static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
697 const char * const **groups,
698 unsigned * const num_groups)
699{
700 *groups = foo_functions[selector].groups;
701 *num_groups = foo_functions[selector].num_groups;
702 return 0;
703}
704
03e9f0ca 705int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
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706 unsigned group)
707{
336cdba0 708 u8 regbit = (1 << selector + group);
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709
710 writeb((readb(MUX)|regbit), MUX)
711 return 0;
712}
713
2744e8af 714struct pinmux_ops foo_pmxops = {
d1e90e9e 715 .get_functions_count = foo_get_functions_count,
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716 .get_function_name = foo_get_fname,
717 .get_function_groups = foo_get_groups,
03e9f0ca 718 .set_mux = foo_set_mux,
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719};
720
721/* Pinmux operations are handled by some pin controller */
722static struct pinctrl_desc foo_desc = {
723 ...
724 .pctlops = &foo_pctrl_ops,
725 .pmxops = &foo_pmxops,
726};
727
728In the example activating muxing 0 and 1 at the same time setting bits
7290 and 1, uses one pin in common so they would collide.
730
731The beauty of the pinmux subsystem is that since it keeps track of all
732pins and who is using them, it will already have denied an impossible
733request like that, so the driver does not need to worry about such
734things - when it gets a selector passed in, the pinmux subsystem makes
735sure no other device or GPIO assignment is already using the selected
736pins. Thus bits 0 and 1 in the control register will never be set at the
737same time.
738
739All the above functions are mandatory to implement for a pinmux driver.
740
741
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742Pin control interaction with the GPIO subsystem
743===============================================
2744e8af 744
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745Note that the following implies that the use case is to use a certain pin
746from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
747and similar functions. There are cases where you may be using something
4dfb0bd7 748that your datasheet calls "GPIO mode", but actually is just an electrical
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749configuration for a certain device. See the section below named
750"GPIO mode pitfalls" for more details on this scenario.
751
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752The public pinmux API contains two functions named pinctrl_request_gpio()
753and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
542e704f 754gpiolib-based drivers as part of their gpio_request() and
e93bcee0 755gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
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756shall only be called from within respective gpio_direction_[input|output]
757gpiolib implementation.
758
759NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
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760controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
761that driver request proper muxing and other control for its pins.
542e704f 762
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763The function list could become long, especially if you can convert every
764individual pin into a GPIO pin independent of any other pins, and then try
765the approach to define every pin as a function.
766
767In this case, the function array would become 64 entries for each GPIO
768setting and then the device functions.
769
e93bcee0 770For this reason there are two functions a pin control driver can implement
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771to enable only GPIO on an individual pin: .gpio_request_enable() and
772.gpio_disable_free().
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773
774This function will pass in the affected GPIO range identified by the pin
775controller core, so you know which GPIO pins are being affected by the request
776operation.
777
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778If your driver needs to have an indication from the framework of whether the
779GPIO pin shall be used for input or output you can implement the
780.gpio_set_direction() function. As described this shall be called from the
781gpiolib driver and the affected GPIO range, pin offset and desired direction
782will be passed along to this function.
783
784Alternatively to using these special functions, it is fully allowed to use
e93bcee0 785named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
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786obtain the function "gpioN" where "N" is the global GPIO pin number if no
787special GPIO-handler is registered.
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788
789
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790GPIO mode pitfalls
791==================
792
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793Due to the naming conventions used by hardware engineers, where "GPIO"
794is taken to mean different things than what the kernel does, the developer
795may be confused by a datasheet talking about a pin being possible to set
796into "GPIO mode". It appears that what hardware engineers mean with
797"GPIO mode" is not necessarily the use case that is implied in the kernel
798interface <linux/gpio.h>: a pin that you grab from kernel code and then
799either listen for input or drive high/low to assert/deassert some
800external line.
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801
802Rather hardware engineers think that "GPIO mode" means that you can
803software-control a few electrical properties of the pin that you would
804not be able to control if the pin was in some other mode, such as muxed in
805for a device.
806
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807The GPIO portions of a pin and its relation to a certain pin controller
808configuration and muxing logic can be constructed in several ways. Here
809are two examples:
810
811(A)
812 pin config
813 logic regs
814 | +- SPI
815 Physical pins --- pad --- pinmux -+- I2C
816 | +- mmc
817 | +- GPIO
818 pin
819 multiplex
820 logic regs
821
822Here some electrical properties of the pin can be configured no matter
823whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
824pin, you can also drive it high/low from "GPIO" registers.
825Alternatively, the pin can be controlled by a certain peripheral, while
826still applying desired pin config properties. GPIO functionality is thus
827orthogonal to any other device using the pin.
828
829In this arrangement the registers for the GPIO portions of the pin controller,
830or the registers for the GPIO hardware module are likely to reside in a
831separate memory range only intended for GPIO driving, and the register
832range dealing with pin config and pin multiplexing get placed into a
833different memory range and a separate section of the data sheet.
834
835(B)
836
837 pin config
838 logic regs
839 | +- SPI
840 Physical pins --- pad --- pinmux -+- I2C
841 | | +- mmc
842 | |
843 GPIO pin
844 multiplex
845 logic regs
846
847In this arrangement, the GPIO functionality can always be enabled, such that
848e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
849pulsed out. It is likely possible to disrupt the traffic on the pin by doing
850wrong things on the GPIO block, as it is never really disconnected. It is
851possible that the GPIO, pin config and pin multiplex registers are placed into
852the same memory range and the same section of the data sheet, although that
853need not be the case.
854
855From a kernel point of view, however, these are different aspects of the
856hardware and shall be put into different subsystems:
857
858- Registers (or fields within registers) that control electrical
859 properties of the pin such as biasing and drive strength should be
860 exposed through the pinctrl subsystem, as "pin configuration" settings.
861
862- Registers (or fields within registers) that control muxing of signals
863 from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
4dfb0bd7 864 be exposed through the pinctrl subsystem, as mux functions.
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865
866- Registers (or fields within registers) that control GPIO functionality
867 such as setting a GPIO's output value, reading a GPIO's input value, or
868 setting GPIO pin direction should be exposed through the GPIO subsystem,
869 and if they also support interrupt capabilities, through the irqchip
870 abstraction.
871
872Depending on the exact HW register design, some functions exposed by the
873GPIO subsystem may call into the pinctrl subsystem in order to
874co-ordinate register settings across HW modules. In particular, this may
875be needed for HW with separate GPIO and pin controller HW modules, where
876e.g. GPIO direction is determined by a register in the pin controller HW
877module rather than the GPIO HW module.
878
879Electrical properties of the pin such as biasing and drive strength
880may be placed at some pin-specific register in all cases or as part
881of the GPIO register in case (B) especially. This doesn't mean that such
882properties necessarily pertain to what the Linux kernel calls "GPIO".
883
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884Example: a pin is usually muxed in to be used as a UART TX line. But during
885system sleep, we need to put this pin into "GPIO mode" and ground it.
886
887If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
4dfb0bd7 888to think that you need to come up with something really complex, that the
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889pin shall be used for UART TX and GPIO at the same time, that you will grab
890a pin control handle and set it to a certain state to enable UART TX to be
891muxed in, then twist it over to GPIO mode and use gpio_direction_output()
892to drive it low during sleep, then mux it over to UART TX again when you
893wake up and maybe even gpio_request/gpio_free as part of this cycle. This
894all gets very complicated.
895
896The solution is to not think that what the datasheet calls "GPIO mode"
897has to be handled by the <linux/gpio.h> interface. Instead view this as
898a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
899and you find this in the documentation:
900
901 PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
902 1 to indicate high level, argument 0 to indicate low level.
903
904So it is perfectly possible to push a pin into "GPIO mode" and drive the
905line low as part of the usual pin control map. So for example your UART
906driver may look like this:
907
908#include <linux/pinctrl/consumer.h>
909
910struct pinctrl *pinctrl;
911struct pinctrl_state *pins_default;
912struct pinctrl_state *pins_sleep;
913
914pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
915pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
916
917/* Normal mode */
918retval = pinctrl_select_state(pinctrl, pins_default);
919/* Sleep mode */
920retval = pinctrl_select_state(pinctrl, pins_sleep);
921
922And your machine configuration may look like this:
923--------------------------------------------------
924
925static unsigned long uart_default_mode[] = {
926 PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
927};
928
929static unsigned long uart_sleep_mode[] = {
930 PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
931};
932
2868a074 933static struct pinctrl_map pinmap[] __initdata = {
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934 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
935 "u0_group", "u0"),
936 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
937 "UART_TX_PIN", uart_default_mode),
938 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
939 "u0_group", "gpio-mode"),
940 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
941 "UART_TX_PIN", uart_sleep_mode),
942};
943
944foo_init(void) {
945 pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
946}
947
948Here the pins we want to control are in the "u0_group" and there is some
949function called "u0" that can be enabled on this group of pins, and then
950everything is UART business as usual. But there is also some function
951named "gpio-mode" that can be mapped onto the same pins to move them into
952GPIO mode.
953
954This will give the desired effect without any bogus interaction with the
955GPIO subsystem. It is just an electrical configuration used by that device
956when going to sleep, it might imply that the pin is set into something the
4dfb0bd7 957datasheet calls "GPIO mode", but that is not the point: it is still used
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958by that UART device to control the pins that pertain to that very UART
959driver, putting them into modes needed by the UART. GPIO in the Linux
960kernel sense are just some 1-bit line, and is a different use case.
961
4dfb0bd7 962How the registers are poked to attain the push or pull, and output low
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963configuration and the muxing of the "u0" or "gpio-mode" group onto these
964pins is a question for the driver.
965
966Some datasheets will be more helpful and refer to the "GPIO mode" as
967"low power mode" rather than anything to do with GPIO. This often means
968the same thing electrically speaking, but in this latter case the
969software engineers will usually quickly identify that this is some
4dfb0bd7 970specific muxing or configuration rather than anything related to the GPIO
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971API.
972
973
1e2082b5 974Board/machine configuration
2744e8af
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975==================================
976
977Boards and machines define how a certain complete running system is put
978together, including how GPIOs and devices are muxed, how regulators are
979constrained and how the clock tree looks. Of course pinmux settings are also
980part of this.
981
1e2082b5
SW
982A pin controller configuration for a machine looks pretty much like a simple
983regulator configuration, so for the example array above we want to enable i2c
984and spi on the second function mapping:
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985
986#include <linux/pinctrl/machine.h>
987
122dbe7e 988static const struct pinctrl_map mapping[] __initconst = {
2744e8af 989 {
806d3143 990 .dev_name = "foo-spi.0",
110e4ec5 991 .name = PINCTRL_STATE_DEFAULT,
1e2082b5 992 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 993 .ctrl_dev_name = "pinctrl-foo",
1e2082b5 994 .data.mux.function = "spi0",
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995 },
996 {
806d3143 997 .dev_name = "foo-i2c.0",
110e4ec5 998 .name = PINCTRL_STATE_DEFAULT,
1e2082b5 999 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1000 .ctrl_dev_name = "pinctrl-foo",
1e2082b5 1001 .data.mux.function = "i2c0",
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1002 },
1003 {
806d3143 1004 .dev_name = "foo-mmc.0",
110e4ec5 1005 .name = PINCTRL_STATE_DEFAULT,
1e2082b5 1006 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1007 .ctrl_dev_name = "pinctrl-foo",
1e2082b5 1008 .data.mux.function = "mmc0",
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1009 },
1010};
1011
1012The dev_name here matches to the unique device name that can be used to look
1013up the device struct (just like with clockdev or regulators). The function name
1014must match a function provided by the pinmux driver handling this pin range.
1015
1016As you can see we may have several pin controllers on the system and thus
4dfb0bd7 1017we need to specify which one of them contains the functions we wish to map.
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1018
1019You register this pinmux mapping to the pinmux subsystem by simply:
1020
e93bcee0 1021 ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
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1022
1023Since the above construct is pretty common there is a helper macro to make
51cd24ee 1024it even more compact which assumes you want to use pinctrl-foo and position
2744e8af
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10250 for mapping, for example:
1026
2868a074 1027static struct pinctrl_map mapping[] __initdata = {
1e2082b5
SW
1028 PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
1029};
1030
1031The mapping table may also contain pin configuration entries. It's common for
1032each pin/group to have a number of configuration entries that affect it, so
1033the table entries for configuration reference an array of config parameters
1034and values. An example using the convenience macros is shown below:
1035
1036static unsigned long i2c_grp_configs[] = {
1037 FOO_PIN_DRIVEN,
1038 FOO_PIN_PULLUP,
1039};
1040
1041static unsigned long i2c_pin_configs[] = {
1042 FOO_OPEN_COLLECTOR,
1043 FOO_SLEW_RATE_SLOW,
1044};
1045
2868a074 1046static struct pinctrl_map mapping[] __initdata = {
1e2082b5 1047 PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
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1048 PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
1049 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1050 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
1e2082b5
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1051};
1052
1053Finally, some devices expect the mapping table to contain certain specific
1054named states. When running on hardware that doesn't need any pin controller
1055configuration, the mapping table must still contain those named states, in
1056order to explicitly indicate that the states were provided and intended to
1057be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
1058a named state without causing any pin controller to be programmed:
1059
2868a074 1060static struct pinctrl_map mapping[] __initdata = {
1e2082b5 1061 PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
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1062};
1063
1064
1065Complex mappings
1066================
1067
1068As it is possible to map a function to different groups of pins an optional
1069.group can be specified like this:
1070
1071...
1072{
806d3143 1073 .dev_name = "foo-spi.0",
2744e8af 1074 .name = "spi0-pos-A",
1e2082b5 1075 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1076 .ctrl_dev_name = "pinctrl-foo",
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1077 .function = "spi0",
1078 .group = "spi0_0_grp",
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1079},
1080{
806d3143 1081 .dev_name = "foo-spi.0",
2744e8af 1082 .name = "spi0-pos-B",
1e2082b5 1083 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1084 .ctrl_dev_name = "pinctrl-foo",
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1085 .function = "spi0",
1086 .group = "spi0_1_grp",
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1087},
1088...
1089
1090This example mapping is used to switch between two positions for spi0 at
1091runtime, as described further below under the heading "Runtime pinmuxing".
1092
6e5e959d
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1093Further it is possible for one named state to affect the muxing of several
1094groups of pins, say for example in the mmc0 example above, where you can
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1095additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1096three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1097case), we define a mapping like this:
1098
1099...
1100{
806d3143 1101 .dev_name = "foo-mmc.0",
f54367f9 1102 .name = "2bit"
1e2082b5 1103 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1104 .ctrl_dev_name = "pinctrl-foo",
2744e8af 1105 .function = "mmc0",
336cdba0 1106 .group = "mmc0_1_grp",
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1107},
1108{
806d3143 1109 .dev_name = "foo-mmc.0",
f54367f9 1110 .name = "4bit"
1e2082b5 1111 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1112 .ctrl_dev_name = "pinctrl-foo",
2744e8af 1113 .function = "mmc0",
336cdba0 1114 .group = "mmc0_1_grp",
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1115},
1116{
806d3143 1117 .dev_name = "foo-mmc.0",
f54367f9 1118 .name = "4bit"
1e2082b5 1119 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1120 .ctrl_dev_name = "pinctrl-foo",
2744e8af 1121 .function = "mmc0",
336cdba0 1122 .group = "mmc0_2_grp",
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1123},
1124{
806d3143 1125 .dev_name = "foo-mmc.0",
f54367f9 1126 .name = "8bit"
1e2082b5 1127 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1128 .ctrl_dev_name = "pinctrl-foo",
6e5e959d 1129 .function = "mmc0",
336cdba0 1130 .group = "mmc0_1_grp",
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1131},
1132{
806d3143 1133 .dev_name = "foo-mmc.0",
f54367f9 1134 .name = "8bit"
1e2082b5 1135 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1136 .ctrl_dev_name = "pinctrl-foo",
2744e8af 1137 .function = "mmc0",
336cdba0 1138 .group = "mmc0_2_grp",
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1139},
1140{
806d3143 1141 .dev_name = "foo-mmc.0",
f54367f9 1142 .name = "8bit"
1e2082b5 1143 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1144 .ctrl_dev_name = "pinctrl-foo",
2744e8af 1145 .function = "mmc0",
336cdba0 1146 .group = "mmc0_3_grp",
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1147},
1148...
1149
1150The result of grabbing this mapping from the device with something like
1151this (see next paragraph):
1152
6d4ca1fb 1153 p = devm_pinctrl_get(dev);
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SW
1154 s = pinctrl_lookup_state(p, "8bit");
1155 ret = pinctrl_select_state(p, s);
1156
1157or more simply:
1158
6d4ca1fb 1159 p = devm_pinctrl_get_select(dev, "8bit");
2744e8af
LW
1160
1161Will be that you activate all the three bottom records in the mapping at
6e5e959d 1162once. Since they share the same name, pin controller device, function and
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LW
1163device, and since we allow multiple groups to match to a single device, they
1164all get selected, and they all get enabled and disable simultaneously by the
1165pinmux core.
1166
1167
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LW
1168Pin control requests from drivers
1169=================================
2744e8af 1170
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LW
1171When a device driver is about to probe the device core will automatically
1172attempt to issue pinctrl_get_select_default() on these devices.
1173This way driver writers do not need to add any of the boilerplate code
1174of the type found below. However when doing fine-grained state selection
1175and not using the "default" state, you may have to do some device driver
1176handling of the pinctrl handles and states.
1177
1178So if you just want to put the pins for a certain device into the default
1179state and be done with it, there is nothing you need to do besides
1180providing the proper mapping table. The device core will take care of
1181the rest.
1182
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LW
1183Generally it is discouraged to let individual drivers get and enable pin
1184control. So if possible, handle the pin control in platform code or some other
1185place where you have access to all the affected struct device * pointers. In
1186some cases where a driver needs to e.g. switch between different mux mappings
1187at runtime this is not possible.
2744e8af 1188
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LW
1189A typical case is if a driver needs to switch bias of pins from normal
1190operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1191PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1192current in sleep mode.
1193
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LW
1194A driver may request a certain control state to be activated, usually just the
1195default state like this:
2744e8af 1196
28a8d14c 1197#include <linux/pinctrl/consumer.h>
2744e8af
LW
1198
1199struct foo_state {
e93bcee0 1200 struct pinctrl *p;
6e5e959d 1201 struct pinctrl_state *s;
2744e8af
LW
1202 ...
1203};
1204
1205foo_probe()
1206{
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SW
1207 /* Allocate a state holder named "foo" etc */
1208 struct foo_state *foo = ...;
1209
6d4ca1fb 1210 foo->p = devm_pinctrl_get(&device);
6e5e959d
SW
1211 if (IS_ERR(foo->p)) {
1212 /* FIXME: clean up "foo" here */
1213 return PTR_ERR(foo->p);
1214 }
2744e8af 1215
6e5e959d
SW
1216 foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1217 if (IS_ERR(foo->s)) {
6e5e959d
SW
1218 /* FIXME: clean up "foo" here */
1219 return PTR_ERR(s);
1220 }
2744e8af 1221
6e5e959d
SW
1222 ret = pinctrl_select_state(foo->s);
1223 if (ret < 0) {
6e5e959d
SW
1224 /* FIXME: clean up "foo" here */
1225 return ret;
1226 }
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LW
1227}
1228
6e5e959d 1229This get/lookup/select/put sequence can just as well be handled by bus drivers
2744e8af
LW
1230if you don't want each and every driver to handle it and you know the
1231arrangement on your bus.
1232
6e5e959d
SW
1233The semantics of the pinctrl APIs are:
1234
1235- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1236 information for a given client device. It will allocate a struct from the
1237 kernel memory to hold the pinmux state. All mapping table parsing or similar
1238 slow operations take place within this API.
2744e8af 1239
6d4ca1fb
SW
1240- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1241 to be called automatically on the retrieved pointer when the associated
1242 device is removed. It is recommended to use this function over plain
1243 pinctrl_get().
1244
6e5e959d 1245- pinctrl_lookup_state() is called in process context to obtain a handle to a
4dfb0bd7 1246 specific state for a client device. This operation may be slow, too.
2744e8af 1247
6e5e959d 1248- pinctrl_select_state() programs pin controller hardware according to the
4dfb0bd7 1249 definition of the state as given by the mapping table. In theory, this is a
6e5e959d
SW
1250 fast-path operation, since it only involved blasting some register settings
1251 into hardware. However, note that some pin controllers may have their
1252 registers on a slow/IRQ-based bus, so client devices should not assume they
1253 can call pinctrl_select_state() from non-blocking contexts.
2744e8af 1254
6e5e959d 1255- pinctrl_put() frees all information associated with a pinctrl handle.
2744e8af 1256
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SW
1257- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1258 explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1259 However, use of this function will be rare, due to the automatic cleanup
1260 that will occur even without calling it.
1261
1262 pinctrl_get() must be paired with a plain pinctrl_put().
1263 pinctrl_get() may not be paired with devm_pinctrl_put().
1264 devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1265 devm_pinctrl_get() may not be paired with plain pinctrl_put().
1266
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1267Usually the pin control core handled the get/put pair and call out to the
1268device drivers bookkeeping operations, like checking available functions and
1269the associated pins, whereas the enable/disable pass on to the pin controller
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LW
1270driver which takes care of activating and/or deactivating the mux setting by
1271quickly poking some registers.
1272
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1273The pins are allocated for your device when you issue the devm_pinctrl_get()
1274call, after this you should be able to see this in the debugfs listing of all
1275pins.
2744e8af 1276
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LW
1277NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1278requested pinctrl handles, for example if the pinctrl driver has not yet
1279registered. Thus make sure that the error path in your driver gracefully
1280cleans up and is ready to retry the probing later in the startup process.
1281
2744e8af 1282
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LW
1283Drivers needing both pin control and GPIOs
1284==========================================
1285
1286Again, it is discouraged to let drivers lookup and select pin control states
1287themselves, but again sometimes this is unavoidable.
1288
1289So say that your driver is fetching its resources like this:
1290
1291#include <linux/pinctrl/consumer.h>
1292#include <linux/gpio.h>
1293
1294struct pinctrl *pinctrl;
1295int gpio;
1296
1297pinctrl = devm_pinctrl_get_select_default(&dev);
1298gpio = devm_gpio_request(&dev, 14, "foo");
1299
1300Here we first request a certain pin state and then request GPIO 14 to be
1301used. If you're using the subsystems orthogonally like this, you should
1302nominally always get your pinctrl handle and select the desired pinctrl
1303state BEFORE requesting the GPIO. This is a semantic convention to avoid
1304situations that can be electrically unpleasant, you will certainly want to
1305mux in and bias pins in a certain way before the GPIO subsystems starts to
1306deal with them.
1307
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LW
1308The above can be hidden: using the device core, the pinctrl core may be
1309setting up the config and muxing for the pins right before the device is
1310probing, nevertheless orthogonal to the GPIO subsystem.
c31a00cd
LW
1311
1312But there are also situations where it makes sense for the GPIO subsystem
7bbc87b8
JH
1313to communicate directly with the pinctrl subsystem, using the latter as a
1314back-end. This is when the GPIO driver may call out to the functions
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LW
1315described in the section "Pin control interaction with the GPIO subsystem"
1316above. This only involves per-pin multiplexing, and will be completely
1317hidden behind the gpio_*() function namespace. In this case, the driver
1318need not interact with the pin control subsystem at all.
1319
1320If a pin control driver and a GPIO driver is dealing with the same pins
1321and the use cases involve multiplexing, you MUST implement the pin controller
1322as a back-end for the GPIO driver like this, unless your hardware design
1323is such that the GPIO controller can override the pin controller's
1324multiplexing state through hardware without the need to interact with the
1325pin control system.
1326
1327
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LW
1328System pin control hogging
1329==========================
2744e8af 1330
1681f5ae 1331Pin control map entries can be hogged by the core when the pin controller
6e5e959d
SW
1332is registered. This means that the core will attempt to call pinctrl_get(),
1333lookup_state() and select_state() on it immediately after the pin control
1334device has been registered.
2744e8af 1335
6e5e959d
SW
1336This occurs for mapping table entries where the client device name is equal
1337to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
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LW
1338
1339{
806d3143 1340 .dev_name = "pinctrl-foo",
46919ae6 1341 .name = PINCTRL_STATE_DEFAULT,
1e2082b5 1342 .type = PIN_MAP_TYPE_MUX_GROUP,
51cd24ee 1343 .ctrl_dev_name = "pinctrl-foo",
2744e8af 1344 .function = "power_func",
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LW
1345},
1346
1347Since it may be common to request the core to hog a few always-applicable
1348mux settings on the primary pin controller, there is a convenience macro for
1349this:
1350
1e2082b5 1351PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
2744e8af
LW
1352
1353This gives the exact same result as the above construction.
1354
1355
1356Runtime pinmuxing
1357=================
1358
1359It is possible to mux a certain function in and out at runtime, say to move
1360an SPI port from one set of pins to another set of pins. Say for example for
1361spi0 in the example above, we expose two different groups of pins for the same
1362function, but with different named in the mapping as described under
6e5e959d
SW
1363"Advanced mapping" above. So that for an SPI device, we have two states named
1364"pos-A" and "pos-B".
2744e8af
LW
1365
1366This snippet first muxes the function in the pins defined by group A, enables
1367it, disables and releases it, and muxes it in on the pins defined by group B:
1368
28a8d14c
LW
1369#include <linux/pinctrl/consumer.h>
1370
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SW
1371struct pinctrl *p;
1372struct pinctrl_state *s1, *s2;
6e5e959d 1373
6d4ca1fb
SW
1374foo_probe()
1375{
6e5e959d 1376 /* Setup */
6d4ca1fb 1377 p = devm_pinctrl_get(&device);
6e5e959d
SW
1378 if (IS_ERR(p))
1379 ...
1380
1381 s1 = pinctrl_lookup_state(foo->p, "pos-A");
1382 if (IS_ERR(s1))
1383 ...
1384
1385 s2 = pinctrl_lookup_state(foo->p, "pos-B");
1386 if (IS_ERR(s2))
1387 ...
6d4ca1fb 1388}
2744e8af 1389
6d4ca1fb
SW
1390foo_switch()
1391{
2744e8af 1392 /* Enable on position A */
6e5e959d
SW
1393 ret = pinctrl_select_state(s1);
1394 if (ret < 0)
1395 ...
2744e8af 1396
6e5e959d 1397 ...
2744e8af
LW
1398
1399 /* Enable on position B */
6e5e959d
SW
1400 ret = pinctrl_select_state(s2);
1401 if (ret < 0)
1402 ...
1403
2744e8af
LW
1404 ...
1405}
1406
1a78958d
LW
1407The above has to be done from process context. The reservation of the pins
1408will be done when the state is activated, so in effect one specific pin
1409can be used by different functions at different times on a running system.