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1 | Booting the Linux/ppc kernel without Open Firmware |
2 | -------------------------------------------------- | |
3 | ||
c125a183 DG |
4 | (c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>, |
5 | IBM Corp. | |
6 | (c) 2005 Becky Bruce <becky.bruce at freescale.com>, | |
7 | Freescale Semiconductor, FSL SOC and 32-bit additions | |
28f9ec34 VW |
8 | (c) 2006 MontaVista Software, Inc. |
9 | Flash chip node definition | |
c125a183 | 10 | |
5e1e9ba6 SY |
11 | Table of Contents |
12 | ================= | |
13 | ||
14 | I - Introduction | |
15 | 1) Entry point for arch/powerpc | |
16 | 2) Board support | |
17 | ||
18 | II - The DT block format | |
19 | 1) Header | |
20 | 2) Device tree generalities | |
21 | 3) Device tree "structure" block | |
22 | 4) Device tree "strings" block | |
23 | ||
24 | III - Required content of the device tree | |
25 | 1) Note about cells and address representation | |
26 | 2) Note about "compatible" properties | |
27 | 3) Note about "name" properties | |
28 | 4) Note about node and property names and character set | |
29 | 5) Required nodes and properties | |
30 | a) The root node | |
31 | b) The /cpus node | |
32 | c) The /cpus/* nodes | |
33 | d) the /memory node(s) | |
34 | e) The /chosen node | |
35 | f) the /soc<SOCname> node | |
36 | ||
37 | IV - "dtc", the device tree compiler | |
38 | ||
39 | V - Recommendations for a bootloader | |
40 | ||
41 | VI - System-on-a-chip devices and nodes | |
42 | 1) Defining child nodes of an SOC | |
43 | 2) Representing devices without a current OF specification | |
ec5d7657 TP |
44 | a) PHY nodes |
45 | b) Interrupt controllers | |
efcc2da3 SR |
46 | c) 4xx/Axon EMAC ethernet nodes |
47 | d) Xilinx IP cores | |
48 | e) USB EHCI controllers | |
49 | f) MDIO on GPIOs | |
50 | g) SPI busses | |
5e1e9ba6 | 51 | |
f5412c49 DF |
52 | VII - Marvell Discovery mv64[345]6x System Controller chips |
53 | 1) The /system-controller node | |
54 | 2) Child nodes of /system-controller | |
55 | a) Marvell Discovery MDIO bus | |
56 | b) Marvell Discovery ethernet controller | |
57 | c) Marvell Discovery PHY nodes | |
58 | d) Marvell Discovery SDMA nodes | |
59 | e) Marvell Discovery BRG nodes | |
60 | f) Marvell Discovery CUNIT nodes | |
61 | g) Marvell Discovery MPSCROUTING nodes | |
62 | h) Marvell Discovery MPSCINTR nodes | |
63 | i) Marvell Discovery MPSC nodes | |
64 | j) Marvell Discovery Watch Dog Timer nodes | |
65 | k) Marvell Discovery I2C nodes | |
66 | l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes | |
67 | m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes | |
68 | n) Marvell Discovery GPP (General Purpose Pins) nodes | |
69 | o) Marvell Discovery PCI host bridge node | |
70 | p) Marvell Discovery CPU Error nodes | |
71 | q) Marvell Discovery SRAM Controller nodes | |
72 | r) Marvell Discovery PCI Error Handler nodes | |
73 | s) Marvell Discovery Memory Controller nodes | |
74 | ||
75 | VIII - Specifying interrupt information for devices | |
5e1e9ba6 SY |
76 | 1) interrupts property |
77 | 2) interrupt-parent property | |
78 | 3) OpenPIC Interrupt Controllers | |
79 | 4) ISA Interrupt Controllers | |
80 | ||
2dff4177 | 81 | IX - Specifying GPIO information for devices |
b7ce3415 AV |
82 | 1) gpios property |
83 | 2) gpio-controller nodes | |
84 | ||
2dff4177 SW |
85 | X - Specifying device power management information (sleep property) |
86 | ||
5e1e9ba6 SY |
87 | Appendix A - Sample SOC node for MPC8540 |
88 | ||
89 | ||
90 | Revision Information | |
91 | ==================== | |
92 | ||
c125a183 DG |
93 | May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet. |
94 | ||
95 | May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or | |
96 | clarifies the fact that a lot of things are | |
97 | optional, the kernel only requires a very | |
98 | small device tree, though it is encouraged | |
99 | to provide an as complete one as possible. | |
100 | ||
101 | May 24, 2005: Rev 0.3 - Precise that DT block has to be in RAM | |
102 | - Misc fixes | |
103 | - Define version 3 and new format version 16 | |
104 | for the DT block (version 16 needs kernel | |
105 | patches, will be fwd separately). | |
106 | String block now has a size, and full path | |
107 | is replaced by unit name for more | |
108 | compactness. | |
109 | linux,phandle is made optional, only nodes | |
110 | that are referenced by other nodes need it. | |
111 | "name" property is now automatically | |
112 | deduced from the unit name | |
113 | ||
114 | June 1, 2005: Rev 0.4 - Correct confusion between OF_DT_END and | |
115 | OF_DT_END_NODE in structure definition. | |
116 | - Change version 16 format to always align | |
117 | property data to 4 bytes. Since tokens are | |
118 | already aligned, that means no specific | |
5d3f083d | 119 | required alignment between property size |
c125a183 DG |
120 | and property data. The old style variable |
121 | alignment would make it impossible to do | |
122 | "simple" insertion of properties using | |
5dd60166 | 123 | memmove (thanks Milton for |
c125a183 | 124 | noticing). Updated kernel patch as well |
5d3f083d | 125 | - Correct a few more alignment constraints |
c125a183 DG |
126 | - Add a chapter about the device-tree |
127 | compiler and the textural representation of | |
128 | the tree that can be "compiled" by dtc. | |
129 | ||
c125a183 DG |
130 | November 21, 2005: Rev 0.5 |
131 | - Additions/generalizations for 32-bit | |
132 | - Changed to reflect the new arch/powerpc | |
133 | structure | |
134 | - Added chapter VI | |
135 | ||
136 | ||
137 | ToDo: | |
138 | - Add some definitions of interrupt tree (simple/complex) | |
5dd60166 | 139 | - Add some definitions for PCI host bridges |
c125a183 DG |
140 | - Add some common address format examples |
141 | - Add definitions for standard properties and "compatible" | |
142 | names for cells that are not already defined by the existing | |
143 | OF spec. | |
144 | - Compare FSL SOC use of PCI to standard and make sure no new | |
145 | node definition required. | |
146 | - Add more information about node definitions for SOC devices | |
147 | that currently have no standard, like the FSL CPM. | |
148 | ||
149 | ||
150 | I - Introduction | |
151 | ================ | |
152 | ||
153 | During the recent development of the Linux/ppc64 kernel, and more | |
154 | specifically, the addition of new platform types outside of the old | |
155 | IBM pSeries/iSeries pair, it was decided to enforce some strict rules | |
156 | regarding the kernel entry and bootloader <-> kernel interfaces, in | |
157 | order to avoid the degeneration that had become the ppc32 kernel entry | |
158 | point and the way a new platform should be added to the kernel. The | |
159 | legacy iSeries platform breaks those rules as it predates this scheme, | |
160 | but no new board support will be accepted in the main tree that | |
161 | doesn't follows them properly. In addition, since the advent of the | |
162 | arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit | |
163 | platforms and 32-bit platforms which move into arch/powerpc will be | |
164 | required to use these rules as well. | |
165 | ||
166 | The main requirement that will be defined in more detail below is | |
167 | the presence of a device-tree whose format is defined after Open | |
168 | Firmware specification. However, in order to make life easier | |
169 | to embedded board vendors, the kernel doesn't require the device-tree | |
170 | to represent every device in the system and only requires some nodes | |
171 | and properties to be present. This will be described in detail in | |
172 | section III, but, for example, the kernel does not require you to | |
173 | create a node for every PCI device in the system. It is a requirement | |
174 | to have a node for PCI host bridges in order to provide interrupt | |
175 | routing informations and memory/IO ranges, among others. It is also | |
176 | recommended to define nodes for on chip devices and other busses that | |
177 | don't specifically fit in an existing OF specification. This creates a | |
178 | great flexibility in the way the kernel can then probe those and match | |
179 | drivers to device, without having to hard code all sorts of tables. It | |
180 | also makes it more flexible for board vendors to do minor hardware | |
181 | upgrades without significantly impacting the kernel code or cluttering | |
182 | it with special cases. | |
183 | ||
184 | ||
185 | 1) Entry point for arch/powerpc | |
186 | ------------------------------- | |
187 | ||
188 | There is one and one single entry point to the kernel, at the start | |
189 | of the kernel image. That entry point supports two calling | |
190 | conventions: | |
191 | ||
192 | a) Boot from Open Firmware. If your firmware is compatible | |
193 | with Open Firmware (IEEE 1275) or provides an OF compatible | |
194 | client interface API (support for "interpret" callback of | |
195 | forth words isn't required), you can enter the kernel with: | |
196 | ||
197 | r5 : OF callback pointer as defined by IEEE 1275 | |
5dd60166 | 198 | bindings to powerpc. Only the 32-bit client interface |
c125a183 DG |
199 | is currently supported |
200 | ||
201 | r3, r4 : address & length of an initrd if any or 0 | |
202 | ||
203 | The MMU is either on or off; the kernel will run the | |
204 | trampoline located in arch/powerpc/kernel/prom_init.c to | |
205 | extract the device-tree and other information from open | |
206 | firmware and build a flattened device-tree as described | |
207 | in b). prom_init() will then re-enter the kernel using | |
208 | the second method. This trampoline code runs in the | |
209 | context of the firmware, which is supposed to handle all | |
210 | exceptions during that time. | |
211 | ||
212 | b) Direct entry with a flattened device-tree block. This entry | |
213 | point is called by a) after the OF trampoline and can also be | |
214 | called directly by a bootloader that does not support the Open | |
215 | Firmware client interface. It is also used by "kexec" to | |
216 | implement "hot" booting of a new kernel from a previous | |
217 | running one. This method is what I will describe in more | |
218 | details in this document, as method a) is simply standard Open | |
219 | Firmware, and thus should be implemented according to the | |
220 | various standard documents defining it and its binding to the | |
221 | PowerPC platform. The entry point definition then becomes: | |
222 | ||
223 | r3 : physical pointer to the device-tree block | |
224 | (defined in chapter II) in RAM | |
225 | ||
226 | r4 : physical pointer to the kernel itself. This is | |
227 | used by the assembly code to properly disable the MMU | |
228 | in case you are entering the kernel with MMU enabled | |
229 | and a non-1:1 mapping. | |
230 | ||
2fe0ae78 | 231 | r5 : NULL (as to differentiate with method a) |
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232 | |
233 | Note about SMP entry: Either your firmware puts your other | |
234 | CPUs in some sleep loop or spin loop in ROM where you can get | |
235 | them out via a soft reset or some other means, in which case | |
236 | you don't need to care, or you'll have to enter the kernel | |
237 | with all CPUs. The way to do that with method b) will be | |
238 | described in a later revision of this document. | |
239 | ||
240 | ||
241 | 2) Board support | |
242 | ---------------- | |
243 | ||
244 | 64-bit kernels: | |
245 | ||
246 | Board supports (platforms) are not exclusive config options. An | |
247 | arbitrary set of board supports can be built in a single kernel | |
248 | image. The kernel will "know" what set of functions to use for a | |
249 | given platform based on the content of the device-tree. Thus, you | |
250 | should: | |
251 | ||
252 | a) add your platform support as a _boolean_ option in | |
253 | arch/powerpc/Kconfig, following the example of PPC_PSERIES, | |
254 | PPC_PMAC and PPC_MAPLE. The later is probably a good | |
255 | example of a board support to start from. | |
256 | ||
257 | b) create your main platform file as | |
258 | "arch/powerpc/platforms/myplatform/myboard_setup.c" and add it | |
259 | to the Makefile under the condition of your CONFIG_ | |
260 | option. This file will define a structure of type "ppc_md" | |
261 | containing the various callbacks that the generic code will | |
262 | use to get to your platform specific code | |
263 | ||
264 | c) Add a reference to your "ppc_md" structure in the | |
265 | "machines" table in arch/powerpc/kernel/setup_64.c if you are | |
266 | a 64-bit platform. | |
267 | ||
268 | d) request and get assigned a platform number (see PLATFORM_* | |
b8b572e1 | 269 | constants in arch/powerpc/include/asm/processor.h |
c125a183 DG |
270 | |
271 | 32-bit embedded kernels: | |
272 | ||
273 | Currently, board support is essentially an exclusive config option. | |
274 | The kernel is configured for a single platform. Part of the reason | |
275 | for this is to keep kernels on embedded systems small and efficient; | |
276 | part of this is due to the fact the code is already that way. In the | |
277 | future, a kernel may support multiple platforms, but only if the | |
5dd60166 | 278 | platforms feature the same core architecture. A single kernel build |
c125a183 DG |
279 | cannot support both configurations with Book E and configurations |
280 | with classic Powerpc architectures. | |
281 | ||
282 | 32-bit embedded platforms that are moved into arch/powerpc using a | |
283 | flattened device tree should adopt the merged tree practice of | |
284 | setting ppc_md up dynamically, even though the kernel is currently | |
285 | built with support for only a single platform at a time. This allows | |
286 | unification of the setup code, and will make it easier to go to a | |
287 | multiple-platform-support model in the future. | |
288 | ||
289 | NOTE: I believe the above will be true once Ben's done with the merge | |
290 | of the boot sequences.... someone speak up if this is wrong! | |
291 | ||
292 | To add a 32-bit embedded platform support, follow the instructions | |
293 | for 64-bit platforms above, with the exception that the Kconfig | |
294 | option should be set up such that the kernel builds exclusively for | |
295 | the platform selected. The processor type for the platform should | |
296 | enable another config option to select the specific board | |
297 | supported. | |
298 | ||
5dd60166 | 299 | NOTE: If Ben doesn't merge the setup files, may need to change this to |
c125a183 DG |
300 | point to setup_32.c |
301 | ||
302 | ||
303 | I will describe later the boot process and various callbacks that | |
304 | your platform should implement. | |
305 | ||
306 | ||
307 | II - The DT block format | |
308 | ======================== | |
309 | ||
310 | ||
311 | This chapter defines the actual format of the flattened device-tree | |
312 | passed to the kernel. The actual content of it and kernel requirements | |
313 | are described later. You can find example of code manipulating that | |
314 | format in various places, including arch/powerpc/kernel/prom_init.c | |
315 | which will generate a flattened device-tree from the Open Firmware | |
316 | representation, or the fs2dt utility which is part of the kexec tools | |
317 | which will generate one from a filesystem representation. It is | |
318 | expected that a bootloader like uboot provides a bit more support, | |
319 | that will be discussed later as well. | |
320 | ||
321 | Note: The block has to be in main memory. It has to be accessible in | |
322 | both real mode and virtual mode with no mapping other than main | |
323 | memory. If you are writing a simple flash bootloader, it should copy | |
324 | the block to RAM before passing it to the kernel. | |
325 | ||
326 | ||
327 | 1) Header | |
328 | --------- | |
329 | ||
330 | The kernel is entered with r3 pointing to an area of memory that is | |
b8b572e1 | 331 | roughly described in arch/powerpc/include/asm/prom.h by the structure |
c125a183 DG |
332 | boot_param_header: |
333 | ||
334 | struct boot_param_header { | |
335 | u32 magic; /* magic word OF_DT_HEADER */ | |
336 | u32 totalsize; /* total size of DT block */ | |
337 | u32 off_dt_struct; /* offset to structure */ | |
338 | u32 off_dt_strings; /* offset to strings */ | |
339 | u32 off_mem_rsvmap; /* offset to memory reserve map | |
5dd60166 | 340 | */ |
c125a183 DG |
341 | u32 version; /* format version */ |
342 | u32 last_comp_version; /* last compatible version */ | |
343 | ||
344 | /* version 2 fields below */ | |
345 | u32 boot_cpuid_phys; /* Which physical CPU id we're | |
346 | booting on */ | |
347 | /* version 3 fields below */ | |
348 | u32 size_dt_strings; /* size of the strings block */ | |
0e0293c8 DG |
349 | |
350 | /* version 17 fields below */ | |
351 | u32 size_dt_struct; /* size of the DT structure block */ | |
c125a183 DG |
352 | }; |
353 | ||
354 | Along with the constants: | |
355 | ||
356 | /* Definitions used by the flattened device tree */ | |
357 | #define OF_DT_HEADER 0xd00dfeed /* 4: version, | |
358 | 4: total size */ | |
359 | #define OF_DT_BEGIN_NODE 0x1 /* Start node: full name | |
5dd60166 | 360 | */ |
c125a183 DG |
361 | #define OF_DT_END_NODE 0x2 /* End node */ |
362 | #define OF_DT_PROP 0x3 /* Property: name off, | |
363 | size, content */ | |
364 | #define OF_DT_END 0x9 | |
365 | ||
366 | All values in this header are in big endian format, the various | |
367 | fields in this header are defined more precisely below. All | |
368 | "offset" values are in bytes from the start of the header; that is | |
369 | from the value of r3. | |
370 | ||
371 | - magic | |
372 | ||
373 | This is a magic value that "marks" the beginning of the | |
374 | device-tree block header. It contains the value 0xd00dfeed and is | |
375 | defined by the constant OF_DT_HEADER | |
376 | ||
377 | - totalsize | |
378 | ||
379 | This is the total size of the DT block including the header. The | |
380 | "DT" block should enclose all data structures defined in this | |
381 | chapter (who are pointed to by offsets in this header). That is, | |
382 | the device-tree structure, strings, and the memory reserve map. | |
383 | ||
384 | - off_dt_struct | |
385 | ||
386 | This is an offset from the beginning of the header to the start | |
387 | of the "structure" part the device tree. (see 2) device tree) | |
388 | ||
389 | - off_dt_strings | |
390 | ||
391 | This is an offset from the beginning of the header to the start | |
392 | of the "strings" part of the device-tree | |
393 | ||
394 | - off_mem_rsvmap | |
395 | ||
396 | This is an offset from the beginning of the header to the start | |
5dd60166 | 397 | of the reserved memory map. This map is a list of pairs of 64- |
c125a183 | 398 | bit integers. Each pair is a physical address and a size. The |
c125a183 DG |
399 | list is terminated by an entry of size 0. This map provides the |
400 | kernel with a list of physical memory areas that are "reserved" | |
401 | and thus not to be used for memory allocations, especially during | |
402 | early initialization. The kernel needs to allocate memory during | |
403 | boot for things like un-flattening the device-tree, allocating an | |
404 | MMU hash table, etc... Those allocations must be done in such a | |
405 | way to avoid overriding critical things like, on Open Firmware | |
406 | capable machines, the RTAS instance, or on some pSeries, the TCE | |
407 | tables used for the iommu. Typically, the reserve map should | |
408 | contain _at least_ this DT block itself (header,total_size). If | |
409 | you are passing an initrd to the kernel, you should reserve it as | |
410 | well. You do not need to reserve the kernel image itself. The map | |
5dd60166 | 411 | should be 64-bit aligned. |
c125a183 DG |
412 | |
413 | - version | |
414 | ||
415 | This is the version of this structure. Version 1 stops | |
416 | here. Version 2 adds an additional field boot_cpuid_phys. | |
417 | Version 3 adds the size of the strings block, allowing the kernel | |
418 | to reallocate it easily at boot and free up the unused flattened | |
419 | structure after expansion. Version 16 introduces a new more | |
420 | "compact" format for the tree itself that is however not backward | |
0e0293c8 DG |
421 | compatible. Version 17 adds an additional field, size_dt_struct, |
422 | allowing it to be reallocated or moved more easily (this is | |
423 | particularly useful for bootloaders which need to make | |
424 | adjustments to a device tree based on probed information). You | |
425 | should always generate a structure of the highest version defined | |
426 | at the time of your implementation. Currently that is version 17, | |
427 | unless you explicitly aim at being backward compatible. | |
c125a183 DG |
428 | |
429 | - last_comp_version | |
430 | ||
431 | Last compatible version. This indicates down to what version of | |
432 | the DT block you are backward compatible. For example, version 2 | |
433 | is backward compatible with version 1 (that is, a kernel build | |
434 | for version 1 will be able to boot with a version 2 format). You | |
435 | should put a 1 in this field if you generate a device tree of | |
0e0293c8 | 436 | version 1 to 3, or 16 if you generate a tree of version 16 or 17 |
c125a183 DG |
437 | using the new unit name format. |
438 | ||
439 | - boot_cpuid_phys | |
440 | ||
441 | This field only exist on version 2 headers. It indicate which | |
442 | physical CPU ID is calling the kernel entry point. This is used, | |
443 | among others, by kexec. If you are on an SMP system, this value | |
444 | should match the content of the "reg" property of the CPU node in | |
445 | the device-tree corresponding to the CPU calling the kernel entry | |
446 | point (see further chapters for more informations on the required | |
447 | device-tree contents) | |
448 | ||
0e0293c8 DG |
449 | - size_dt_strings |
450 | ||
451 | This field only exists on version 3 and later headers. It | |
452 | gives the size of the "strings" section of the device tree (which | |
453 | starts at the offset given by off_dt_strings). | |
454 | ||
455 | - size_dt_struct | |
456 | ||
457 | This field only exists on version 17 and later headers. It gives | |
458 | the size of the "structure" section of the device tree (which | |
459 | starts at the offset given by off_dt_struct). | |
c125a183 DG |
460 | |
461 | So the typical layout of a DT block (though the various parts don't | |
462 | need to be in that order) looks like this (addresses go from top to | |
463 | bottom): | |
464 | ||
465 | ||
466 | ------------------------------ | |
467 | r3 -> | struct boot_param_header | | |
468 | ------------------------------ | |
469 | | (alignment gap) (*) | | |
470 | ------------------------------ | |
471 | | memory reserve map | | |
472 | ------------------------------ | |
473 | | (alignment gap) | | |
474 | ------------------------------ | |
475 | | | | |
476 | | device-tree structure | | |
477 | | | | |
478 | ------------------------------ | |
479 | | (alignment gap) | | |
480 | ------------------------------ | |
481 | | | | |
482 | | device-tree strings | | |
483 | | | | |
484 | -----> ------------------------------ | |
485 | | | |
486 | | | |
487 | --- (r3 + totalsize) | |
488 | ||
489 | (*) The alignment gaps are not necessarily present; their presence | |
490 | and size are dependent on the various alignment requirements of | |
491 | the individual data blocks. | |
492 | ||
493 | ||
494 | 2) Device tree generalities | |
495 | --------------------------- | |
496 | ||
497 | This device-tree itself is separated in two different blocks, a | |
498 | structure block and a strings block. Both need to be aligned to a 4 | |
499 | byte boundary. | |
500 | ||
501 | First, let's quickly describe the device-tree concept before detailing | |
502 | the storage format. This chapter does _not_ describe the detail of the | |
503 | required types of nodes & properties for the kernel, this is done | |
504 | later in chapter III. | |
505 | ||
506 | The device-tree layout is strongly inherited from the definition of | |
507 | the Open Firmware IEEE 1275 device-tree. It's basically a tree of | |
508 | nodes, each node having two or more named properties. A property can | |
509 | have a value or not. | |
510 | ||
511 | It is a tree, so each node has one and only one parent except for the | |
512 | root node who has no parent. | |
513 | ||
514 | A node has 2 names. The actual node name is generally contained in a | |
515 | property of type "name" in the node property list whose value is a | |
516 | zero terminated string and is mandatory for version 1 to 3 of the | |
0e0293c8 | 517 | format definition (as it is in Open Firmware). Version 16 makes it |
c125a183 DG |
518 | optional as it can generate it from the unit name defined below. |
519 | ||
2fe0ae78 | 520 | There is also a "unit name" that is used to differentiate nodes with |
c125a183 | 521 | the same name at the same level, it is usually made of the node |
2fe0ae78 | 522 | names, the "@" sign, and a "unit address", which definition is |
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523 | specific to the bus type the node sits on. |
524 | ||
525 | The unit name doesn't exist as a property per-se but is included in | |
526 | the device-tree structure. It is typically used to represent "path" in | |
527 | the device-tree. More details about the actual format of these will be | |
528 | below. | |
529 | ||
530 | The kernel powerpc generic code does not make any formal use of the | |
531 | unit address (though some board support code may do) so the only real | |
532 | requirement here for the unit address is to ensure uniqueness of | |
533 | the node unit name at a given level of the tree. Nodes with no notion | |
534 | of address and no possible sibling of the same name (like /memory or | |
535 | /cpus) may omit the unit address in the context of this specification, | |
536 | or use the "@0" default unit address. The unit name is used to define | |
537 | a node "full path", which is the concatenation of all parent node | |
538 | unit names separated with "/". | |
539 | ||
540 | The root node doesn't have a defined name, and isn't required to have | |
541 | a name property either if you are using version 3 or earlier of the | |
542 | format. It also has no unit address (no @ symbol followed by a unit | |
543 | address). The root node unit name is thus an empty string. The full | |
544 | path to the root node is "/". | |
545 | ||
546 | Every node which actually represents an actual device (that is, a node | |
547 | which isn't only a virtual "container" for more nodes, like "/cpus" | |
548 | is) is also required to have a "device_type" property indicating the | |
549 | type of node . | |
550 | ||
551 | Finally, every node that can be referenced from a property in another | |
552 | node is required to have a "linux,phandle" property. Real open | |
553 | firmware implementations provide a unique "phandle" value for every | |
554 | node that the "prom_init()" trampoline code turns into | |
555 | "linux,phandle" properties. However, this is made optional if the | |
556 | flattened device tree is used directly. An example of a node | |
557 | referencing another node via "phandle" is when laying out the | |
558 | interrupt tree which will be described in a further version of this | |
559 | document. | |
560 | ||
5dd60166 | 561 | This "linux, phandle" property is a 32-bit value that uniquely |
c125a183 DG |
562 | identifies a node. You are free to use whatever values or system of |
563 | values, internal pointers, or whatever to generate these, the only | |
564 | requirement is that every node for which you provide that property has | |
565 | a unique value for it. | |
566 | ||
567 | Here is an example of a simple device-tree. In this example, an "o" | |
568 | designates a node followed by the node unit name. Properties are | |
569 | presented with their name followed by their content. "content" | |
570 | represents an ASCII string (zero terminated) value, while <content> | |
5dd60166 | 571 | represents a 32-bit hexadecimal value. The various nodes in this |
c125a183 DG |
572 | example will be discussed in a later chapter. At this point, it is |
573 | only meant to give you a idea of what a device-tree looks like. I have | |
574 | purposefully kept the "name" and "linux,phandle" properties which | |
575 | aren't necessary in order to give you a better idea of what the tree | |
576 | looks like in practice. | |
577 | ||
578 | / o device-tree | |
579 | |- name = "device-tree" | |
580 | |- model = "MyBoardName" | |
581 | |- compatible = "MyBoardFamilyName" | |
582 | |- #address-cells = <2> | |
583 | |- #size-cells = <2> | |
584 | |- linux,phandle = <0> | |
585 | | | |
586 | o cpus | |
587 | | | - name = "cpus" | |
588 | | | - linux,phandle = <1> | |
589 | | | - #address-cells = <1> | |
590 | | | - #size-cells = <0> | |
591 | | | | |
592 | | o PowerPC,970@0 | |
593 | | |- name = "PowerPC,970" | |
594 | | |- device_type = "cpu" | |
595 | | |- reg = <0> | |
596 | | |- clock-frequency = <5f5e1000> | |
32aed2a5 | 597 | | |- 64-bit |
c125a183 DG |
598 | | |- linux,phandle = <2> |
599 | | | |
600 | o memory@0 | |
601 | | |- name = "memory" | |
602 | | |- device_type = "memory" | |
603 | | |- reg = <00000000 00000000 00000000 20000000> | |
604 | | |- linux,phandle = <3> | |
605 | | | |
606 | o chosen | |
607 | |- name = "chosen" | |
608 | |- bootargs = "root=/dev/sda2" | |
c125a183 DG |
609 | |- linux,phandle = <4> |
610 | ||
611 | This tree is almost a minimal tree. It pretty much contains the | |
612 | minimal set of required nodes and properties to boot a linux kernel; | |
613 | that is, some basic model informations at the root, the CPUs, and the | |
614 | physical memory layout. It also includes misc information passed | |
615 | through /chosen, like in this example, the platform type (mandatory) | |
616 | and the kernel command line arguments (optional). | |
617 | ||
32aed2a5 | 618 | The /cpus/PowerPC,970@0/64-bit property is an example of a |
c125a183 DG |
619 | property without a value. All other properties have a value. The |
620 | significance of the #address-cells and #size-cells properties will be | |
621 | explained in chapter IV which defines precisely the required nodes and | |
622 | properties and their content. | |
623 | ||
624 | ||
625 | 3) Device tree "structure" block | |
626 | ||
627 | The structure of the device tree is a linearized tree structure. The | |
628 | "OF_DT_BEGIN_NODE" token starts a new node, and the "OF_DT_END_NODE" | |
629 | ends that node definition. Child nodes are simply defined before | |
630 | "OF_DT_END_NODE" (that is nodes within the node). A 'token' is a 32 | |
631 | bit value. The tree has to be "finished" with a OF_DT_END token | |
632 | ||
633 | Here's the basic structure of a single node: | |
634 | ||
635 | * token OF_DT_BEGIN_NODE (that is 0x00000001) | |
636 | * for version 1 to 3, this is the node full path as a zero | |
637 | terminated string, starting with "/". For version 16 and later, | |
638 | this is the node unit name only (or an empty string for the | |
639 | root node) | |
640 | * [align gap to next 4 bytes boundary] | |
641 | * for each property: | |
642 | * token OF_DT_PROP (that is 0x00000003) | |
5dd60166 DP |
643 | * 32-bit value of property value size in bytes (or 0 if no |
644 | value) | |
645 | * 32-bit value of offset in string block of property name | |
c125a183 DG |
646 | * property value data if any |
647 | * [align gap to next 4 bytes boundary] | |
648 | * [child nodes if any] | |
649 | * token OF_DT_END_NODE (that is 0x00000002) | |
650 | ||
5dd60166 | 651 | So the node content can be summarized as a start token, a full path, |
53cb4726 | 652 | a list of properties, a list of child nodes, and an end token. Every |
c125a183 DG |
653 | child node is a full node structure itself as defined above. |
654 | ||
eff2ebd2 DG |
655 | NOTE: The above definition requires that all property definitions for |
656 | a particular node MUST precede any subnode definitions for that node. | |
657 | Although the structure would not be ambiguous if properties and | |
658 | subnodes were intermingled, the kernel parser requires that the | |
659 | properties come first (up until at least 2.6.22). Any tools | |
660 | manipulating a flattened tree must take care to preserve this | |
661 | constraint. | |
662 | ||
53cb4726 | 663 | 4) Device tree "strings" block |
c125a183 DG |
664 | |
665 | In order to save space, property names, which are generally redundant, | |
666 | are stored separately in the "strings" block. This block is simply the | |
667 | whole bunch of zero terminated strings for all property names | |
668 | concatenated together. The device-tree property definitions in the | |
669 | structure block will contain offset values from the beginning of the | |
670 | strings block. | |
671 | ||
672 | ||
673 | III - Required content of the device tree | |
674 | ========================================= | |
675 | ||
676 | WARNING: All "linux,*" properties defined in this document apply only | |
677 | to a flattened device-tree. If your platform uses a real | |
678 | implementation of Open Firmware or an implementation compatible with | |
679 | the Open Firmware client interface, those properties will be created | |
680 | by the trampoline code in the kernel's prom_init() file. For example, | |
681 | that's where you'll have to add code to detect your board model and | |
a2ffd275 | 682 | set the platform number. However, when using the flattened device-tree |
c125a183 DG |
683 | entry point, there is no prom_init() pass, and thus you have to |
684 | provide those properties yourself. | |
685 | ||
686 | ||
687 | 1) Note about cells and address representation | |
688 | ---------------------------------------------- | |
689 | ||
690 | The general rule is documented in the various Open Firmware | |
5dd60166 | 691 | documentations. If you choose to describe a bus with the device-tree |
c125a183 DG |
692 | and there exist an OF bus binding, then you should follow the |
693 | specification. However, the kernel does not require every single | |
694 | device or bus to be described by the device tree. | |
695 | ||
696 | In general, the format of an address for a device is defined by the | |
697 | parent bus type, based on the #address-cells and #size-cells | |
5b14e5f9 | 698 | properties. Note that the parent's parent definitions of #address-cells |
d9195881 | 699 | and #size-cells are not inherited so every node with children must specify |
5b14e5f9 MG |
700 | them. The kernel requires the root node to have those properties defining |
701 | addresses format for devices directly mapped on the processor bus. | |
c125a183 DG |
702 | |
703 | Those 2 properties define 'cells' for representing an address and a | |
5dd60166 | 704 | size. A "cell" is a 32-bit number. For example, if both contain 2 |
c125a183 | 705 | like the example tree given above, then an address and a size are both |
5dd60166 | 706 | composed of 2 cells, and each is a 64-bit number (cells are |
c125a183 DG |
707 | concatenated and expected to be in big endian format). Another example |
708 | is the way Apple firmware defines them, with 2 cells for an address | |
709 | and one cell for a size. Most 32-bit implementations should define | |
710 | #address-cells and #size-cells to 1, which represents a 32-bit value. | |
711 | Some 32-bit processors allow for physical addresses greater than 32 | |
712 | bits; these processors should define #address-cells as 2. | |
713 | ||
714 | "reg" properties are always a tuple of the type "address size" where | |
715 | the number of cells of address and size is specified by the bus | |
716 | #address-cells and #size-cells. When a bus supports various address | |
717 | spaces and other flags relative to a given address allocation (like | |
718 | prefetchable, etc...) those flags are usually added to the top level | |
719 | bits of the physical address. For example, a PCI physical address is | |
720 | made of 3 cells, the bottom two containing the actual address itself | |
721 | while the top cell contains address space indication, flags, and pci | |
722 | bus & device numbers. | |
723 | ||
724 | For busses that support dynamic allocation, it's the accepted practice | |
725 | to then not provide the address in "reg" (keep it 0) though while | |
726 | providing a flag indicating the address is dynamically allocated, and | |
727 | then, to provide a separate "assigned-addresses" property that | |
728 | contains the fully allocated addresses. See the PCI OF bindings for | |
729 | details. | |
730 | ||
731 | In general, a simple bus with no address space bits and no dynamic | |
732 | allocation is preferred if it reflects your hardware, as the existing | |
733 | kernel address parsing functions will work out of the box. If you | |
734 | define a bus type with a more complex address format, including things | |
735 | like address space bits, you'll have to add a bus translator to the | |
736 | prom_parse.c file of the recent kernels for your bus type. | |
737 | ||
e1fd1865 SN |
738 | The "reg" property only defines addresses and sizes (if #size-cells is |
739 | non-0) within a given bus. In order to translate addresses upward | |
5dd60166 | 740 | (that is into parent bus addresses, and possibly into CPU physical |
c125a183 DG |
741 | addresses), all busses must contain a "ranges" property. If the |
742 | "ranges" property is missing at a given level, it's assumed that | |
e1fd1865 SN |
743 | translation isn't possible, i.e., the registers are not visible on the |
744 | parent bus. The format of the "ranges" property for a bus is a list | |
745 | of: | |
c125a183 DG |
746 | |
747 | bus address, parent bus address, size | |
748 | ||
749 | "bus address" is in the format of the bus this bus node is defining, | |
750 | that is, for a PCI bridge, it would be a PCI address. Thus, (bus | |
751 | address, size) defines a range of addresses for child devices. "parent | |
752 | bus address" is in the format of the parent bus of this bus. For | |
753 | example, for a PCI host controller, that would be a CPU address. For a | |
754 | PCI<->ISA bridge, that would be a PCI address. It defines the base | |
755 | address in the parent bus where the beginning of that range is mapped. | |
756 | ||
5dd60166 | 757 | For a new 64-bit powerpc board, I recommend either the 2/2 format or |
c125a183 | 758 | Apple's 2/1 format which is slightly more compact since sizes usually |
5dd60166 | 759 | fit in a single 32-bit word. New 32-bit powerpc boards should use a |
c125a183 DG |
760 | 1/1 format, unless the processor supports physical addresses greater |
761 | than 32-bits, in which case a 2/1 format is recommended. | |
762 | ||
e1fd1865 SN |
763 | Alternatively, the "ranges" property may be empty, indicating that the |
764 | registers are visible on the parent bus using an identity mapping | |
765 | translation. In other words, the parent bus address space is the same | |
766 | as the child bus address space. | |
c125a183 DG |
767 | |
768 | 2) Note about "compatible" properties | |
769 | ------------------------------------- | |
770 | ||
771 | These properties are optional, but recommended in devices and the root | |
772 | node. The format of a "compatible" property is a list of concatenated | |
773 | zero terminated strings. They allow a device to express its | |
774 | compatibility with a family of similar devices, in some cases, | |
775 | allowing a single driver to match against several devices regardless | |
776 | of their actual names. | |
777 | ||
778 | 3) Note about "name" properties | |
779 | ------------------------------- | |
780 | ||
781 | While earlier users of Open Firmware like OldWorld macintoshes tended | |
782 | to use the actual device name for the "name" property, it's nowadays | |
783 | considered a good practice to use a name that is closer to the device | |
784 | class (often equal to device_type). For example, nowadays, ethernet | |
785 | controllers are named "ethernet", an additional "model" property | |
786 | defining precisely the chip type/model, and "compatible" property | |
787 | defining the family in case a single driver can driver more than one | |
788 | of these chips. However, the kernel doesn't generally put any | |
789 | restriction on the "name" property; it is simply considered good | |
790 | practice to follow the standard and its evolutions as closely as | |
791 | possible. | |
792 | ||
793 | Note also that the new format version 16 makes the "name" property | |
794 | optional. If it's absent for a node, then the node's unit name is then | |
795 | used to reconstruct the name. That is, the part of the unit name | |
796 | before the "@" sign is used (or the entire unit name if no "@" sign | |
797 | is present). | |
798 | ||
799 | 4) Note about node and property names and character set | |
800 | ------------------------------------------------------- | |
801 | ||
a2ffd275 | 802 | While open firmware provides more flexible usage of 8859-1, this |
c125a183 DG |
803 | specification enforces more strict rules. Nodes and properties should |
804 | be comprised only of ASCII characters 'a' to 'z', '0' to | |
805 | '9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally | |
806 | allow uppercase characters 'A' to 'Z' (property names should be | |
807 | lowercase. The fact that vendors like Apple don't respect this rule is | |
808 | irrelevant here). Additionally, node and property names should always | |
809 | begin with a character in the range 'a' to 'z' (or 'A' to 'Z' for node | |
810 | names). | |
811 | ||
812 | The maximum number of characters for both nodes and property names | |
813 | is 31. In the case of node names, this is only the leftmost part of | |
814 | a unit name (the pure "name" property), it doesn't include the unit | |
815 | address which can extend beyond that limit. | |
816 | ||
817 | ||
818 | 5) Required nodes and properties | |
819 | -------------------------------- | |
820 | These are all that are currently required. However, it is strongly | |
821 | recommended that you expose PCI host bridges as documented in the | |
822 | PCI binding to open firmware, and your interrupt tree as documented | |
823 | in OF interrupt tree specification. | |
824 | ||
825 | a) The root node | |
826 | ||
827 | The root node requires some properties to be present: | |
828 | ||
829 | - model : this is your board name/model | |
830 | - #address-cells : address representation for "root" devices | |
831 | - #size-cells: the size representation for "root" devices | |
e8222502 BH |
832 | - device_type : This property shouldn't be necessary. However, if |
833 | you decide to create a device_type for your root node, make sure it | |
834 | is _not_ "chrp" unless your platform is a pSeries or PAPR compliant | |
835 | one for 64-bit, or a CHRP-type machine for 32-bit as this will | |
836 | matched by the kernel this way. | |
c125a183 DG |
837 | |
838 | Additionally, some recommended properties are: | |
839 | ||
840 | - compatible : the board "family" generally finds its way here, | |
841 | for example, if you have 2 board models with a similar layout, | |
842 | that typically get driven by the same platform code in the | |
843 | kernel, you would use a different "model" property but put a | |
844 | value in "compatible". The kernel doesn't directly use that | |
143a42d1 | 845 | value but it is generally useful. |
c125a183 DG |
846 | |
847 | The root node is also generally where you add additional properties | |
848 | specific to your board like the serial number if any, that sort of | |
6c28f2c0 | 849 | thing. It is recommended that if you add any "custom" property whose |
c125a183 DG |
850 | name may clash with standard defined ones, you prefix them with your |
851 | vendor name and a comma. | |
852 | ||
853 | b) The /cpus node | |
854 | ||
855 | This node is the parent of all individual CPU nodes. It doesn't | |
856 | have any specific requirements, though it's generally good practice | |
857 | to have at least: | |
858 | ||
859 | #address-cells = <00000001> | |
860 | #size-cells = <00000000> | |
861 | ||
862 | This defines that the "address" for a CPU is a single cell, and has | |
863 | no meaningful size. This is not necessary but the kernel will assume | |
864 | that format when reading the "reg" properties of a CPU node, see | |
865 | below | |
866 | ||
867 | c) The /cpus/* nodes | |
868 | ||
869 | So under /cpus, you are supposed to create a node for every CPU on | |
870 | the machine. There is no specific restriction on the name of the | |
871 | CPU, though It's common practice to call it PowerPC,<name>. For | |
872 | example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX. | |
873 | ||
874 | Required properties: | |
875 | ||
876 | - device_type : has to be "cpu" | |
5dd60166 | 877 | - reg : This is the physical CPU number, it's a single 32-bit cell |
c125a183 DG |
878 | and is also used as-is as the unit number for constructing the |
879 | unit name in the full path. For example, with 2 CPUs, you would | |
880 | have the full path: | |
881 | /cpus/PowerPC,970FX@0 | |
882 | /cpus/PowerPC,970FX@1 | |
883 | (unit addresses do not require leading zeroes) | |
20474abd BH |
884 | - d-cache-block-size : one cell, L1 data cache block size in bytes (*) |
885 | - i-cache-block-size : one cell, L1 instruction cache block size in | |
c125a183 DG |
886 | bytes |
887 | - d-cache-size : one cell, size of L1 data cache in bytes | |
888 | - i-cache-size : one cell, size of L1 instruction cache in bytes | |
c125a183 | 889 | |
20474abd BH |
890 | (*) The cache "block" size is the size on which the cache management |
891 | instructions operate. Historically, this document used the cache | |
892 | "line" size here which is incorrect. The kernel will prefer the cache | |
893 | block size and will fallback to cache line size for backward | |
894 | compatibility. | |
895 | ||
c125a183 DG |
896 | Recommended properties: |
897 | ||
898 | - timebase-frequency : a cell indicating the frequency of the | |
899 | timebase in Hz. This is not directly used by the generic code, | |
900 | but you are welcome to copy/paste the pSeries code for setting | |
901 | the kernel timebase/decrementer calibration based on this | |
902 | value. | |
903 | - clock-frequency : a cell indicating the CPU core clock frequency | |
5dd60166 | 904 | in Hz. A new property will be defined for 64-bit values, but if |
c125a183 DG |
905 | your frequency is < 4Ghz, one cell is enough. Here as well as |
906 | for the above, the common code doesn't use that property, but | |
907 | you are welcome to re-use the pSeries or Maple one. A future | |
908 | kernel version might provide a common function for this. | |
20474abd BH |
909 | - d-cache-line-size : one cell, L1 data cache line size in bytes |
910 | if different from the block size | |
911 | - i-cache-line-size : one cell, L1 instruction cache line size in | |
912 | bytes if different from the block size | |
c125a183 DG |
913 | |
914 | You are welcome to add any property you find relevant to your board, | |
915 | like some information about the mechanism used to soft-reset the | |
916 | CPUs. For example, Apple puts the GPIO number for CPU soft reset | |
917 | lines in there as a "soft-reset" property since they start secondary | |
918 | CPUs by soft-resetting them. | |
919 | ||
920 | ||
921 | d) the /memory node(s) | |
922 | ||
923 | To define the physical memory layout of your board, you should | |
924 | create one or more memory node(s). You can either create a single | |
925 | node with all memory ranges in its reg property, or you can create | |
926 | several nodes, as you wish. The unit address (@ part) used for the | |
927 | full path is the address of the first range of memory defined by a | |
928 | given node. If you use a single memory node, this will typically be | |
929 | @0. | |
930 | ||
931 | Required properties: | |
932 | ||
933 | - device_type : has to be "memory" | |
934 | - reg : This property contains all the physical memory ranges of | |
935 | your board. It's a list of addresses/sizes concatenated | |
936 | together, with the number of cells of each defined by the | |
937 | #address-cells and #size-cells of the root node. For example, | |
6c28f2c0 | 938 | with both of these properties being 2 like in the example given |
c125a183 DG |
939 | earlier, a 970 based machine with 6Gb of RAM could typically |
940 | have a "reg" property here that looks like: | |
941 | ||
942 | 00000000 00000000 00000000 80000000 | |
943 | 00000001 00000000 00000001 00000000 | |
944 | ||
945 | That is a range starting at 0 of 0x80000000 bytes and a range | |
946 | starting at 0x100000000 and of 0x100000000 bytes. You can see | |
947 | that there is no memory covering the IO hole between 2Gb and | |
948 | 4Gb. Some vendors prefer splitting those ranges into smaller | |
949 | segments, but the kernel doesn't care. | |
950 | ||
951 | e) The /chosen node | |
952 | ||
953 | This node is a bit "special". Normally, that's where open firmware | |
954 | puts some variable environment information, like the arguments, or | |
d1bff9ed | 955 | the default input/output devices. |
c125a183 DG |
956 | |
957 | This specification makes a few of these mandatory, but also defines | |
958 | some linux-specific properties that would be normally constructed by | |
959 | the prom_init() trampoline when booting with an OF client interface, | |
960 | but that you have to provide yourself when using the flattened format. | |
961 | ||
c125a183 DG |
962 | Recommended properties: |
963 | ||
964 | - bootargs : This zero-terminated string is passed as the kernel | |
965 | command line | |
966 | - linux,stdout-path : This is the full path to your standard | |
967 | console device if any. Typically, if you have serial devices on | |
968 | your board, you may want to put the full path to the one set as | |
969 | the default console in the firmware here, for the kernel to pick | |
5d3f083d | 970 | it up as its own default console. If you look at the function |
c125a183 DG |
971 | set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see |
972 | that the kernel tries to find out the default console and has | |
973 | knowledge of various types like 8250 serial ports. You may want | |
974 | to extend this function to add your own. | |
c125a183 DG |
975 | |
976 | Note that u-boot creates and fills in the chosen node for platforms | |
977 | that use it. | |
978 | ||
d1bff9ed SY |
979 | (Note: a practice that is now obsolete was to include a property |
980 | under /chosen called interrupt-controller which had a phandle value | |
981 | that pointed to the main interrupt controller) | |
982 | ||
c125a183 DG |
983 | f) the /soc<SOCname> node |
984 | ||
985 | This node is used to represent a system-on-a-chip (SOC) and must be | |
986 | present if the processor is a SOC. The top-level soc node contains | |
987 | information that is global to all devices on the SOC. The node name | |
988 | should contain a unit address for the SOC, which is the base address | |
989 | of the memory-mapped register set for the SOC. The name of an soc | |
990 | node should start with "soc", and the remainder of the name should | |
991 | represent the part number for the soc. For example, the MPC8540's | |
992 | soc node would be called "soc8540". | |
993 | ||
994 | Required properties: | |
995 | ||
996 | - device_type : Should be "soc" | |
997 | - ranges : Should be defined as specified in 1) to describe the | |
998 | translation of SOC addresses for memory mapped SOC registers. | |
7d4b95ae BB |
999 | - bus-frequency: Contains the bus frequency for the SOC node. |
1000 | Typically, the value of this field is filled in by the boot | |
efcc2da3 | 1001 | loader. |
7d4b95ae | 1002 | |
c125a183 DG |
1003 | |
1004 | Recommended properties: | |
1005 | ||
1006 | - reg : This property defines the address and size of the | |
1007 | memory-mapped registers that are used for the SOC node itself. | |
1008 | It does not include the child device registers - these will be | |
1009 | defined inside each child node. The address specified in the | |
1010 | "reg" property should match the unit address of the SOC node. | |
1011 | - #address-cells : Address representation for "soc" devices. The | |
1012 | format of this field may vary depending on whether or not the | |
1013 | device registers are memory mapped. For memory mapped | |
1014 | registers, this field represents the number of cells needed to | |
1015 | represent the address of the registers. For SOCs that do not | |
1016 | use MMIO, a special address format should be defined that | |
1017 | contains enough cells to represent the required information. | |
1018 | See 1) above for more details on defining #address-cells. | |
1019 | - #size-cells : Size representation for "soc" devices | |
1020 | - #interrupt-cells : Defines the width of cells used to represent | |
1021 | interrupts. Typically this value is <2>, which includes a | |
1022 | 32-bit number that represents the interrupt number, and a | |
1023 | 32-bit number that represents the interrupt sense and level. | |
1024 | This field is only needed if the SOC contains an interrupt | |
1025 | controller. | |
1026 | ||
1027 | The SOC node may contain child nodes for each SOC device that the | |
1028 | platform uses. Nodes should not be created for devices which exist | |
1029 | on the SOC but are not used by a particular platform. See chapter VI | |
5dd60166 | 1030 | for more information on how to specify devices that are part of a SOC. |
c125a183 DG |
1031 | |
1032 | Example SOC node for the MPC8540: | |
1033 | ||
1034 | soc8540@e0000000 { | |
1035 | #address-cells = <1>; | |
1036 | #size-cells = <1>; | |
1037 | #interrupt-cells = <2>; | |
1038 | device_type = "soc"; | |
1039 | ranges = <00000000 e0000000 00100000> | |
1040 | reg = <e0000000 00003000>; | |
7d4b95ae | 1041 | bus-frequency = <0>; |
c125a183 DG |
1042 | } |
1043 | ||
1044 | ||
1045 | ||
1046 | IV - "dtc", the device tree compiler | |
1047 | ==================================== | |
1048 | ||
1049 | ||
1050 | dtc source code can be found at | |
1051 | <http://ozlabs.org/~dgibson/dtc/dtc.tar.gz> | |
1052 | ||
1053 | WARNING: This version is still in early development stage; the | |
1054 | resulting device-tree "blobs" have not yet been validated with the | |
1055 | kernel. The current generated bloc lacks a useful reserve map (it will | |
1056 | be fixed to generate an empty one, it's up to the bootloader to fill | |
1057 | it up) among others. The error handling needs work, bugs are lurking, | |
1058 | etc... | |
1059 | ||
1060 | dtc basically takes a device-tree in a given format and outputs a | |
1061 | device-tree in another format. The currently supported formats are: | |
1062 | ||
1063 | Input formats: | |
1064 | ------------- | |
1065 | ||
1066 | - "dtb": "blob" format, that is a flattened device-tree block | |
1067 | with | |
1068 | header all in a binary blob. | |
1069 | - "dts": "source" format. This is a text file containing a | |
1070 | "source" for a device-tree. The format is defined later in this | |
1071 | chapter. | |
1072 | - "fs" format. This is a representation equivalent to the | |
1073 | output of /proc/device-tree, that is nodes are directories and | |
1074 | properties are files | |
1075 | ||
1076 | Output formats: | |
1077 | --------------- | |
1078 | ||
1079 | - "dtb": "blob" format | |
1080 | - "dts": "source" format | |
1081 | - "asm": assembly language file. This is a file that can be | |
1082 | sourced by gas to generate a device-tree "blob". That file can | |
1083 | then simply be added to your Makefile. Additionally, the | |
6c28f2c0 | 1084 | assembly file exports some symbols that can be used. |
c125a183 DG |
1085 | |
1086 | ||
1087 | The syntax of the dtc tool is | |
1088 | ||
1089 | dtc [-I <input-format>] [-O <output-format>] | |
1090 | [-o output-filename] [-V output_version] input_filename | |
1091 | ||
1092 | ||
5dd60166 | 1093 | The "output_version" defines what version of the "blob" format will be |
c125a183 DG |
1094 | generated. Supported versions are 1,2,3 and 16. The default is |
1095 | currently version 3 but that may change in the future to version 16. | |
1096 | ||
1097 | Additionally, dtc performs various sanity checks on the tree, like the | |
6c28f2c0 | 1098 | uniqueness of linux, phandle properties, validity of strings, etc... |
c125a183 DG |
1099 | |
1100 | The format of the .dts "source" file is "C" like, supports C and C++ | |
6c28f2c0 | 1101 | style comments. |
c125a183 DG |
1102 | |
1103 | / { | |
1104 | } | |
1105 | ||
1106 | The above is the "device-tree" definition. It's the only statement | |
1107 | supported currently at the toplevel. | |
1108 | ||
1109 | / { | |
1110 | property1 = "string_value"; /* define a property containing a 0 | |
1111 | * terminated string | |
1112 | */ | |
1113 | ||
1114 | property2 = <1234abcd>; /* define a property containing a | |
5dd60166 | 1115 | * numerical 32-bit value (hexadecimal) |
c125a183 DG |
1116 | */ |
1117 | ||
1118 | property3 = <12345678 12345678 deadbeef>; | |
1119 | /* define a property containing 3 | |
5dd60166 | 1120 | * numerical 32-bit values (cells) in |
c125a183 DG |
1121 | * hexadecimal |
1122 | */ | |
1123 | property4 = [0a 0b 0c 0d de ea ad be ef]; | |
1124 | /* define a property whose content is | |
1125 | * an arbitrary array of bytes | |
1126 | */ | |
1127 | ||
1128 | childnode@addresss { /* define a child node named "childnode" | |
1129 | * whose unit name is "childnode at | |
1130 | * address" | |
1131 | */ | |
1132 | ||
1133 | childprop = "hello\n"; /* define a property "childprop" of | |
1134 | * childnode (in this case, a string) | |
1135 | */ | |
1136 | }; | |
1137 | }; | |
1138 | ||
1139 | Nodes can contain other nodes etc... thus defining the hierarchical | |
1140 | structure of the tree. | |
1141 | ||
1142 | Strings support common escape sequences from C: "\n", "\t", "\r", | |
1143 | "\(octal value)", "\x(hex value)". | |
1144 | ||
1145 | It is also suggested that you pipe your source file through cpp (gcc | |
1146 | preprocessor) so you can use #include's, #define for constants, etc... | |
1147 | ||
1148 | Finally, various options are planned but not yet implemented, like | |
1149 | automatic generation of phandles, labels (exported to the asm file so | |
1150 | you can point to a property content and change it easily from whatever | |
1151 | you link the device-tree with), label or path instead of numeric value | |
1152 | in some cells to "point" to a node (replaced by a phandle at compile | |
1153 | time), export of reserve map address to the asm file, ability to | |
1154 | specify reserve map content at compile time, etc... | |
1155 | ||
1156 | We may provide a .h include file with common definitions of that | |
1157 | proves useful for some properties (like building PCI properties or | |
1158 | interrupt maps) though it may be better to add a notion of struct | |
1159 | definitions to the compiler... | |
1160 | ||
1161 | ||
1162 | V - Recommendations for a bootloader | |
1163 | ==================================== | |
1164 | ||
1165 | ||
1166 | Here are some various ideas/recommendations that have been proposed | |
1167 | while all this has been defined and implemented. | |
1168 | ||
1169 | - The bootloader may want to be able to use the device-tree itself | |
1170 | and may want to manipulate it (to add/edit some properties, | |
1171 | like physical memory size or kernel arguments). At this point, 2 | |
1172 | choices can be made. Either the bootloader works directly on the | |
1173 | flattened format, or the bootloader has its own internal tree | |
1174 | representation with pointers (similar to the kernel one) and | |
1175 | re-flattens the tree when booting the kernel. The former is a bit | |
1176 | more difficult to edit/modify, the later requires probably a bit | |
1177 | more code to handle the tree structure. Note that the structure | |
1178 | format has been designed so it's relatively easy to "insert" | |
1179 | properties or nodes or delete them by just memmoving things | |
1180 | around. It contains no internal offsets or pointers for this | |
1181 | purpose. | |
1182 | ||
d6bc8ac9 | 1183 | - An example of code for iterating nodes & retrieving properties |
c125a183 DG |
1184 | directly from the flattened tree format can be found in the kernel |
1185 | file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function, | |
d6bc8ac9 | 1186 | its usage in early_init_devtree(), and the corresponding various |
c125a183 DG |
1187 | early_init_dt_scan_*() callbacks. That code can be re-used in a |
1188 | GPL bootloader, and as the author of that code, I would be happy | |
5dd60166 | 1189 | to discuss possible free licensing to any vendor who wishes to |
c125a183 DG |
1190 | integrate all or part of this code into a non-GPL bootloader. |
1191 | ||
1192 | ||
1193 | ||
1194 | VI - System-on-a-chip devices and nodes | |
1195 | ======================================= | |
1196 | ||
1197 | Many companies are now starting to develop system-on-a-chip | |
5dd60166 | 1198 | processors, where the processor core (CPU) and many peripheral devices |
c125a183 DG |
1199 | exist on a single piece of silicon. For these SOCs, an SOC node |
1200 | should be used that defines child nodes for the devices that make | |
1201 | up the SOC. While platforms are not required to use this model in | |
1202 | order to boot the kernel, it is highly encouraged that all SOC | |
1203 | implementations define as complete a flat-device-tree as possible to | |
1204 | describe the devices on the SOC. This will allow for the | |
1205 | genericization of much of the kernel code. | |
1206 | ||
1207 | ||
1208 | 1) Defining child nodes of an SOC | |
1209 | --------------------------------- | |
1210 | ||
1211 | Each device that is part of an SOC may have its own node entry inside | |
1212 | the SOC node. For each device that is included in the SOC, the unit | |
1213 | address property represents the address offset for this device's | |
1214 | memory-mapped registers in the parent's address space. The parent's | |
1215 | address space is defined by the "ranges" property in the top-level soc | |
1216 | node. The "reg" property for each node that exists directly under the | |
1217 | SOC node should contain the address mapping from the child address space | |
1218 | to the parent SOC address space and the size of the device's | |
1219 | memory-mapped register file. | |
1220 | ||
1221 | For many devices that may exist inside an SOC, there are predefined | |
1222 | specifications for the format of the device tree node. All SOC child | |
1223 | nodes should follow these specifications, except where noted in this | |
1224 | document. | |
1225 | ||
1226 | See appendix A for an example partial SOC node definition for the | |
1227 | MPC8540. | |
1228 | ||
1229 | ||
27565903 | 1230 | 2) Representing devices without a current OF specification |
c125a183 DG |
1231 | ---------------------------------------------------------- |
1232 | ||
1233 | Currently, there are many devices on SOCs that do not have a standard | |
1234 | representation pre-defined as part of the open firmware | |
1235 | specifications, mainly because the boards that contain these SOCs are | |
1236 | not currently booted using open firmware. This section contains | |
1237 | descriptions for the SOC devices for which new nodes have been | |
1238 | defined; this list will expand as more and more SOC-containing | |
1239 | platforms are moved over to use the flattened-device-tree model. | |
1240 | ||
d0fc2eaa | 1241 | a) PHY nodes |
c125a183 DG |
1242 | |
1243 | Required properties: | |
1244 | ||
1245 | - device_type : Should be "ethernet-phy" | |
1246 | - interrupts : <a b> where a is the interrupt number and b is a | |
1247 | field that represents an encoding of the sense and level | |
1248 | information for the interrupt. This should be encoded based on | |
1249 | the information in section 2) depending on the type of interrupt | |
1250 | controller you have. | |
1251 | - interrupt-parent : the phandle for the interrupt controller that | |
1252 | services interrupts for this device. | |
1253 | - reg : The ID number for the phy, usually a small integer | |
1254 | - linux,phandle : phandle for this node; likely referenced by an | |
1255 | ethernet controller node. | |
1256 | ||
1257 | ||
1258 | Example: | |
1259 | ||
1260 | ethernet-phy@0 { | |
1261 | linux,phandle = <2452000> | |
1262 | interrupt-parent = <40000>; | |
1263 | interrupts = <35 1>; | |
1264 | reg = <0>; | |
1265 | device_type = "ethernet-phy"; | |
1266 | }; | |
1267 | ||
1268 | ||
d0fc2eaa | 1269 | b) Interrupt controllers |
c125a183 DG |
1270 | |
1271 | Some SOC devices contain interrupt controllers that are different | |
1272 | from the standard Open PIC specification. The SOC device nodes for | |
1273 | these types of controllers should be specified just like a standard | |
1274 | OpenPIC controller. Sense and level information should be encoded | |
1275 | as specified in section 2) of this chapter for each device that | |
1276 | specifies an interrupt. | |
1277 | ||
1278 | Example : | |
1279 | ||
1280 | pic@40000 { | |
1281 | linux,phandle = <40000>; | |
c125a183 DG |
1282 | interrupt-controller; |
1283 | #address-cells = <0>; | |
1284 | reg = <40000 40000>; | |
c125a183 DG |
1285 | compatible = "chrp,open-pic"; |
1286 | device_type = "open-pic"; | |
c125a183 DG |
1287 | }; |
1288 | ||
efcc2da3 | 1289 | c) 4xx/Axon EMAC ethernet nodes |
1d3bb996 DG |
1290 | |
1291 | The EMAC ethernet controller in IBM and AMCC 4xx chips, and also | |
1292 | the Axon bridge. To operate this needs to interact with a ths | |
1293 | special McMAL DMA controller, and sometimes an RGMII or ZMII | |
1294 | interface. In addition to the nodes and properties described | |
1295 | below, the node for the OPB bus on which the EMAC sits must have a | |
1296 | correct clock-frequency property. | |
1297 | ||
1298 | i) The EMAC node itself | |
1299 | ||
1300 | Required properties: | |
1301 | - device_type : "network" | |
1302 | ||
1303 | - compatible : compatible list, contains 2 entries, first is | |
1304 | "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, | |
1305 | 405gp, Axon) and second is either "ibm,emac" or | |
1306 | "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", | |
1307 | "ibm,emac4" | |
1308 | - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> | |
1309 | - interrupt-parent : optional, if needed for interrupt mapping | |
1310 | - reg : <registers mapping> | |
1311 | - local-mac-address : 6 bytes, MAC address | |
1312 | - mal-device : phandle of the associated McMAL node | |
1313 | - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated | |
1314 | with this EMAC | |
1315 | - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated | |
1316 | with this EMAC | |
1317 | - cell-index : 1 cell, hardware index of the EMAC cell on a given | |
1318 | ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on | |
1319 | each Axon chip) | |
1320 | - max-frame-size : 1 cell, maximum frame size supported in bytes | |
1321 | - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec | |
1322 | operations. | |
1323 | For Axon, 2048 | |
1324 | - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec | |
1325 | operations. | |
1326 | For Axon, 2048. | |
1327 | - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate | |
1328 | thresholds). | |
1329 | For Axon, 0x00000010 | |
1330 | - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds) | |
1331 | in bytes. | |
1332 | For Axon, 0x00000100 (I think ...) | |
1333 | - phy-mode : string, mode of operations of the PHY interface. | |
1334 | Supported values are: "mii", "rmii", "smii", "rgmii", | |
1335 | "tbi", "gmii", rtbi", "sgmii". | |
1336 | For Axon on CAB, it is "rgmii" | |
1337 | - mdio-device : 1 cell, required iff using shared MDIO registers | |
1338 | (440EP). phandle of the EMAC to use to drive the | |
1339 | MDIO lines for the PHY used by this EMAC. | |
1340 | - zmii-device : 1 cell, required iff connected to a ZMII. phandle of | |
1341 | the ZMII device node | |
1342 | - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII | |
1343 | channel or 0xffffffff if ZMII is only used for MDIO. | |
1344 | - rgmii-device : 1 cell, required iff connected to an RGMII. phandle | |
1345 | of the RGMII device node. | |
1346 | For Axon: phandle of plb5/plb4/opb/rgmii | |
1347 | - rgmii-channel : 1 cell, required iff connected to an RGMII. Which | |
1348 | RGMII channel is used by this EMAC. | |
1349 | Fox Axon: present, whatever value is appropriate for each | |
1350 | EMAC, that is the content of the current (bogus) "phy-port" | |
1351 | property. | |
1352 | ||
1d3bb996 DG |
1353 | Optional properties: |
1354 | - phy-address : 1 cell, optional, MDIO address of the PHY. If absent, | |
1355 | a search is performed. | |
1356 | - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY | |
1357 | for, used if phy-address is absent. bit 0x00000001 is | |
1358 | MDIO address 0. | |
1359 | For Axon it can be absent, thouugh my current driver | |
1360 | doesn't handle phy-address yet so for now, keep | |
1361 | 0x00ffffff in it. | |
1362 | - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec | |
1363 | operations (if absent the value is the same as | |
1364 | rx-fifo-size). For Axon, either absent or 2048. | |
1365 | - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec | |
1366 | operations (if absent the value is the same as | |
1367 | tx-fifo-size). For Axon, either absent or 2048. | |
1368 | - tah-device : 1 cell, optional. If connected to a TAH engine for | |
1369 | offload, phandle of the TAH device node. | |
1370 | - tah-channel : 1 cell, optional. If appropriate, channel used on the | |
1371 | TAH engine. | |
1372 | ||
1373 | Example: | |
1374 | ||
1375 | EMAC0: ethernet@40000800 { | |
1d3bb996 DG |
1376 | device_type = "network"; |
1377 | compatible = "ibm,emac-440gp", "ibm,emac"; | |
1378 | interrupt-parent = <&UIC1>; | |
1379 | interrupts = <1c 4 1d 4>; | |
1380 | reg = <40000800 70>; | |
1381 | local-mac-address = [00 04 AC E3 1B 1E]; | |
1382 | mal-device = <&MAL0>; | |
1383 | mal-tx-channel = <0 1>; | |
1384 | mal-rx-channel = <0>; | |
1385 | cell-index = <0>; | |
1386 | max-frame-size = <5dc>; | |
1387 | rx-fifo-size = <1000>; | |
1388 | tx-fifo-size = <800>; | |
1389 | phy-mode = "rmii"; | |
1390 | phy-map = <00000001>; | |
1391 | zmii-device = <&ZMII0>; | |
1392 | zmii-channel = <0>; | |
1393 | }; | |
1394 | ||
1395 | ii) McMAL node | |
1396 | ||
1397 | Required properties: | |
1398 | - device_type : "dma-controller" | |
1399 | - compatible : compatible list, containing 2 entries, first is | |
1400 | "ibm,mcmal-CHIP" where CHIP is the host ASIC (like | |
1401 | emac) and the second is either "ibm,mcmal" or | |
1402 | "ibm,mcmal2". | |
1403 | For Axon, "ibm,mcmal-axon","ibm,mcmal2" | |
1404 | - interrupts : <interrupt mapping for the MAL interrupts sources: | |
1405 | 5 sources: tx_eob, rx_eob, serr, txde, rxde>. | |
1406 | For Axon: This is _different_ from the current | |
1407 | firmware. We use the "delayed" interrupts for txeob | |
1408 | and rxeob. Thus we end up with mapping those 5 MPIC | |
1409 | interrupts, all level positive sensitive: 10, 11, 32, | |
1410 | 33, 34 (in decimal) | |
1411 | - dcr-reg : < DCR registers range > | |
1412 | - dcr-parent : if needed for dcr-reg | |
1413 | - num-tx-chans : 1 cell, number of Tx channels | |
1414 | - num-rx-chans : 1 cell, number of Rx channels | |
1415 | ||
1416 | iii) ZMII node | |
1417 | ||
1418 | Required properties: | |
1419 | - compatible : compatible list, containing 2 entries, first is | |
1420 | "ibm,zmii-CHIP" where CHIP is the host ASIC (like | |
1421 | EMAC) and the second is "ibm,zmii". | |
1422 | For Axon, there is no ZMII node. | |
1423 | - reg : <registers mapping> | |
1424 | ||
1425 | iv) RGMII node | |
1426 | ||
1427 | Required properties: | |
1428 | - compatible : compatible list, containing 2 entries, first is | |
1429 | "ibm,rgmii-CHIP" where CHIP is the host ASIC (like | |
1430 | EMAC) and the second is "ibm,rgmii". | |
1431 | For Axon, "ibm,rgmii-axon","ibm,rgmii" | |
1432 | - reg : <registers mapping> | |
1433 | - revision : as provided by the RGMII new version register if | |
1434 | available. | |
1435 | For Axon: 0x0000012a | |
1436 | ||
efcc2da3 | 1437 | d) Xilinx IP cores |
7ae0fa49 GL |
1438 | |
1439 | The Xilinx EDK toolchain ships with a set of IP cores (devices) for use | |
1440 | in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range | |
1441 | of standard device types (network, serial, etc.) and miscellanious | |
1442 | devices (gpio, LCD, spi, etc). Also, since these devices are | |
1443 | implemented within the fpga fabric every instance of the device can be | |
1444 | synthesised with different options that change the behaviour. | |
1445 | ||
1446 | Each IP-core has a set of parameters which the FPGA designer can use to | |
1447 | control how the core is synthesized. Historically, the EDK tool would | |
1448 | extract the device parameters relevant to device drivers and copy them | |
1449 | into an 'xparameters.h' in the form of #define symbols. This tells the | |
1450 | device drivers how the IP cores are configured, but it requres the kernel | |
1451 | to be recompiled every time the FPGA bitstream is resynthesized. | |
1452 | ||
1453 | The new approach is to export the parameters into the device tree and | |
1454 | generate a new device tree each time the FPGA bitstream changes. The | |
1455 | parameters which used to be exported as #defines will now become | |
1456 | properties of the device node. In general, device nodes for IP-cores | |
1457 | will take the following form: | |
1458 | ||
ab99eee8 | 1459 | (name): (generic-name)@(base-address) { |
7ae0fa49 GL |
1460 | compatible = "xlnx,(ip-core-name)-(HW_VER)" |
1461 | [, (list of compatible devices), ...]; | |
1462 | reg = <(baseaddr) (size)>; | |
1463 | interrupt-parent = <&interrupt-controller-phandle>; | |
1464 | interrupts = < ... >; | |
1465 | xlnx,(parameter1) = "(string-value)"; | |
1466 | xlnx,(parameter2) = <(int-value)>; | |
1467 | }; | |
1468 | ||
ab99eee8 SN |
1469 | (generic-name): an open firmware-style name that describes the |
1470 | generic class of device. Preferably, this is one word, such | |
1471 | as 'serial' or 'ethernet'. | |
7ae0fa49 GL |
1472 | (ip-core-name): the name of the ip block (given after the BEGIN |
1473 | directive in system.mhs). Should be in lowercase | |
1474 | and all underscores '_' converted to dashes '-'. | |
1475 | (name): is derived from the "PARAMETER INSTANCE" value. | |
1476 | (parameter#): C_* parameters from system.mhs. The C_ prefix is | |
1477 | dropped from the parameter name, the name is converted | |
1478 | to lowercase and all underscore '_' characters are | |
1479 | converted to dashes '-'. | |
ab99eee8 | 1480 | (baseaddr): the baseaddr parameter value (often named C_BASEADDR). |
7ae0fa49 | 1481 | (HW_VER): from the HW_VER parameter. |
ab99eee8 | 1482 | (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1). |
7ae0fa49 GL |
1483 | |
1484 | Typically, the compatible list will include the exact IP core version | |
1485 | followed by an older IP core version which implements the same | |
1486 | interface or any other device with the same interface. | |
1487 | ||
1488 | 'reg', 'interrupt-parent' and 'interrupts' are all optional properties. | |
1489 | ||
1490 | For example, the following block from system.mhs: | |
1491 | ||
1492 | BEGIN opb_uartlite | |
1493 | PARAMETER INSTANCE = opb_uartlite_0 | |
1494 | PARAMETER HW_VER = 1.00.b | |
1495 | PARAMETER C_BAUDRATE = 115200 | |
1496 | PARAMETER C_DATA_BITS = 8 | |
1497 | PARAMETER C_ODD_PARITY = 0 | |
1498 | PARAMETER C_USE_PARITY = 0 | |
1499 | PARAMETER C_CLK_FREQ = 50000000 | |
1500 | PARAMETER C_BASEADDR = 0xEC100000 | |
1501 | PARAMETER C_HIGHADDR = 0xEC10FFFF | |
1502 | BUS_INTERFACE SOPB = opb_7 | |
1503 | PORT OPB_Clk = CLK_50MHz | |
1504 | PORT Interrupt = opb_uartlite_0_Interrupt | |
1505 | PORT RX = opb_uartlite_0_RX | |
1506 | PORT TX = opb_uartlite_0_TX | |
1507 | PORT OPB_Rst = sys_bus_reset_0 | |
1508 | END | |
1509 | ||
1510 | becomes the following device tree node: | |
1511 | ||
ab99eee8 | 1512 | opb_uartlite_0: serial@ec100000 { |
7ae0fa49 GL |
1513 | device_type = "serial"; |
1514 | compatible = "xlnx,opb-uartlite-1.00.b"; | |
1515 | reg = <ec100000 10000>; | |
ab99eee8 | 1516 | interrupt-parent = <&opb_intc_0>; |
7ae0fa49 GL |
1517 | interrupts = <1 0>; // got this from the opb_intc parameters |
1518 | current-speed = <d#115200>; // standard serial device prop | |
1519 | clock-frequency = <d#50000000>; // standard serial device prop | |
1520 | xlnx,data-bits = <8>; | |
1521 | xlnx,odd-parity = <0>; | |
1522 | xlnx,use-parity = <0>; | |
1523 | }; | |
1524 | ||
ab99eee8 SN |
1525 | Some IP cores actually implement 2 or more logical devices. In |
1526 | this case, the device should still describe the whole IP core with | |
1527 | a single node and add a child node for each logical device. The | |
1528 | ranges property can be used to translate from parent IP-core to the | |
1529 | registers of each device. In addition, the parent node should be | |
1530 | compatible with the bus type 'xlnx,compound', and should contain | |
1531 | #address-cells and #size-cells, as with any other bus. (Note: this | |
1532 | makes the assumption that both logical devices have the same bus | |
1533 | binding. If this is not true, then separate nodes should be used | |
1534 | for each logical device). The 'cell-index' property can be used to | |
1535 | enumerate logical devices within an IP core. For example, the | |
1536 | following is the system.mhs entry for the dual ps2 controller found | |
1537 | on the ml403 reference design. | |
7ae0fa49 GL |
1538 | |
1539 | BEGIN opb_ps2_dual_ref | |
1540 | PARAMETER INSTANCE = opb_ps2_dual_ref_0 | |
1541 | PARAMETER HW_VER = 1.00.a | |
1542 | PARAMETER C_BASEADDR = 0xA9000000 | |
1543 | PARAMETER C_HIGHADDR = 0xA9001FFF | |
1544 | BUS_INTERFACE SOPB = opb_v20_0 | |
1545 | PORT Sys_Intr1 = ps2_1_intr | |
1546 | PORT Sys_Intr2 = ps2_2_intr | |
1547 | PORT Clkin1 = ps2_clk_rx_1 | |
1548 | PORT Clkin2 = ps2_clk_rx_2 | |
1549 | PORT Clkpd1 = ps2_clk_tx_1 | |
1550 | PORT Clkpd2 = ps2_clk_tx_2 | |
1551 | PORT Rx1 = ps2_d_rx_1 | |
1552 | PORT Rx2 = ps2_d_rx_2 | |
1553 | PORT Txpd1 = ps2_d_tx_1 | |
1554 | PORT Txpd2 = ps2_d_tx_2 | |
1555 | END | |
1556 | ||
1557 | It would result in the following device tree nodes: | |
1558 | ||
ab99eee8 SN |
1559 | opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 { |
1560 | #address-cells = <1>; | |
1561 | #size-cells = <1>; | |
1562 | compatible = "xlnx,compound"; | |
7ae0fa49 GL |
1563 | ranges = <0 a9000000 2000>; |
1564 | // If this device had extra parameters, then they would | |
1565 | // go here. | |
1566 | ps2@0 { | |
1567 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | |
1568 | reg = <0 40>; | |
ab99eee8 | 1569 | interrupt-parent = <&opb_intc_0>; |
7ae0fa49 GL |
1570 | interrupts = <3 0>; |
1571 | cell-index = <0>; | |
1572 | }; | |
1573 | ps2@1000 { | |
1574 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | |
1575 | reg = <1000 40>; | |
ab99eee8 | 1576 | interrupt-parent = <&opb_intc_0>; |
7ae0fa49 GL |
1577 | interrupts = <3 0>; |
1578 | cell-index = <0>; | |
1579 | }; | |
1580 | }; | |
1581 | ||
1582 | Also, the system.mhs file defines bus attachments from the processor | |
1583 | to the devices. The device tree structure should reflect the bus | |
1584 | attachments. Again an example; this system.mhs fragment: | |
1585 | ||
1586 | BEGIN ppc405_virtex4 | |
1587 | PARAMETER INSTANCE = ppc405_0 | |
1588 | PARAMETER HW_VER = 1.01.a | |
1589 | BUS_INTERFACE DPLB = plb_v34_0 | |
1590 | BUS_INTERFACE IPLB = plb_v34_0 | |
1591 | END | |
1592 | ||
1593 | BEGIN opb_intc | |
1594 | PARAMETER INSTANCE = opb_intc_0 | |
1595 | PARAMETER HW_VER = 1.00.c | |
1596 | PARAMETER C_BASEADDR = 0xD1000FC0 | |
1597 | PARAMETER C_HIGHADDR = 0xD1000FDF | |
1598 | BUS_INTERFACE SOPB = opb_v20_0 | |
1599 | END | |
1600 | ||
1601 | BEGIN opb_uart16550 | |
1602 | PARAMETER INSTANCE = opb_uart16550_0 | |
1603 | PARAMETER HW_VER = 1.00.d | |
1604 | PARAMETER C_BASEADDR = 0xa0000000 | |
1605 | PARAMETER C_HIGHADDR = 0xa0001FFF | |
1606 | BUS_INTERFACE SOPB = opb_v20_0 | |
1607 | END | |
1608 | ||
1609 | BEGIN plb_v34 | |
1610 | PARAMETER INSTANCE = plb_v34_0 | |
1611 | PARAMETER HW_VER = 1.02.a | |
1612 | END | |
1613 | ||
1614 | BEGIN plb_bram_if_cntlr | |
1615 | PARAMETER INSTANCE = plb_bram_if_cntlr_0 | |
1616 | PARAMETER HW_VER = 1.00.b | |
1617 | PARAMETER C_BASEADDR = 0xFFFF0000 | |
1618 | PARAMETER C_HIGHADDR = 0xFFFFFFFF | |
1619 | BUS_INTERFACE SPLB = plb_v34_0 | |
1620 | END | |
1621 | ||
1622 | BEGIN plb2opb_bridge | |
1623 | PARAMETER INSTANCE = plb2opb_bridge_0 | |
1624 | PARAMETER HW_VER = 1.01.a | |
1625 | PARAMETER C_RNG0_BASEADDR = 0x20000000 | |
1626 | PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF | |
1627 | PARAMETER C_RNG1_BASEADDR = 0x60000000 | |
1628 | PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF | |
1629 | PARAMETER C_RNG2_BASEADDR = 0x80000000 | |
1630 | PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF | |
1631 | PARAMETER C_RNG3_BASEADDR = 0xC0000000 | |
1632 | PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF | |
1633 | BUS_INTERFACE SPLB = plb_v34_0 | |
1634 | BUS_INTERFACE MOPB = opb_v20_0 | |
1635 | END | |
1636 | ||
1637 | Gives this device tree (some properties removed for clarity): | |
1638 | ||
ab99eee8 | 1639 | plb@0 { |
7ae0fa49 GL |
1640 | #address-cells = <1>; |
1641 | #size-cells = <1>; | |
ab99eee8 | 1642 | compatible = "xlnx,plb-v34-1.02.a"; |
7ae0fa49 GL |
1643 | device_type = "ibm,plb"; |
1644 | ranges; // 1:1 translation | |
1645 | ||
ab99eee8 | 1646 | plb_bram_if_cntrl_0: bram@ffff0000 { |
7ae0fa49 GL |
1647 | reg = <ffff0000 10000>; |
1648 | } | |
1649 | ||
ab99eee8 | 1650 | opb@20000000 { |
7ae0fa49 GL |
1651 | #address-cells = <1>; |
1652 | #size-cells = <1>; | |
1653 | ranges = <20000000 20000000 20000000 | |
1654 | 60000000 60000000 20000000 | |
1655 | 80000000 80000000 40000000 | |
1656 | c0000000 c0000000 20000000>; | |
1657 | ||
ab99eee8 | 1658 | opb_uart16550_0: serial@a0000000 { |
7ae0fa49 GL |
1659 | reg = <a00000000 2000>; |
1660 | }; | |
1661 | ||
ab99eee8 | 1662 | opb_intc_0: interrupt-controller@d1000fc0 { |
7ae0fa49 GL |
1663 | reg = <d1000fc0 20>; |
1664 | }; | |
1665 | }; | |
1666 | }; | |
1667 | ||
1668 | That covers the general approach to binding xilinx IP cores into the | |
1669 | device tree. The following are bindings for specific devices: | |
1670 | ||
1671 | i) Xilinx ML300 Framebuffer | |
1672 | ||
1673 | Simple framebuffer device from the ML300 reference design (also on the | |
1674 | ML403 reference design as well as others). | |
1675 | ||
1676 | Optional properties: | |
1677 | - resolution = <xres yres> : pixel resolution of framebuffer. Some | |
1678 | implementations use a different resolution. | |
1679 | Default is <d#640 d#480> | |
1680 | - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. | |
1681 | Default is <d#1024 d#480>. | |
1682 | - rotate-display (empty) : rotate display 180 degrees. | |
1683 | ||
1684 | ii) Xilinx SystemACE | |
1685 | ||
1686 | The Xilinx SystemACE device is used to program FPGAs from an FPGA | |
1687 | bitstream stored on a CF card. It can also be used as a generic CF | |
1688 | interface device. | |
1689 | ||
1690 | Optional properties: | |
1691 | - 8-bit (empty) : Set this property for SystemACE in 8 bit mode | |
1692 | ||
1693 | iii) Xilinx EMAC and Xilinx TEMAC | |
1694 | ||
1695 | Xilinx Ethernet devices. In addition to general xilinx properties | |
1696 | listed above, nodes for these devices should include a phy-handle | |
1697 | property, and may include other common network device properties | |
1698 | like local-mac-address. | |
efcc2da3 | 1699 | |
7ae0fa49 GL |
1700 | iv) Xilinx Uartlite |
1701 | ||
1702 | Xilinx uartlite devices are simple fixed speed serial ports. | |
1703 | ||
d9195881 | 1704 | Required properties: |
7ae0fa49 GL |
1705 | - current-speed : Baud rate of uartlite |
1706 | ||
ef66a9d2 SN |
1707 | v) Xilinx hwicap |
1708 | ||
1709 | Xilinx hwicap devices provide access to the configuration logic | |
1710 | of the FPGA through the Internal Configuration Access Port | |
1711 | (ICAP). The ICAP enables partial reconfiguration of the FPGA, | |
1712 | readback of the configuration information, and some control over | |
1713 | 'warm boots' of the FPGA fabric. | |
1714 | ||
1715 | Required properties: | |
1716 | - xlnx,family : The family of the FPGA, necessary since the | |
1717 | capabilities of the underlying ICAP hardware | |
1718 | differ between different families. May be | |
1719 | 'virtex2p', 'virtex4', or 'virtex5'. | |
1720 | ||
b912b5e2 JL |
1721 | vi) Xilinx Uart 16550 |
1722 | ||
1723 | Xilinx UART 16550 devices are very similar to the NS16550 but with | |
1724 | different register spacing and an offset from the base address. | |
1725 | ||
d9195881 | 1726 | Required properties: |
b912b5e2 JL |
1727 | - clock-frequency : Frequency of the clock input |
1728 | - reg-offset : A value of 3 is required | |
1729 | - reg-shift : A value of 2 is required | |
1730 | ||
efcc2da3 | 1731 | e) USB EHCI controllers |
41abd68e VB |
1732 | |
1733 | Required properties: | |
1734 | - compatible : should be "usb-ehci". | |
1735 | - reg : should contain at least address and length of the standard EHCI | |
1736 | register set for the device. Optional platform-dependent registers | |
1737 | (debug-port or other) can be also specified here, but only after | |
1738 | definition of standard EHCI registers. | |
1739 | - interrupts : one EHCI interrupt should be described here. | |
1740 | If device registers are implemented in big endian mode, the device | |
1741 | node should have "big-endian-regs" property. | |
1742 | If controller implementation operates with big endian descriptors, | |
1743 | "big-endian-desc" property should be specified. | |
1744 | If both big endian registers and descriptors are used by the controller | |
1745 | implementation, "big-endian" property can be specified instead of having | |
1746 | both "big-endian-regs" and "big-endian-desc". | |
1747 | ||
1748 | Example (Sequoia 440EPx): | |
1749 | ehci@e0000300 { | |
1750 | compatible = "ibm,usb-ehci-440epx", "usb-ehci"; | |
1751 | interrupt-parent = <&UIC0>; | |
1752 | interrupts = <1a 4>; | |
1753 | reg = <0 e0000300 90 0 e0000390 70>; | |
1754 | big-endian; | |
1755 | }; | |
1756 | ||
efcc2da3 | 1757 | f) MDIO on GPIOs |
a5edeccb LP |
1758 | |
1759 | Currently defined compatibles: | |
1760 | - virtual,gpio-mdio | |
1761 | ||
1762 | MDC and MDIO lines connected to GPIO controllers are listed in the | |
1763 | gpios property as described in section VIII.1 in the following order: | |
1764 | ||
1765 | MDC, MDIO. | |
1766 | ||
1767 | Example: | |
1768 | ||
1769 | mdio { | |
1770 | compatible = "virtual,mdio-gpio"; | |
1771 | #address-cells = <1>; | |
1772 | #size-cells = <0>; | |
1773 | gpios = <&qe_pio_a 11 | |
1774 | &qe_pio_c 6>; | |
1775 | }; | |
1776 | ||
efcc2da3 | 1777 | g) SPI (Serial Peripheral Interface) busses |
79c28acb GL |
1778 | |
1779 | SPI busses can be described with a node for the SPI master device | |
1780 | and a set of child nodes for each SPI slave on the bus. For this | |
1781 | discussion, it is assumed that the system's SPI controller is in | |
1782 | SPI master mode. This binding does not describe SPI controllers | |
1783 | in slave mode. | |
1784 | ||
1785 | The SPI master node requires the following properties: | |
1786 | - #address-cells - number of cells required to define a chip select | |
1787 | address on the SPI bus. | |
1788 | - #size-cells - should be zero. | |
1789 | - compatible - name of SPI bus controller following generic names | |
1790 | recommended practice. | |
1791 | No other properties are required in the SPI bus node. It is assumed | |
1792 | that a driver for an SPI bus device will understand that it is an SPI bus. | |
1793 | However, the binding does not attempt to define the specific method for | |
1794 | assigning chip select numbers. Since SPI chip select configuration is | |
1795 | flexible and non-standardized, it is left out of this binding with the | |
1796 | assumption that board specific platform code will be used to manage | |
1797 | chip selects. Individual drivers can define additional properties to | |
1798 | support describing the chip select layout. | |
1799 | ||
1800 | SPI slave nodes must be children of the SPI master node and can | |
1801 | contain the following properties. | |
1802 | - reg - (required) chip select address of device. | |
1803 | - compatible - (required) name of SPI device following generic names | |
1804 | recommended practice | |
1805 | - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz | |
1806 | - spi-cpol - (optional) Empty property indicating device requires | |
1807 | inverse clock polarity (CPOL) mode | |
1808 | - spi-cpha - (optional) Empty property indicating device requires | |
1809 | shifted clock phase (CPHA) mode | |
f618ebfc WO |
1810 | - spi-cs-high - (optional) Empty property indicating device requires |
1811 | chip select active high | |
79c28acb GL |
1812 | |
1813 | SPI example for an MPC5200 SPI bus: | |
1814 | spi@f00 { | |
1815 | #address-cells = <1>; | |
1816 | #size-cells = <0>; | |
1817 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; | |
1818 | reg = <0xf00 0x20>; | |
1819 | interrupts = <2 13 0 2 14 0>; | |
1820 | interrupt-parent = <&mpc5200_pic>; | |
1821 | ||
1822 | ethernet-switch@0 { | |
1823 | compatible = "micrel,ks8995m"; | |
1824 | spi-max-frequency = <1000000>; | |
1825 | reg = <0>; | |
1826 | }; | |
1827 | ||
1828 | codec@1 { | |
1829 | compatible = "ti,tlv320aic26"; | |
1830 | spi-max-frequency = <100000>; | |
1831 | reg = <1>; | |
1832 | }; | |
1833 | }; | |
1834 | ||
f5412c49 DF |
1835 | VII - Marvell Discovery mv64[345]6x System Controller chips |
1836 | =========================================================== | |
c125a183 | 1837 | |
f5412c49 DF |
1838 | The Marvell mv64[345]60 series of system controller chips contain |
1839 | many of the peripherals needed to implement a complete computer | |
1840 | system. In this section, we define device tree nodes to describe | |
1841 | the system controller chip itself and each of the peripherals | |
1842 | which it contains. Compatible string values for each node are | |
1843 | prefixed with the string "marvell,", for Marvell Technology Group Ltd. | |
1844 | ||
1845 | 1) The /system-controller node | |
1846 | ||
1847 | This node is used to represent the system-controller and must be | |
d9195881 | 1848 | present when the system uses a system controller chip. The top-level |
f5412c49 DF |
1849 | system-controller node contains information that is global to all |
1850 | devices within the system controller chip. The node name begins | |
1851 | with "system-controller" followed by the unit address, which is | |
1852 | the base address of the memory-mapped register set for the system | |
1853 | controller chip. | |
1854 | ||
1855 | Required properties: | |
1856 | ||
1857 | - ranges : Describes the translation of system controller addresses | |
1858 | for memory mapped registers. | |
1859 | - clock-frequency: Contains the main clock frequency for the system | |
1860 | controller chip. | |
1861 | - reg : This property defines the address and size of the | |
1862 | memory-mapped registers contained within the system controller | |
1863 | chip. The address specified in the "reg" property should match | |
1864 | the unit address of the system-controller node. | |
1865 | - #address-cells : Address representation for system controller | |
1866 | devices. This field represents the number of cells needed to | |
1867 | represent the address of the memory-mapped registers of devices | |
1868 | within the system controller chip. | |
1869 | - #size-cells : Size representation for for the memory-mapped | |
1870 | registers within the system controller chip. | |
1871 | - #interrupt-cells : Defines the width of cells used to represent | |
1872 | interrupts. | |
1873 | ||
1874 | Optional properties: | |
1875 | ||
1876 | - model : The specific model of the system controller chip. Such | |
1877 | as, "mv64360", "mv64460", or "mv64560". | |
1878 | - compatible : A string identifying the compatibility identifiers | |
1879 | of the system controller chip. | |
1880 | ||
1881 | The system-controller node contains child nodes for each system | |
1882 | controller device that the platform uses. Nodes should not be created | |
1883 | for devices which exist on the system controller chip but are not used | |
1884 | ||
1885 | Example Marvell Discovery mv64360 system-controller node: | |
1886 | ||
1887 | system-controller@f1000000 { /* Marvell Discovery mv64360 */ | |
1888 | #address-cells = <1>; | |
1889 | #size-cells = <1>; | |
1890 | model = "mv64360"; /* Default */ | |
1891 | compatible = "marvell,mv64360"; | |
1892 | clock-frequency = <133333333>; | |
1893 | reg = <0xf1000000 0x10000>; | |
1894 | virtual-reg = <0xf1000000>; | |
1895 | ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */ | |
1896 | 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */ | |
1897 | 0xa0000000 0xa0000000 0x4000000 /* User FLASH */ | |
1898 | 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */ | |
1899 | 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */ | |
1900 | ||
1901 | [ child node definitions... ] | |
1902 | } | |
1903 | ||
1904 | 2) Child nodes of /system-controller | |
1905 | ||
1906 | a) Marvell Discovery MDIO bus | |
1907 | ||
1908 | The MDIO is a bus to which the PHY devices are connected. For each | |
1909 | device that exists on this bus, a child node should be created. See | |
1910 | the definition of the PHY node below for an example of how to define | |
1911 | a PHY. | |
1912 | ||
1913 | Required properties: | |
1914 | - #address-cells : Should be <1> | |
1915 | - #size-cells : Should be <0> | |
1916 | - device_type : Should be "mdio" | |
1917 | - compatible : Should be "marvell,mv64360-mdio" | |
1918 | ||
1919 | Example: | |
1920 | ||
1921 | mdio { | |
1922 | #address-cells = <1>; | |
1923 | #size-cells = <0>; | |
1924 | device_type = "mdio"; | |
1925 | compatible = "marvell,mv64360-mdio"; | |
1926 | ||
1927 | ethernet-phy@0 { | |
1928 | ...... | |
1929 | }; | |
1930 | }; | |
1931 | ||
1932 | ||
1933 | b) Marvell Discovery ethernet controller | |
1934 | ||
1935 | The Discover ethernet controller is described with two levels | |
1936 | of nodes. The first level describes an ethernet silicon block | |
1937 | and the second level describes up to 3 ethernet nodes within | |
1938 | that block. The reason for the multiple levels is that the | |
1939 | registers for the node are interleaved within a single set | |
1940 | of registers. The "ethernet-block" level describes the | |
1941 | shared register set, and the "ethernet" nodes describe ethernet | |
1942 | port-specific properties. | |
1943 | ||
1944 | Ethernet block node | |
1945 | ||
1946 | Required properties: | |
1947 | - #address-cells : <1> | |
1948 | - #size-cells : <0> | |
1949 | - compatible : "marvell,mv64360-eth-block" | |
1950 | - reg : Offset and length of the register set for this block | |
1951 | ||
1952 | Example Discovery Ethernet block node: | |
1953 | ethernet-block@2000 { | |
1954 | #address-cells = <1>; | |
1955 | #size-cells = <0>; | |
1956 | compatible = "marvell,mv64360-eth-block"; | |
1957 | reg = <0x2000 0x2000>; | |
1958 | ethernet@0 { | |
1959 | ....... | |
1960 | }; | |
1961 | }; | |
1962 | ||
1963 | Ethernet port node | |
1964 | ||
1965 | Required properties: | |
1966 | - device_type : Should be "network". | |
1967 | - compatible : Should be "marvell,mv64360-eth". | |
1968 | - reg : Should be <0>, <1>, or <2>, according to which registers | |
1969 | within the silicon block the device uses. | |
1970 | - interrupts : <a> where a is the interrupt number for the port. | |
1971 | - interrupt-parent : the phandle for the interrupt controller | |
1972 | that services interrupts for this device. | |
1973 | - phy : the phandle for the PHY connected to this ethernet | |
1974 | controller. | |
1975 | - local-mac-address : 6 bytes, MAC address | |
1976 | ||
1977 | Example Discovery Ethernet port node: | |
1978 | ethernet@0 { | |
1979 | device_type = "network"; | |
1980 | compatible = "marvell,mv64360-eth"; | |
1981 | reg = <0>; | |
1982 | interrupts = <32>; | |
1983 | interrupt-parent = <&PIC>; | |
1984 | phy = <&PHY0>; | |
1985 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
1986 | }; | |
1987 | ||
1988 | ||
1989 | ||
1990 | c) Marvell Discovery PHY nodes | |
1991 | ||
1992 | Required properties: | |
1993 | - device_type : Should be "ethernet-phy" | |
1994 | - interrupts : <a> where a is the interrupt number for this phy. | |
1995 | - interrupt-parent : the phandle for the interrupt controller that | |
1996 | services interrupts for this device. | |
1997 | - reg : The ID number for the phy, usually a small integer | |
1998 | ||
1999 | Example Discovery PHY node: | |
2000 | ethernet-phy@1 { | |
2001 | device_type = "ethernet-phy"; | |
2002 | compatible = "broadcom,bcm5421"; | |
2003 | interrupts = <76>; /* GPP 12 */ | |
2004 | interrupt-parent = <&PIC>; | |
2005 | reg = <1>; | |
2006 | }; | |
2007 | ||
2008 | ||
2009 | d) Marvell Discovery SDMA nodes | |
2010 | ||
2011 | Represent DMA hardware associated with the MPSC (multiprotocol | |
2012 | serial controllers). | |
2013 | ||
2014 | Required properties: | |
2015 | - compatible : "marvell,mv64360-sdma" | |
2016 | - reg : Offset and length of the register set for this device | |
2017 | - interrupts : <a> where a is the interrupt number for the DMA | |
2018 | device. | |
2019 | - interrupt-parent : the phandle for the interrupt controller | |
2020 | that services interrupts for this device. | |
2021 | ||
2022 | Example Discovery SDMA node: | |
2023 | sdma@4000 { | |
2024 | compatible = "marvell,mv64360-sdma"; | |
2025 | reg = <0x4000 0xc18>; | |
2026 | virtual-reg = <0xf1004000>; | |
2027 | interrupts = <36>; | |
2028 | interrupt-parent = <&PIC>; | |
2029 | }; | |
2030 | ||
2031 | ||
2032 | e) Marvell Discovery BRG nodes | |
2033 | ||
2034 | Represent baud rate generator hardware associated with the MPSC | |
2035 | (multiprotocol serial controllers). | |
2036 | ||
2037 | Required properties: | |
2038 | - compatible : "marvell,mv64360-brg" | |
2039 | - reg : Offset and length of the register set for this device | |
2040 | - clock-src : A value from 0 to 15 which selects the clock | |
2041 | source for the baud rate generator. This value corresponds | |
2042 | to the CLKS value in the BRGx configuration register. See | |
2043 | the mv64x60 User's Manual. | |
2044 | - clock-frequence : The frequency (in Hz) of the baud rate | |
2045 | generator's input clock. | |
2046 | - current-speed : The current speed setting (presumably by | |
2047 | firmware) of the baud rate generator. | |
2048 | ||
2049 | Example Discovery BRG node: | |
2050 | brg@b200 { | |
2051 | compatible = "marvell,mv64360-brg"; | |
2052 | reg = <0xb200 0x8>; | |
2053 | clock-src = <8>; | |
2054 | clock-frequency = <133333333>; | |
2055 | current-speed = <9600>; | |
2056 | }; | |
2057 | ||
2058 | ||
2059 | f) Marvell Discovery CUNIT nodes | |
2060 | ||
2061 | Represent the Serial Communications Unit device hardware. | |
2062 | ||
2063 | Required properties: | |
2064 | - reg : Offset and length of the register set for this device | |
2065 | ||
2066 | Example Discovery CUNIT node: | |
2067 | cunit@f200 { | |
2068 | reg = <0xf200 0x200>; | |
2069 | }; | |
2070 | ||
2071 | ||
2072 | g) Marvell Discovery MPSCROUTING nodes | |
2073 | ||
2074 | Represent the Discovery's MPSC routing hardware | |
2075 | ||
2076 | Required properties: | |
2077 | - reg : Offset and length of the register set for this device | |
2078 | ||
2079 | Example Discovery CUNIT node: | |
2080 | mpscrouting@b500 { | |
2081 | reg = <0xb400 0xc>; | |
2082 | }; | |
2083 | ||
2084 | ||
2085 | h) Marvell Discovery MPSCINTR nodes | |
2086 | ||
2087 | Represent the Discovery's MPSC DMA interrupt hardware registers | |
2088 | (SDMA cause and mask registers). | |
2089 | ||
2090 | Required properties: | |
2091 | - reg : Offset and length of the register set for this device | |
2092 | ||
2093 | Example Discovery MPSCINTR node: | |
2094 | mpsintr@b800 { | |
2095 | reg = <0xb800 0x100>; | |
2096 | }; | |
2097 | ||
2098 | ||
2099 | i) Marvell Discovery MPSC nodes | |
2100 | ||
2101 | Represent the Discovery's MPSC (Multiprotocol Serial Controller) | |
2102 | serial port. | |
2103 | ||
2104 | Required properties: | |
2105 | - device_type : "serial" | |
2106 | - compatible : "marvell,mv64360-mpsc" | |
2107 | - reg : Offset and length of the register set for this device | |
2108 | - sdma : the phandle for the SDMA node used by this port | |
2109 | - brg : the phandle for the BRG node used by this port | |
2110 | - cunit : the phandle for the CUNIT node used by this port | |
2111 | - mpscrouting : the phandle for the MPSCROUTING node used by this port | |
2112 | - mpscintr : the phandle for the MPSCINTR node used by this port | |
2113 | - cell-index : the hardware index of this cell in the MPSC core | |
2114 | - max_idle : value needed for MPSC CHR3 (Maximum Frame Length) | |
2115 | register | |
2116 | - interrupts : <a> where a is the interrupt number for the MPSC. | |
2117 | - interrupt-parent : the phandle for the interrupt controller | |
2118 | that services interrupts for this device. | |
2119 | ||
2120 | Example Discovery MPSCINTR node: | |
2121 | mpsc@8000 { | |
2122 | device_type = "serial"; | |
2123 | compatible = "marvell,mv64360-mpsc"; | |
2124 | reg = <0x8000 0x38>; | |
2125 | virtual-reg = <0xf1008000>; | |
2126 | sdma = <&SDMA0>; | |
2127 | brg = <&BRG0>; | |
2128 | cunit = <&CUNIT>; | |
2129 | mpscrouting = <&MPSCROUTING>; | |
2130 | mpscintr = <&MPSCINTR>; | |
2131 | cell-index = <0>; | |
2132 | max_idle = <40>; | |
2133 | interrupts = <40>; | |
2134 | interrupt-parent = <&PIC>; | |
2135 | }; | |
2136 | ||
2137 | ||
2138 | j) Marvell Discovery Watch Dog Timer nodes | |
2139 | ||
2140 | Represent the Discovery's watchdog timer hardware | |
2141 | ||
2142 | Required properties: | |
2143 | - compatible : "marvell,mv64360-wdt" | |
2144 | - reg : Offset and length of the register set for this device | |
2145 | ||
2146 | Example Discovery Watch Dog Timer node: | |
2147 | wdt@b410 { | |
2148 | compatible = "marvell,mv64360-wdt"; | |
2149 | reg = <0xb410 0x8>; | |
2150 | }; | |
2151 | ||
2152 | ||
2153 | k) Marvell Discovery I2C nodes | |
2154 | ||
2155 | Represent the Discovery's I2C hardware | |
2156 | ||
2157 | Required properties: | |
2158 | - device_type : "i2c" | |
2159 | - compatible : "marvell,mv64360-i2c" | |
2160 | - reg : Offset and length of the register set for this device | |
2161 | - interrupts : <a> where a is the interrupt number for the I2C. | |
2162 | - interrupt-parent : the phandle for the interrupt controller | |
2163 | that services interrupts for this device. | |
2164 | ||
2165 | Example Discovery I2C node: | |
2166 | compatible = "marvell,mv64360-i2c"; | |
2167 | reg = <0xc000 0x20>; | |
2168 | virtual-reg = <0xf100c000>; | |
2169 | interrupts = <37>; | |
2170 | interrupt-parent = <&PIC>; | |
2171 | }; | |
2172 | ||
2173 | ||
2174 | l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes | |
2175 | ||
2176 | Represent the Discovery's PIC hardware | |
2177 | ||
2178 | Required properties: | |
2179 | - #interrupt-cells : <1> | |
2180 | - #address-cells : <0> | |
2181 | - compatible : "marvell,mv64360-pic" | |
2182 | - reg : Offset and length of the register set for this device | |
2183 | - interrupt-controller | |
2184 | ||
2185 | Example Discovery PIC node: | |
2186 | pic { | |
2187 | #interrupt-cells = <1>; | |
2188 | #address-cells = <0>; | |
2189 | compatible = "marvell,mv64360-pic"; | |
2190 | reg = <0x0 0x88>; | |
2191 | interrupt-controller; | |
2192 | }; | |
2193 | ||
2194 | ||
2195 | m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes | |
2196 | ||
2197 | Represent the Discovery's MPP hardware | |
2198 | ||
2199 | Required properties: | |
2200 | - compatible : "marvell,mv64360-mpp" | |
2201 | - reg : Offset and length of the register set for this device | |
2202 | ||
2203 | Example Discovery MPP node: | |
2204 | mpp@f000 { | |
2205 | compatible = "marvell,mv64360-mpp"; | |
2206 | reg = <0xf000 0x10>; | |
2207 | }; | |
2208 | ||
2209 | ||
2210 | n) Marvell Discovery GPP (General Purpose Pins) nodes | |
2211 | ||
2212 | Represent the Discovery's GPP hardware | |
2213 | ||
2214 | Required properties: | |
2215 | - compatible : "marvell,mv64360-gpp" | |
2216 | - reg : Offset and length of the register set for this device | |
2217 | ||
2218 | Example Discovery GPP node: | |
2219 | gpp@f000 { | |
2220 | compatible = "marvell,mv64360-gpp"; | |
2221 | reg = <0xf100 0x20>; | |
2222 | }; | |
2223 | ||
2224 | ||
2225 | o) Marvell Discovery PCI host bridge node | |
2226 | ||
2227 | Represents the Discovery's PCI host bridge device. The properties | |
2228 | for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE | |
2229 | 1275-1994. A typical value for the compatible property is | |
2230 | "marvell,mv64360-pci". | |
2231 | ||
2232 | Example Discovery PCI host bridge node | |
2233 | pci@80000000 { | |
2234 | #address-cells = <3>; | |
2235 | #size-cells = <2>; | |
2236 | #interrupt-cells = <1>; | |
2237 | device_type = "pci"; | |
2238 | compatible = "marvell,mv64360-pci"; | |
2239 | reg = <0xcf8 0x8>; | |
2240 | ranges = <0x01000000 0x0 0x0 | |
2241 | 0x88000000 0x0 0x01000000 | |
2242 | 0x02000000 0x0 0x80000000 | |
2243 | 0x80000000 0x0 0x08000000>; | |
2244 | bus-range = <0 255>; | |
2245 | clock-frequency = <66000000>; | |
2246 | interrupt-parent = <&PIC>; | |
2247 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
2248 | interrupt-map = < | |
2249 | /* IDSEL 0x0a */ | |
2250 | 0x5000 0 0 1 &PIC 80 | |
2251 | 0x5000 0 0 2 &PIC 81 | |
2252 | 0x5000 0 0 3 &PIC 91 | |
2253 | 0x5000 0 0 4 &PIC 93 | |
2254 | ||
2255 | /* IDSEL 0x0b */ | |
2256 | 0x5800 0 0 1 &PIC 91 | |
2257 | 0x5800 0 0 2 &PIC 93 | |
2258 | 0x5800 0 0 3 &PIC 80 | |
2259 | 0x5800 0 0 4 &PIC 81 | |
2260 | ||
2261 | /* IDSEL 0x0c */ | |
2262 | 0x6000 0 0 1 &PIC 91 | |
2263 | 0x6000 0 0 2 &PIC 93 | |
2264 | 0x6000 0 0 3 &PIC 80 | |
2265 | 0x6000 0 0 4 &PIC 81 | |
2266 | ||
2267 | /* IDSEL 0x0d */ | |
2268 | 0x6800 0 0 1 &PIC 93 | |
2269 | 0x6800 0 0 2 &PIC 80 | |
2270 | 0x6800 0 0 3 &PIC 81 | |
2271 | 0x6800 0 0 4 &PIC 91 | |
2272 | >; | |
2273 | }; | |
2274 | ||
2275 | ||
2276 | p) Marvell Discovery CPU Error nodes | |
2277 | ||
2278 | Represent the Discovery's CPU error handler device. | |
2279 | ||
2280 | Required properties: | |
2281 | - compatible : "marvell,mv64360-cpu-error" | |
2282 | - reg : Offset and length of the register set for this device | |
2283 | - interrupts : the interrupt number for this device | |
2284 | - interrupt-parent : the phandle for the interrupt controller | |
2285 | that services interrupts for this device. | |
2286 | ||
2287 | Example Discovery CPU Error node: | |
2288 | cpu-error@0070 { | |
2289 | compatible = "marvell,mv64360-cpu-error"; | |
2290 | reg = <0x70 0x10 0x128 0x28>; | |
2291 | interrupts = <3>; | |
2292 | interrupt-parent = <&PIC>; | |
2293 | }; | |
2294 | ||
2295 | ||
2296 | q) Marvell Discovery SRAM Controller nodes | |
2297 | ||
2298 | Represent the Discovery's SRAM controller device. | |
2299 | ||
2300 | Required properties: | |
2301 | - compatible : "marvell,mv64360-sram-ctrl" | |
2302 | - reg : Offset and length of the register set for this device | |
2303 | - interrupts : the interrupt number for this device | |
2304 | - interrupt-parent : the phandle for the interrupt controller | |
2305 | that services interrupts for this device. | |
2306 | ||
2307 | Example Discovery SRAM Controller node: | |
2308 | sram-ctrl@0380 { | |
2309 | compatible = "marvell,mv64360-sram-ctrl"; | |
2310 | reg = <0x380 0x80>; | |
2311 | interrupts = <13>; | |
2312 | interrupt-parent = <&PIC>; | |
2313 | }; | |
2314 | ||
2315 | ||
2316 | r) Marvell Discovery PCI Error Handler nodes | |
2317 | ||
2318 | Represent the Discovery's PCI error handler device. | |
2319 | ||
2320 | Required properties: | |
2321 | - compatible : "marvell,mv64360-pci-error" | |
2322 | - reg : Offset and length of the register set for this device | |
2323 | - interrupts : the interrupt number for this device | |
2324 | - interrupt-parent : the phandle for the interrupt controller | |
2325 | that services interrupts for this device. | |
2326 | ||
2327 | Example Discovery PCI Error Handler node: | |
2328 | pci-error@1d40 { | |
2329 | compatible = "marvell,mv64360-pci-error"; | |
2330 | reg = <0x1d40 0x40 0xc28 0x4>; | |
2331 | interrupts = <12>; | |
2332 | interrupt-parent = <&PIC>; | |
2333 | }; | |
2334 | ||
2335 | ||
2336 | s) Marvell Discovery Memory Controller nodes | |
2337 | ||
2338 | Represent the Discovery's memory controller device. | |
2339 | ||
2340 | Required properties: | |
2341 | - compatible : "marvell,mv64360-mem-ctrl" | |
2342 | - reg : Offset and length of the register set for this device | |
2343 | - interrupts : the interrupt number for this device | |
2344 | - interrupt-parent : the phandle for the interrupt controller | |
2345 | that services interrupts for this device. | |
2346 | ||
2347 | Example Discovery Memory Controller node: | |
2348 | mem-ctrl@1400 { | |
2349 | compatible = "marvell,mv64360-mem-ctrl"; | |
2350 | reg = <0x1400 0x60>; | |
2351 | interrupts = <17>; | |
2352 | interrupt-parent = <&PIC>; | |
2353 | }; | |
2354 | ||
2355 | ||
2356 | VIII - Specifying interrupt information for devices | |
27565903 SY |
2357 | =================================================== |
2358 | ||
2359 | The device tree represents the busses and devices of a hardware | |
2360 | system in a form similar to the physical bus topology of the | |
2361 | hardware. | |
2362 | ||
2363 | In addition, a logical 'interrupt tree' exists which represents the | |
2364 | hierarchy and routing of interrupts in the hardware. | |
2365 | ||
2366 | The interrupt tree model is fully described in the | |
2367 | document "Open Firmware Recommended Practice: Interrupt | |
2368 | Mapping Version 0.9". The document is available at: | |
2369 | <http://playground.sun.com/1275/practice>. | |
2370 | ||
2371 | 1) interrupts property | |
2372 | ---------------------- | |
2373 | ||
2374 | Devices that generate interrupts to a single interrupt controller | |
2375 | should use the conventional OF representation described in the | |
2376 | OF interrupt mapping documentation. | |
2377 | ||
2378 | Each device which generates interrupts must have an 'interrupt' | |
2379 | property. The interrupt property value is an arbitrary number of | |
2380 | of 'interrupt specifier' values which describe the interrupt or | |
2381 | interrupts for the device. | |
2382 | ||
2383 | The encoding of an interrupt specifier is determined by the | |
2384 | interrupt domain in which the device is located in the | |
2385 | interrupt tree. The root of an interrupt domain specifies in | |
2386 | its #interrupt-cells property the number of 32-bit cells | |
2387 | required to encode an interrupt specifier. See the OF interrupt | |
2388 | mapping documentation for a detailed description of domains. | |
2389 | ||
2390 | For example, the binding for the OpenPIC interrupt controller | |
2391 | specifies an #interrupt-cells value of 2 to encode the interrupt | |
2392 | number and level/sense information. All interrupt children in an | |
2393 | OpenPIC interrupt domain use 2 cells per interrupt in their interrupts | |
2394 | property. | |
2395 | ||
2396 | The PCI bus binding specifies a #interrupt-cell value of 1 to encode | |
2397 | which interrupt pin (INTA,INTB,INTC,INTD) is used. | |
2398 | ||
2399 | 2) interrupt-parent property | |
2400 | ---------------------------- | |
2401 | ||
2402 | The interrupt-parent property is specified to define an explicit | |
2403 | link between a device node and its interrupt parent in | |
2404 | the interrupt tree. The value of interrupt-parent is the | |
2405 | phandle of the parent node. | |
2406 | ||
2407 | If the interrupt-parent property is not defined for a node, it's | |
2408 | interrupt parent is assumed to be an ancestor in the node's | |
2409 | _device tree_ hierarchy. | |
2410 | ||
2411 | 3) OpenPIC Interrupt Controllers | |
2412 | -------------------------------- | |
2413 | ||
2414 | OpenPIC interrupt controllers require 2 cells to encode | |
2415 | interrupt information. The first cell defines the interrupt | |
2416 | number. The second cell defines the sense and level | |
2417 | information. | |
2418 | ||
2419 | Sense and level information should be encoded as follows: | |
2420 | ||
2421 | 0 = low to high edge sensitive type enabled | |
2422 | 1 = active low level sensitive type enabled | |
2423 | 2 = active high level sensitive type enabled | |
2424 | 3 = high to low edge sensitive type enabled | |
2425 | ||
2426 | 4) ISA Interrupt Controllers | |
2427 | ---------------------------- | |
2428 | ||
2429 | ISA PIC interrupt controllers require 2 cells to encode | |
2430 | interrupt information. The first cell defines the interrupt | |
2431 | number. The second cell defines the sense and level | |
2432 | information. | |
2433 | ||
2434 | ISA PIC interrupt controllers should adhere to the ISA PIC | |
2435 | encodings listed below: | |
2436 | ||
2437 | 0 = active low level sensitive type enabled | |
2438 | 1 = active high level sensitive type enabled | |
2439 | 2 = high to low edge sensitive type enabled | |
2440 | 3 = low to high edge sensitive type enabled | |
2441 | ||
2dff4177 SW |
2442 | IX - Specifying GPIO information for devices |
2443 | ============================================ | |
b7ce3415 AV |
2444 | |
2445 | 1) gpios property | |
2446 | ----------------- | |
2447 | ||
2448 | Nodes that makes use of GPIOs should define them using `gpios' property, | |
2449 | format of which is: <&gpio-controller1-phandle gpio1-specifier | |
2450 | &gpio-controller2-phandle gpio2-specifier | |
2451 | 0 /* holes are permitted, means no GPIO 3 */ | |
2452 | &gpio-controller4-phandle gpio4-specifier | |
2453 | ...>; | |
2454 | ||
2455 | Note that gpio-specifier length is controller dependent. | |
2456 | ||
2457 | gpio-specifier may encode: bank, pin position inside the bank, | |
2458 | whether pin is open-drain and whether pin is logically inverted. | |
2459 | ||
2460 | Example of the node using GPIOs: | |
2461 | ||
2462 | node { | |
2463 | gpios = <&qe_pio_e 18 0>; | |
2464 | }; | |
2465 | ||
2466 | In this example gpio-specifier is "18 0" and encodes GPIO pin number, | |
2467 | and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller. | |
2468 | ||
2469 | 2) gpio-controller nodes | |
2470 | ------------------------ | |
2471 | ||
2472 | Every GPIO controller node must have #gpio-cells property defined, | |
2473 | this information will be used to translate gpio-specifiers. | |
2474 | ||
2475 | Example of two SOC GPIO banks defined as gpio-controller nodes: | |
2476 | ||
2477 | qe_pio_a: gpio-controller@1400 { | |
2478 | #gpio-cells = <2>; | |
2479 | compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; | |
2480 | reg = <0x1400 0x18>; | |
2481 | gpio-controller; | |
2482 | }; | |
2483 | ||
2484 | qe_pio_e: gpio-controller@1460 { | |
2485 | #gpio-cells = <2>; | |
2486 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; | |
2487 | reg = <0x1460 0x18>; | |
2488 | gpio-controller; | |
2489 | }; | |
c125a183 | 2490 | |
2dff4177 SW |
2491 | X - Specifying Device Power Management Information (sleep property) |
2492 | =================================================================== | |
2493 | ||
2494 | Devices on SOCs often have mechanisms for placing devices into low-power | |
2495 | states that are decoupled from the devices' own register blocks. Sometimes, | |
2496 | this information is more complicated than a cell-index property can | |
2497 | reasonably describe. Thus, each device controlled in such a manner | |
2498 | may contain a "sleep" property which describes these connections. | |
2499 | ||
2500 | The sleep property consists of one or more sleep resources, each of | |
2501 | which consists of a phandle to a sleep controller, followed by a | |
2502 | controller-specific sleep specifier of zero or more cells. | |
2503 | ||
2504 | The semantics of what type of low power modes are possible are defined | |
2505 | by the sleep controller. Some examples of the types of low power modes | |
2506 | that may be supported are: | |
2507 | ||
2508 | - Dynamic: The device may be disabled or enabled at any time. | |
2509 | - System Suspend: The device may request to be disabled or remain | |
2510 | awake during system suspend, but will not be disabled until then. | |
2511 | - Permanent: The device is disabled permanently (until the next hard | |
2512 | reset). | |
2513 | ||
2514 | Some devices may share a clock domain with each other, such that they should | |
2515 | only be suspended when none of the devices are in use. Where reasonable, | |
2516 | such nodes should be placed on a virtual bus, where the bus has the sleep | |
2517 | property. If the clock domain is shared among devices that cannot be | |
2518 | reasonably grouped in this manner, then create a virtual sleep controller | |
2519 | (similar to an interrupt nexus, except that defining a standardized | |
2520 | sleep-map should wait until its necessity is demonstrated). | |
2521 | ||
c125a183 DG |
2522 | Appendix A - Sample SOC node for MPC8540 |
2523 | ======================================== | |
2524 | ||
7e72063c | 2525 | soc@e0000000 { |
c125a183 DG |
2526 | #address-cells = <1>; |
2527 | #size-cells = <1>; | |
7e72063c | 2528 | compatible = "fsl,mpc8540-ccsr", "simple-bus"; |
c125a183 | 2529 | device_type = "soc"; |
7e72063c | 2530 | ranges = <0x00000000 0xe0000000 0x00100000> |
7d4b95ae | 2531 | bus-frequency = <0>; |
7e72063c | 2532 | interrupt-parent = <&pic>; |
c125a183 | 2533 | |
c125a183 | 2534 | ethernet@24000 { |
2dff4177 SW |
2535 | #address-cells = <1>; |
2536 | #size-cells = <1>; | |
c125a183 DG |
2537 | device_type = "network"; |
2538 | model = "TSEC"; | |
2dff4177 | 2539 | compatible = "gianfar", "simple-bus"; |
7e72063c SW |
2540 | reg = <0x24000 0x1000>; |
2541 | local-mac-address = [ 00 E0 0C 00 73 00 ]; | |
2542 | interrupts = <29 2 30 2 34 2>; | |
2543 | phy-handle = <&phy0>; | |
2dff4177 SW |
2544 | sleep = <&pmc 00000080>; |
2545 | ranges; | |
2546 | ||
2547 | mdio@24520 { | |
7e72063c | 2548 | reg = <0x24520 0x20>; |
2dff4177 SW |
2549 | compatible = "fsl,gianfar-mdio"; |
2550 | ||
7e72063c SW |
2551 | phy0: ethernet-phy@0 { |
2552 | interrupts = <5 1>; | |
2dff4177 SW |
2553 | reg = <0>; |
2554 | device_type = "ethernet-phy"; | |
2555 | }; | |
2556 | ||
7e72063c SW |
2557 | phy1: ethernet-phy@1 { |
2558 | interrupts = <5 1>; | |
2dff4177 SW |
2559 | reg = <1>; |
2560 | device_type = "ethernet-phy"; | |
2561 | }; | |
2562 | ||
7e72063c SW |
2563 | phy3: ethernet-phy@3 { |
2564 | interrupts = <7 1>; | |
2dff4177 SW |
2565 | reg = <3>; |
2566 | device_type = "ethernet-phy"; | |
2567 | }; | |
2568 | }; | |
c125a183 DG |
2569 | }; |
2570 | ||
2571 | ethernet@25000 { | |
c125a183 DG |
2572 | device_type = "network"; |
2573 | model = "TSEC"; | |
2574 | compatible = "gianfar"; | |
7e72063c SW |
2575 | reg = <0x25000 0x1000>; |
2576 | local-mac-address = [ 00 E0 0C 00 73 01 ]; | |
2577 | interrupts = <13 2 14 2 18 2>; | |
2578 | phy-handle = <&phy1>; | |
2dff4177 | 2579 | sleep = <&pmc 00000040>; |
c125a183 DG |
2580 | }; |
2581 | ||
2582 | ethernet@26000 { | |
c125a183 DG |
2583 | device_type = "network"; |
2584 | model = "FEC"; | |
2585 | compatible = "gianfar"; | |
7e72063c SW |
2586 | reg = <0x26000 0x1000>; |
2587 | local-mac-address = [ 00 E0 0C 00 73 02 ]; | |
2588 | interrupts = <41 2>; | |
2589 | phy-handle = <&phy3>; | |
2dff4177 | 2590 | sleep = <&pmc 00000020>; |
c125a183 DG |
2591 | }; |
2592 | ||
2593 | serial@4500 { | |
2dff4177 SW |
2594 | #address-cells = <1>; |
2595 | #size-cells = <1>; | |
2596 | compatible = "fsl,mpc8540-duart", "simple-bus"; | |
2597 | sleep = <&pmc 00000002>; | |
2598 | ranges; | |
2599 | ||
2600 | serial@4500 { | |
2601 | device_type = "serial"; | |
2602 | compatible = "ns16550"; | |
7e72063c | 2603 | reg = <0x4500 0x100>; |
2dff4177 | 2604 | clock-frequency = <0>; |
7e72063c | 2605 | interrupts = <42 2>; |
2dff4177 SW |
2606 | }; |
2607 | ||
2608 | serial@4600 { | |
2609 | device_type = "serial"; | |
2610 | compatible = "ns16550"; | |
7e72063c | 2611 | reg = <0x4600 0x100>; |
2dff4177 | 2612 | clock-frequency = <0>; |
7e72063c | 2613 | interrupts = <42 2>; |
2dff4177 | 2614 | }; |
c125a183 DG |
2615 | }; |
2616 | ||
7e72063c | 2617 | pic: pic@40000 { |
c125a183 DG |
2618 | interrupt-controller; |
2619 | #address-cells = <0>; | |
7e72063c SW |
2620 | #interrupt-cells = <2>; |
2621 | reg = <0x40000 0x40000>; | |
c125a183 DG |
2622 | compatible = "chrp,open-pic"; |
2623 | device_type = "open-pic"; | |
c125a183 DG |
2624 | }; |
2625 | ||
2626 | i2c@3000 { | |
7e72063c SW |
2627 | interrupts = <43 2>; |
2628 | reg = <0x3000 0x100>; | |
c125a183 DG |
2629 | compatible = "fsl-i2c"; |
2630 | dfsrr; | |
2dff4177 | 2631 | sleep = <&pmc 00000004>; |
c125a183 DG |
2632 | }; |
2633 | ||
2dff4177 SW |
2634 | pmc: power@e0070 { |
2635 | compatible = "fsl,mpc8540-pmc", "fsl,mpc8548-pmc"; | |
7e72063c | 2636 | reg = <0xe0070 0x20>; |
2dff4177 | 2637 | }; |
c125a183 | 2638 | }; |