[mirror_ubuntu-bionic-kernel.git] / Documentation / sound / soc / clocking.rst

==============
Audio Clocking
==============

This text describes the audio clocking terms in ASoC and digital audio in
general. Note: Audio clocking can be complex!


Master Clock
------------

Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
or SYSCLK). This audio master clock can be derived from a number of sources
(e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
audio playback and capture sample rates.

Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
their speed can be altered by software (depending on the system use and to save
power). Other master clocks are fixed at a set frequency (i.e. crystals).


DAI Clocks
----------
The Digital Audio Interface is usually driven by a Bit Clock (often referred to
as BCLK). This clock is used to drive the digital audio data across the link
between the codec and CPU.

The DAI also has a frame clock to signal the start of each audio frame. This
clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
runs at exactly the sample rate (LRC = Rate).

Bit Clock can be generated as follows:-

- BCLK = MCLK / x, or
- BCLK = LRC * x, or
- BCLK = LRC * Channels * Word Size

This relationship depends on the codec or SoC CPU in particular. In general
it is best to configure BCLK to the lowest possible speed (depending on your
rate, number of channels and word size) to save on power.

It is also desirable to use the codec (if possible) to drive (or master) the
audio clocks as it usually gives more accurate sample rates than the CPU.
Commit	Line	Data
fb3df950	1	==============
eb1a6af3 LG	2	Audio Clocking
	3	==============
	4
	5	This text describes the audio clocking terms in ASoC and digital audio in
01dd2fbf	6	general. Note: Audio clocking can be complex!
eb1a6af3 LG	7
	8
	9	Master Clock
	10	------------
	11
01dd2fbf	12	Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
eb1a6af3 LG	13	or SYSCLK). This audio master clock can be derived from a number of sources
	14	(e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
	15	audio playback and capture sample rates.
	16
7c4dbbd8	17	Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
eb1a6af3	18	their speed can be altered by software (depending on the system use and to save
01dd2fbf	19	power). Other master clocks are fixed at a set frequency (i.e. crystals).
eb1a6af3 LG	20
	21
	22	DAI Clocks
	23	----------
	24	The Digital Audio Interface is usually driven by a Bit Clock (often referred to
	25	as BCLK). This clock is used to drive the digital audio data across the link
	26	between the codec and CPU.
	27
	28	The DAI also has a frame clock to signal the start of each audio frame. This
	29	clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
a71a468a	30	runs at exactly the sample rate (LRC = Rate).
eb1a6af3	31
a71a468a	32	Bit Clock can be generated as follows:-
eb1a6af3	33
fb3df950 TI	34	- BCLK = MCLK / x, or
	35	- BCLK = LRC * x, or
	36	- BCLK = LRC * Channels * Word Size
a71a468a	37
10b98527	38	This relationship depends on the codec or SoC CPU in particular. In general
7c4dbbd8 MB	39	it is best to configure BCLK to the lowest possible speed (depending on your
7c4dbbd8 MB	40	rate, number of channels and word size) to save on power.
eb1a6af3	41
7c4dbbd8 MB	42	It is also desirable to use the codec (if possible) to drive (or master) the
7c4dbbd8 MB	43	audio clocks as it usually gives more accurate sample rates than the CPU.
eb1a6af3	44
eb1a6af3	45
eb1a6af3	46