[mirror_ubuntu-kernels.git] / Documentation / xtensa / atomctl.rst

===========================================
Atomic Operation Control (ATOMCTL) Register
===========================================

We Have Atomic Operation Control (ATOMCTL) Register.
This register determines the effect of using a S32C1I instruction
with various combinations of:

     1. With and without an Coherent Cache Controller which
        can do Atomic Transactions to the memory internally.

     2. With and without An Intelligent Memory Controller which
        can do Atomic Transactions itself.

The Core comes up with a default value of for the three types of cache ops::

      0x28: (WB: Internal, WT: Internal, BY:Exception)

On the FPGA Cards we typically simulate an Intelligent Memory controller
which can implement  RCW transactions. For FPGA cards with an External
Memory controller we let it to the atomic operations internally while
doing a Cached (WB) transaction and use the Memory RCW for un-cached
operations.

For systems without an coherent cache controller, non-MX, we always
use the memory controllers RCW, thought non-MX controlers likely
support the Internal Operation.

CUSTOMER-WARNING:
   Virtually all customers buy their memory controllers from vendors that
   don't support atomic RCW memory transactions and will likely want to
   configure this register to not use RCW.

Developers might find using RCW in Bypass mode convenient when testing
with the cache being bypassed; for example studying cache alias problems.

See Section 4.3.12.4 of ISA; Bits::

                             WB     WT      BY
                           5   4 | 3   2 | 1   0

=========    ==================      ==================      ===============
  2 Bit
  Field
  Values     WB - Write Back         WT - Write Thru         BY - Bypass
=========    ==================      ==================      ===============
    0        Exception               Exception               Exception
    1        RCW Transaction         RCW Transaction         RCW Transaction
    2        Internal Operation      Internal Operation      Reserved
    3        Reserved                Reserved                Reserved
=========    ==================      ==================      ===============
Commit	Line	Data
8ea0afa3 MCC	1	===========================================
	2	Atomic Operation Control (ATOMCTL) Register
	3	===========================================
	4
c622b29d MF	5	We Have Atomic Operation Control (ATOMCTL) Register.
	6	This register determines the effect of using a S32C1I instruction
	7	with various combinations of:
	8
	9	1. With and without an Coherent Cache Controller which
	10	can do Atomic Transactions to the memory internally.
	11
	12	2. With and without An Intelligent Memory Controller which
	13	can do Atomic Transactions itself.
	14
8ea0afa3	15	The Core comes up with a default value of for the three types of cache ops::
c622b29d MF	16
	17	0x28: (WB: Internal, WT: Internal, BY:Exception)
	18
	19	On the FPGA Cards we typically simulate an Intelligent Memory controller
	20	which can implement RCW transactions. For FPGA cards with an External
	21	Memory controller we let it to the atomic operations internally while
	22	doing a Cached (WB) transaction and use the Memory RCW for un-cached
	23	operations.
	24
	25	For systems without an coherent cache controller, non-MX, we always
	26	use the memory controllers RCW, thought non-MX controlers likely
	27	support the Internal Operation.
	28
	29	CUSTOMER-WARNING:
	30	Virtually all customers buy their memory controllers from vendors that
	31	don't support atomic RCW memory transactions and will likely want to
	32	configure this register to not use RCW.
	33
	34	Developers might find using RCW in Bypass mode convenient when testing
	35	with the cache being bypassed; for example studying cache alias problems.
	36
8ea0afa3	37	See Section 4.3.12.4 of ISA; Bits::
c622b29d MF	38
	39	WB WT BY
	40	5 4 \| 3 2 \| 1 0
8ea0afa3 MCC	41
8ea0afa3 MCC	42	========= ================== ================== ===============
c622b29d MF	43	2 Bit
	44	Field
	45	Values WB - Write Back WT - Write Thru BY - Bypass
8ea0afa3	46	========= ================== ================== ===============
c622b29d MF	47	0 Exception Exception Exception
c622b29d MF	48	1 RCW Transaction RCW Transaction RCW Transaction
5f42146e	49	2 Internal Operation Internal Operation Reserved
c622b29d	50	3 Reserved Reserved Reserved
8ea0afa3	51	========= ================== ================== ===============