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Commit | Line | Data |
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8ea0afa3 MCC |
1 | ============================= |
2 | MMUv3 initialization sequence | |
3 | ============================= | |
4 | ||
5 | The code in the initialize_mmu macro sets up MMUv3 memory mapping | |
6 | identically to MMUv2 fixed memory mapping. Depending on | |
7 | CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is | |
8 | located in addresses it was linked for (symbol undefined), or not | |
9 | (symbol defined), so it needs to be position-independent. | |
10 | ||
11 | The code has the following assumptions: | |
12 | ||
13 | - This code fragment is run only on an MMU v3. | |
14 | - TLBs are in their reset state. | |
15 | - ITLBCFG and DTLBCFG are zero (reset state). | |
16 | - RASID is 0x04030201 (reset state). | |
17 | - PS.RING is zero (reset state). | |
18 | - LITBASE is zero (reset state, PC-relative literals); required to be PIC. | |
19 | ||
20 | TLB setup proceeds along the following steps. | |
21 | ||
22 | Legend: | |
23 | ||
24 | - VA = virtual address (two upper nibbles of it); | |
25 | - PA = physical address (two upper nibbles of it); | |
26 | - pc = physical range that contains this code; | |
27 | ||
28 | After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff | |
29 | or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below | |
30 | 0x40000000 or above. That address corresponds to next instruction to execute | |
31 | in this code. After step 4, we jump to intended (linked) address of this code. | |
32 | The scheme below assumes that the kernel is loaded below 0x40000000. | |
33 | ||
34 | ====== ===== ===== ===== ===== ====== ===== ===== | |
35 | - Step0 Step1 Step2 Step3 Step4 Step5 | |
36 | ||
37 | VA PA PA PA PA VA PA PA | |
38 | ====== ===== ===== ===== ===== ====== ===== ===== | |
39 | E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0 | |
40 | C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0 | |
41 | A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00 | |
42 | 80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00 | |
43 | 60..7F -> 60 -> 60 -> 60 | |
44 | 40..5F -> 40 -> pc -> pc 40..5F -> pc | |
45 | 20..3F -> 20 -> 20 -> 20 | |
46 | 00..1F -> 00 -> 00 -> 00 | |
47 | ====== ===== ===== ===== ===== ====== ===== ===== | |
48 | ||
49 | The default location of IO peripherals is above 0xf0000000. This may be changed | |
50 | using a "ranges" property in a device tree simple-bus node. See the Devicetree | |
51 | Specification, section 4.5 for details on the syntax and semantics of | |
52 | simple-bus nodes. The following limitations apply: | |
53 | ||
54 | 1. Only top level simple-bus nodes are considered | |
55 | ||
56 | 2. Only one (first) simple-bus node is considered | |
57 | ||
58 | 3. Empty "ranges" properties are not supported | |
59 | ||
60 | 4. Only the first triplet in the "ranges" property is considered | |
61 | ||
62 | 5. The parent-bus-address value is rounded down to the nearest 256MB boundary | |
63 | ||
64 | 6. The IO area covers the entire 256MB segment of parent-bus-address; the | |
65 | "ranges" triplet length field is ignored | |
66 | ||
67 | ||
68 | MMUv3 address space layouts. | |
69 | ============================ | |
70 | ||
71 | Default MMUv2-compatible layout:: | |
72 | ||
73 | Symbol VADDR Size | |
74 | +------------------+ | |
75 | | Userspace | 0x00000000 TASK_SIZE | |
76 | +------------------+ 0x40000000 | |
77 | +------------------+ | |
78 | | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE | |
79 | +------------------+ | |
80 | | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE | |
81 | +------------------+ 0x8e400000 | |
82 | +------------------+ | |
83 | | VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB | |
84 | +------------------+ VMALLOC_END | |
481535c5 MF |
85 | +------------------+ |
86 | | Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE | |
8ea0afa3 MCC |
87 | | remap area 1 | |
88 | +------------------+ | |
89 | | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE | |
90 | | remap area 2 | | |
91 | +------------------+ | |
92 | +------------------+ | |
93 | | KMAP area | PKMAP_BASE PTRS_PER_PTE * | |
94 | | | DCACHE_N_COLORS * | |
95 | | | PAGE_SIZE | |
96 | | | (4MB * DCACHE_N_COLORS) | |
97 | +------------------+ | |
98 | | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * | |
99 | | | NR_CPUS * | |
100 | | | DCACHE_N_COLORS * | |
101 | | | PAGE_SIZE | |
102 | +------------------+ FIXADDR_TOP 0xcffff000 | |
103 | +------------------+ | |
104 | | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB | |
105 | +------------------+ | |
106 | | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB | |
107 | +------------------+ | |
108 | | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB | |
109 | +------------------+ | |
110 | | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB | |
111 | +------------------+ | |
112 | ||
113 | ||
114 | 256MB cached + 256MB uncached layout:: | |
115 | ||
116 | Symbol VADDR Size | |
117 | +------------------+ | |
118 | | Userspace | 0x00000000 TASK_SIZE | |
119 | +------------------+ 0x40000000 | |
120 | +------------------+ | |
121 | | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE | |
122 | +------------------+ | |
123 | | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE | |
124 | +------------------+ 0x8e400000 | |
125 | +------------------+ | |
126 | | VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB | |
127 | +------------------+ VMALLOC_END | |
481535c5 MF |
128 | +------------------+ |
129 | | Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE | |
8ea0afa3 MCC |
130 | | remap area 1 | |
131 | +------------------+ | |
132 | | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE | |
133 | | remap area 2 | | |
134 | +------------------+ | |
135 | +------------------+ | |
136 | | KMAP area | PKMAP_BASE PTRS_PER_PTE * | |
137 | | | DCACHE_N_COLORS * | |
138 | | | PAGE_SIZE | |
139 | | | (4MB * DCACHE_N_COLORS) | |
140 | +------------------+ | |
141 | | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * | |
142 | | | NR_CPUS * | |
143 | | | DCACHE_N_COLORS * | |
144 | | | PAGE_SIZE | |
145 | +------------------+ FIXADDR_TOP 0xaffff000 | |
146 | +------------------+ | |
147 | | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB | |
148 | +------------------+ | |
149 | | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB | |
150 | +------------------+ | |
151 | +------------------+ | |
152 | | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB | |
153 | +------------------+ | |
154 | | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB | |
155 | +------------------+ | |
156 | ||
157 | ||
158 | 512MB cached + 512MB uncached layout:: | |
159 | ||
160 | Symbol VADDR Size | |
161 | +------------------+ | |
162 | | Userspace | 0x00000000 TASK_SIZE | |
163 | +------------------+ 0x40000000 | |
164 | +------------------+ | |
165 | | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE | |
166 | +------------------+ | |
167 | | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE | |
168 | +------------------+ 0x8e400000 | |
169 | +------------------+ | |
170 | | VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB | |
171 | +------------------+ VMALLOC_END | |
481535c5 MF |
172 | +------------------+ |
173 | | Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE | |
8ea0afa3 MCC |
174 | | remap area 1 | |
175 | +------------------+ | |
176 | | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE | |
177 | | remap area 2 | | |
178 | +------------------+ | |
179 | +------------------+ | |
180 | | KMAP area | PKMAP_BASE PTRS_PER_PTE * | |
181 | | | DCACHE_N_COLORS * | |
182 | | | PAGE_SIZE | |
183 | | | (4MB * DCACHE_N_COLORS) | |
184 | +------------------+ | |
185 | | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * | |
186 | | | NR_CPUS * | |
187 | | | DCACHE_N_COLORS * | |
188 | | | PAGE_SIZE | |
189 | +------------------+ FIXADDR_TOP 0x9ffff000 | |
190 | +------------------+ | |
191 | | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB | |
192 | +------------------+ | |
193 | | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB | |
194 | +------------------+ | |
195 | | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB | |
196 | +------------------+ | |
197 | | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB | |
198 | +------------------+ |