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Commit | Line | Data |
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7d13299d | 1 | /* |
e965fc38 | 2 | * emulator main execution loop |
5fafdf24 | 3 | * |
66321a11 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
7d13299d | 5 | * |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
fb0343d5 | 9 | * version 2.1 of the License, or (at your option) any later version. |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 | 16 | * You should have received a copy of the GNU Lesser General Public |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
7d13299d | 18 | */ |
a8d25326 | 19 | |
7b31bbc2 | 20 | #include "qemu/osdep.h" |
a8d25326 | 21 | #include "qemu-common.h" |
740b1759 | 22 | #include "qemu/qemu-print.h" |
cea5f9a2 | 23 | #include "cpu.h" |
d9bb58e5 | 24 | #include "trace.h" |
76cad711 | 25 | #include "disas/disas.h" |
63c91552 | 26 | #include "exec/exec-all.h" |
dcb32f1d | 27 | #include "tcg/tcg.h" |
1de7afc9 | 28 | #include "qemu/atomic.h" |
9c17d615 | 29 | #include "sysemu/qtest.h" |
c2aa5f81 | 30 | #include "qemu/timer.h" |
79e2b9ae | 31 | #include "qemu/rcu.h" |
e1b89321 | 32 | #include "exec/tb-hash.h" |
f6bb84d5 | 33 | #include "exec/tb-lookup.h" |
508127e2 | 34 | #include "exec/log.h" |
8d04fb55 | 35 | #include "qemu/main-loop.h" |
6220e900 PD |
36 | #if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) |
37 | #include "hw/i386/apic.h" | |
38 | #endif | |
d2528bdc | 39 | #include "sysemu/cpus.h" |
740b1759 CF |
40 | #include "exec/cpu-all.h" |
41 | #include "sysemu/cpu-timers.h" | |
6f060969 | 42 | #include "sysemu/replay.h" |
c2aa5f81 ST |
43 | |
44 | /* -icount align implementation. */ | |
45 | ||
46 | typedef struct SyncClocks { | |
47 | int64_t diff_clk; | |
48 | int64_t last_cpu_icount; | |
7f7bc144 | 49 | int64_t realtime_clock; |
c2aa5f81 ST |
50 | } SyncClocks; |
51 | ||
52 | #if !defined(CONFIG_USER_ONLY) | |
53 | /* Allow the guest to have a max 3ms advance. | |
54 | * The difference between the 2 clocks could therefore | |
55 | * oscillate around 0. | |
56 | */ | |
57 | #define VM_CLOCK_ADVANCE 3000000 | |
7f7bc144 ST |
58 | #define THRESHOLD_REDUCE 1.5 |
59 | #define MAX_DELAY_PRINT_RATE 2000000000LL | |
60 | #define MAX_NB_PRINTS 100 | |
c2aa5f81 | 61 | |
740b1759 CF |
62 | static int64_t max_delay; |
63 | static int64_t max_advance; | |
64 | ||
5e140196 | 65 | static void align_clocks(SyncClocks *sc, CPUState *cpu) |
c2aa5f81 ST |
66 | { |
67 | int64_t cpu_icount; | |
68 | ||
69 | if (!icount_align_option) { | |
70 | return; | |
71 | } | |
72 | ||
5e140196 | 73 | cpu_icount = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; |
8191d368 | 74 | sc->diff_clk += icount_to_ns(sc->last_cpu_icount - cpu_icount); |
c2aa5f81 ST |
75 | sc->last_cpu_icount = cpu_icount; |
76 | ||
77 | if (sc->diff_clk > VM_CLOCK_ADVANCE) { | |
78 | #ifndef _WIN32 | |
79 | struct timespec sleep_delay, rem_delay; | |
80 | sleep_delay.tv_sec = sc->diff_clk / 1000000000LL; | |
81 | sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL; | |
82 | if (nanosleep(&sleep_delay, &rem_delay) < 0) { | |
a498d0ef | 83 | sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec; |
c2aa5f81 ST |
84 | } else { |
85 | sc->diff_clk = 0; | |
86 | } | |
87 | #else | |
88 | Sleep(sc->diff_clk / SCALE_MS); | |
89 | sc->diff_clk = 0; | |
90 | #endif | |
91 | } | |
92 | } | |
93 | ||
7f7bc144 ST |
94 | static void print_delay(const SyncClocks *sc) |
95 | { | |
96 | static float threshold_delay; | |
97 | static int64_t last_realtime_clock; | |
98 | static int nb_prints; | |
99 | ||
100 | if (icount_align_option && | |
101 | sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE && | |
102 | nb_prints < MAX_NB_PRINTS) { | |
103 | if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) || | |
104 | (-sc->diff_clk / (float)1000000000LL < | |
105 | (threshold_delay - THRESHOLD_REDUCE))) { | |
106 | threshold_delay = (-sc->diff_clk / 1000000000LL) + 1; | |
740b1759 CF |
107 | qemu_printf("Warning: The guest is now late by %.1f to %.1f seconds\n", |
108 | threshold_delay - 1, | |
109 | threshold_delay); | |
7f7bc144 ST |
110 | nb_prints++; |
111 | last_realtime_clock = sc->realtime_clock; | |
112 | } | |
113 | } | |
114 | } | |
115 | ||
5e140196 | 116 | static void init_delay_params(SyncClocks *sc, CPUState *cpu) |
c2aa5f81 ST |
117 | { |
118 | if (!icount_align_option) { | |
119 | return; | |
120 | } | |
2e91cc62 PB |
121 | sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); |
122 | sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock; | |
5e140196 RH |
123 | sc->last_cpu_icount |
124 | = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; | |
27498bef ST |
125 | if (sc->diff_clk < max_delay) { |
126 | max_delay = sc->diff_clk; | |
127 | } | |
128 | if (sc->diff_clk > max_advance) { | |
129 | max_advance = sc->diff_clk; | |
130 | } | |
7f7bc144 ST |
131 | |
132 | /* Print every 2s max if the guest is late. We limit the number | |
133 | of printed messages to NB_PRINT_MAX(currently 100) */ | |
134 | print_delay(sc); | |
c2aa5f81 ST |
135 | } |
136 | #else | |
137 | static void align_clocks(SyncClocks *sc, const CPUState *cpu) | |
138 | { | |
139 | } | |
140 | ||
141 | static void init_delay_params(SyncClocks *sc, const CPUState *cpu) | |
142 | { | |
143 | } | |
144 | #endif /* CONFIG USER ONLY */ | |
7d13299d | 145 | |
77211379 | 146 | /* Execute a TB, and fix up the CPU state afterwards if necessary */ |
1a830635 | 147 | static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) |
77211379 PM |
148 | { |
149 | CPUArchState *env = cpu->env_ptr; | |
819af24b SF |
150 | uintptr_t ret; |
151 | TranslationBlock *last_tb; | |
152 | int tb_exit; | |
e7e168f4 | 153 | uint8_t *tb_ptr = itb->tc.ptr; |
1a830635 | 154 | |
d977e1c2 | 155 | qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, |
4fad446b PB |
156 | "Trace %d: %p [" |
157 | TARGET_FMT_lx "/" TARGET_FMT_lx "/%#x] %s\n", | |
158 | cpu->cpu_index, itb->tc.ptr, | |
159 | itb->cs_base, itb->pc, itb->flags, | |
4426f83a | 160 | lookup_symbol(itb->pc)); |
03afa5f8 RH |
161 | |
162 | #if defined(DEBUG_DISAS) | |
be2208e2 RH |
163 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU) |
164 | && qemu_log_in_addr_range(itb->pc)) { | |
fc59d2d8 | 165 | FILE *logfile = qemu_log_lock(); |
ae765180 PM |
166 | int flags = 0; |
167 | if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) { | |
168 | flags |= CPU_DUMP_FPU; | |
169 | } | |
03afa5f8 | 170 | #if defined(TARGET_I386) |
ae765180 | 171 | flags |= CPU_DUMP_CCOP; |
03afa5f8 | 172 | #endif |
ae765180 | 173 | log_cpu_state(cpu, flags); |
fc59d2d8 | 174 | qemu_log_unlock(logfile); |
03afa5f8 RH |
175 | } |
176 | #endif /* DEBUG_DISAS */ | |
177 | ||
819af24b | 178 | ret = tcg_qemu_tb_exec(env, tb_ptr); |
626cf8f4 | 179 | cpu->can_do_io = 1; |
819af24b SF |
180 | last_tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK); |
181 | tb_exit = ret & TB_EXIT_MASK; | |
182 | trace_exec_tb_exit(last_tb, tb_exit); | |
6db8b538 | 183 | |
819af24b | 184 | if (tb_exit > TB_EXIT_IDX1) { |
77211379 PM |
185 | /* We didn't start executing this TB (eg because the instruction |
186 | * counter hit zero); we must restore the guest PC to the address | |
187 | * of the start of the TB. | |
188 | */ | |
bdf7ae5b | 189 | CPUClass *cc = CPU_GET_CLASS(cpu); |
819af24b | 190 | qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, |
d977e1c2 AB |
191 | "Stopped execution of TB chain before %p [" |
192 | TARGET_FMT_lx "] %s\n", | |
e7e168f4 | 193 | last_tb->tc.ptr, last_tb->pc, |
819af24b | 194 | lookup_symbol(last_tb->pc)); |
bdf7ae5b | 195 | if (cc->synchronize_from_tb) { |
819af24b | 196 | cc->synchronize_from_tb(cpu, last_tb); |
bdf7ae5b AF |
197 | } else { |
198 | assert(cc->set_pc); | |
819af24b | 199 | cc->set_pc(cpu, last_tb->pc); |
bdf7ae5b | 200 | } |
77211379 | 201 | } |
819af24b | 202 | return ret; |
77211379 PM |
203 | } |
204 | ||
7687bf52 | 205 | #ifndef CONFIG_USER_ONLY |
2e70f6ef PB |
206 | /* Execute the code without caching the generated code. An interpreter |
207 | could be used if available. */ | |
ea3e9847 | 208 | static void cpu_exec_nocache(CPUState *cpu, int max_cycles, |
56c0269a | 209 | TranslationBlock *orig_tb, bool ignore_icount) |
2e70f6ef | 210 | { |
2e70f6ef | 211 | TranslationBlock *tb; |
416986d3 RH |
212 | uint32_t cflags = curr_cflags() | CF_NOCACHE; |
213 | ||
214 | if (ignore_icount) { | |
215 | cflags &= ~CF_USE_ICOUNT; | |
216 | } | |
2e70f6ef PB |
217 | |
218 | /* Should never happen. | |
219 | We only end up here when an existing TB is too long. */ | |
416986d3 | 220 | cflags |= MIN(max_cycles, CF_COUNT_MASK); |
2e70f6ef | 221 | |
0ac20318 | 222 | mmap_lock(); |
416986d3 RH |
223 | tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, |
224 | orig_tb->flags, cflags); | |
3359baad | 225 | tb->orig_tb = orig_tb; |
0ac20318 | 226 | mmap_unlock(); |
a5e99826 | 227 | |
2e70f6ef | 228 | /* execute the generated code */ |
6db8b538 | 229 | trace_exec_tb_nocache(tb, tb->pc); |
1a830635 | 230 | cpu_tb_exec(cpu, tb); |
a5e99826 | 231 | |
0ac20318 | 232 | mmap_lock(); |
2e70f6ef | 233 | tb_phys_invalidate(tb, -1); |
0ac20318 | 234 | mmap_unlock(); |
be2cdc5e | 235 | tcg_tb_remove(tb); |
2e70f6ef | 236 | } |
7687bf52 | 237 | #endif |
2e70f6ef | 238 | |
ac03ee53 | 239 | void cpu_exec_step_atomic(CPUState *cpu) |
fdbc2b57 | 240 | { |
08e73c48 | 241 | CPUClass *cc = CPU_GET_CLASS(cpu); |
fdbc2b57 RH |
242 | TranslationBlock *tb; |
243 | target_ulong cs_base, pc; | |
244 | uint32_t flags; | |
416986d3 | 245 | uint32_t cflags = 1; |
ac03ee53 | 246 | uint32_t cf_mask = cflags & CF_HASH_MASK; |
fdbc2b57 | 247 | |
08e73c48 | 248 | if (sigsetjmp(cpu->jmp_env, 0) == 0) { |
886cc689 AB |
249 | start_exclusive(); |
250 | ||
ac03ee53 | 251 | tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); |
4e2ca83e EC |
252 | if (tb == NULL) { |
253 | mmap_lock(); | |
95590e24 | 254 | tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); |
4e2ca83e EC |
255 | mmap_unlock(); |
256 | } | |
08e73c48 | 257 | |
ac03ee53 EC |
258 | /* Since we got here, we know that parallel_cpus must be true. */ |
259 | parallel_cpus = false; | |
08e73c48 PK |
260 | cc->cpu_exec_enter(cpu); |
261 | /* execute the generated code */ | |
4e2ca83e | 262 | trace_exec_tb(tb, pc); |
08e73c48 PK |
263 | cpu_tb_exec(cpu, tb); |
264 | cc->cpu_exec_exit(cpu); | |
08e73c48 | 265 | } else { |
0ac20318 | 266 | /* |
08e73c48 PK |
267 | * The mmap_lock is dropped by tb_gen_code if it runs out of |
268 | * memory. | |
269 | */ | |
270 | #ifndef CONFIG_SOFTMMU | |
271 | tcg_debug_assert(!have_mmap_lock()); | |
272 | #endif | |
6aaa24f9 EC |
273 | if (qemu_mutex_iothread_locked()) { |
274 | qemu_mutex_unlock_iothread(); | |
275 | } | |
faa9372c | 276 | assert_no_pages_locked(); |
e6d86bed | 277 | qemu_plugin_disable_mem_helpers(cpu); |
08e73c48 | 278 | } |
426eeecd | 279 | |
886cc689 AB |
280 | |
281 | /* | |
282 | * As we start the exclusive region before codegen we must still | |
283 | * be in the region if we longjump out of either the codegen or | |
284 | * the execution. | |
285 | */ | |
286 | g_assert(cpu_in_exclusive_context(cpu)); | |
287 | parallel_cpus = true; | |
288 | end_exclusive(); | |
fdbc2b57 RH |
289 | } |
290 | ||
909eaac9 EC |
291 | struct tb_desc { |
292 | target_ulong pc; | |
293 | target_ulong cs_base; | |
294 | CPUArchState *env; | |
295 | tb_page_addr_t phys_page1; | |
296 | uint32_t flags; | |
4e2ca83e | 297 | uint32_t cf_mask; |
61a67f71 | 298 | uint32_t trace_vcpu_dstate; |
909eaac9 EC |
299 | }; |
300 | ||
61b8cef1 | 301 | static bool tb_lookup_cmp(const void *p, const void *d) |
909eaac9 EC |
302 | { |
303 | const TranslationBlock *tb = p; | |
304 | const struct tb_desc *desc = d; | |
305 | ||
306 | if (tb->pc == desc->pc && | |
307 | tb->page_addr[0] == desc->phys_page1 && | |
308 | tb->cs_base == desc->cs_base && | |
6d21e420 | 309 | tb->flags == desc->flags && |
61a67f71 | 310 | tb->trace_vcpu_dstate == desc->trace_vcpu_dstate && |
4e2ca83e | 311 | (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == desc->cf_mask) { |
909eaac9 EC |
312 | /* check next page if needed */ |
313 | if (tb->page_addr[1] == -1) { | |
314 | return true; | |
315 | } else { | |
316 | tb_page_addr_t phys_page2; | |
317 | target_ulong virt_page2; | |
318 | ||
319 | virt_page2 = (desc->pc & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
320 | phys_page2 = get_page_addr_code(desc->env, virt_page2); | |
321 | if (tb->page_addr[1] == phys_page2) { | |
322 | return true; | |
323 | } | |
324 | } | |
325 | } | |
326 | return false; | |
327 | } | |
328 | ||
cedbcb01 | 329 | TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, |
4e2ca83e EC |
330 | target_ulong cs_base, uint32_t flags, |
331 | uint32_t cf_mask) | |
8a40a180 | 332 | { |
909eaac9 EC |
333 | tb_page_addr_t phys_pc; |
334 | struct tb_desc desc; | |
42bd3228 | 335 | uint32_t h; |
3b46e624 | 336 | |
909eaac9 EC |
337 | desc.env = (CPUArchState *)cpu->env_ptr; |
338 | desc.cs_base = cs_base; | |
339 | desc.flags = flags; | |
4e2ca83e | 340 | desc.cf_mask = cf_mask; |
61a67f71 | 341 | desc.trace_vcpu_dstate = *cpu->trace_dstate; |
909eaac9 EC |
342 | desc.pc = pc; |
343 | phys_pc = get_page_addr_code(desc.env, pc); | |
7252f2de PM |
344 | if (phys_pc == -1) { |
345 | return NULL; | |
346 | } | |
909eaac9 | 347 | desc.phys_page1 = phys_pc & TARGET_PAGE_MASK; |
4e2ca83e | 348 | h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); |
61b8cef1 | 349 | return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); |
9fd1a948 PB |
350 | } |
351 | ||
a8583393 RH |
352 | void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) |
353 | { | |
354 | if (TCG_TARGET_HAS_direct_jump) { | |
355 | uintptr_t offset = tb->jmp_target_arg[n]; | |
e7e168f4 | 356 | uintptr_t tc_ptr = (uintptr_t)tb->tc.ptr; |
a8583393 RH |
357 | tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr); |
358 | } else { | |
359 | tb->jmp_target_arg[n] = addr; | |
360 | } | |
361 | } | |
362 | ||
a8583393 RH |
363 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
364 | TranslationBlock *tb_next) | |
365 | { | |
194125e3 EC |
366 | uintptr_t old; |
367 | ||
a8583393 | 368 | assert(n < ARRAY_SIZE(tb->jmp_list_next)); |
194125e3 EC |
369 | qemu_spin_lock(&tb_next->jmp_lock); |
370 | ||
371 | /* make sure the destination TB is valid */ | |
372 | if (tb_next->cflags & CF_INVALID) { | |
373 | goto out_unlock_next; | |
374 | } | |
375 | /* Atomically claim the jump destination slot only if it was NULL */ | |
d73415a3 SH |
376 | old = qatomic_cmpxchg(&tb->jmp_dest[n], (uintptr_t)NULL, |
377 | (uintptr_t)tb_next); | |
194125e3 EC |
378 | if (old) { |
379 | goto out_unlock_next; | |
a8583393 | 380 | } |
194125e3 EC |
381 | |
382 | /* patch the native jump address */ | |
383 | tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr); | |
384 | ||
385 | /* add in TB jmp list */ | |
386 | tb->jmp_list_next[n] = tb_next->jmp_list_head; | |
387 | tb_next->jmp_list_head = (uintptr_t)tb | n; | |
388 | ||
389 | qemu_spin_unlock(&tb_next->jmp_lock); | |
390 | ||
a8583393 RH |
391 | qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, |
392 | "Linking TBs %p [" TARGET_FMT_lx | |
393 | "] index %d -> %p [" TARGET_FMT_lx "]\n", | |
e7e168f4 EC |
394 | tb->tc.ptr, tb->pc, n, |
395 | tb_next->tc.ptr, tb_next->pc); | |
194125e3 | 396 | return; |
a8583393 | 397 | |
194125e3 EC |
398 | out_unlock_next: |
399 | qemu_spin_unlock(&tb_next->jmp_lock); | |
400 | return; | |
a8583393 RH |
401 | } |
402 | ||
bd2710d5 SF |
403 | static inline TranslationBlock *tb_find(CPUState *cpu, |
404 | TranslationBlock *last_tb, | |
9b990ee5 | 405 | int tb_exit, uint32_t cf_mask) |
8a40a180 FB |
406 | { |
407 | TranslationBlock *tb; | |
408 | target_ulong cs_base, pc; | |
89fee74a | 409 | uint32_t flags; |
8a40a180 | 410 | |
4e2ca83e | 411 | tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); |
f6bb84d5 | 412 | if (tb == NULL) { |
f6bb84d5 | 413 | mmap_lock(); |
95590e24 | 414 | tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask); |
f6bb84d5 | 415 | mmap_unlock(); |
bd2710d5 | 416 | /* We add the TB in the virtual pc hash table for the fast lookup */ |
d73415a3 | 417 | qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); |
8a40a180 | 418 | } |
c88c67e5 SF |
419 | #ifndef CONFIG_USER_ONLY |
420 | /* We don't take care of direct jumps when address mapping changes in | |
421 | * system emulation. So it's not safe to make a direct jump to a TB | |
422 | * spanning two pages because the mapping for the second page can change. | |
423 | */ | |
424 | if (tb->page_addr[1] != -1) { | |
4b7e6950 | 425 | last_tb = NULL; |
c88c67e5 SF |
426 | } |
427 | #endif | |
a0522c7a | 428 | /* See if we can patch the calling TB. */ |
d7f425fd | 429 | if (last_tb) { |
194125e3 | 430 | tb_add_jump(last_tb, tb_exit, tb); |
74d356dd | 431 | } |
8a40a180 FB |
432 | return tb; |
433 | } | |
434 | ||
8b2d34e9 SF |
435 | static inline bool cpu_handle_halt(CPUState *cpu) |
436 | { | |
437 | if (cpu->halted) { | |
438 | #if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) | |
4084893d | 439 | if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { |
8b2d34e9 | 440 | X86CPU *x86_cpu = X86_CPU(cpu); |
8d04fb55 | 441 | qemu_mutex_lock_iothread(); |
8b2d34e9 SF |
442 | apic_poll_irq(x86_cpu->apic_state); |
443 | cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); | |
8d04fb55 | 444 | qemu_mutex_unlock_iothread(); |
8b2d34e9 SF |
445 | } |
446 | #endif | |
447 | if (!cpu_has_work(cpu)) { | |
8b2d34e9 SF |
448 | return true; |
449 | } | |
450 | ||
451 | cpu->halted = 0; | |
452 | } | |
453 | ||
454 | return false; | |
455 | } | |
456 | ||
ea284766 | 457 | static inline void cpu_handle_debug_exception(CPUState *cpu) |
1009d2ed | 458 | { |
86025ee4 | 459 | CPUClass *cc = CPU_GET_CLASS(cpu); |
1009d2ed JK |
460 | CPUWatchpoint *wp; |
461 | ||
ff4700b0 AF |
462 | if (!cpu->watchpoint_hit) { |
463 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | |
1009d2ed JK |
464 | wp->flags &= ~BP_WATCHPOINT_HIT; |
465 | } | |
466 | } | |
86025ee4 PM |
467 | |
468 | cc->debug_excp_handler(cpu); | |
1009d2ed JK |
469 | } |
470 | ||
ea284766 SF |
471 | static inline bool cpu_handle_exception(CPUState *cpu, int *ret) |
472 | { | |
17b50b0c PD |
473 | if (cpu->exception_index < 0) { |
474 | #ifndef CONFIG_USER_ONLY | |
475 | if (replay_has_exception() | |
5e140196 | 476 | && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) { |
17b50b0c PD |
477 | /* try to cause an exception pending in the log */ |
478 | cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true); | |
479 | } | |
480 | #endif | |
481 | if (cpu->exception_index < 0) { | |
482 | return false; | |
483 | } | |
484 | } | |
485 | ||
486 | if (cpu->exception_index >= EXCP_INTERRUPT) { | |
487 | /* exit request from the cpu execution loop */ | |
488 | *ret = cpu->exception_index; | |
489 | if (*ret == EXCP_DEBUG) { | |
490 | cpu_handle_debug_exception(cpu); | |
491 | } | |
492 | cpu->exception_index = -1; | |
493 | return true; | |
494 | } else { | |
ea284766 | 495 | #if defined(CONFIG_USER_ONLY) |
17b50b0c PD |
496 | /* if user mode only, we simulate a fake exception |
497 | which will be handled outside the cpu execution | |
498 | loop */ | |
ea284766 | 499 | #if defined(TARGET_I386) |
17b50b0c PD |
500 | CPUClass *cc = CPU_GET_CLASS(cpu); |
501 | cc->do_interrupt(cpu); | |
502 | #endif | |
503 | *ret = cpu->exception_index; | |
504 | cpu->exception_index = -1; | |
505 | return true; | |
506 | #else | |
507 | if (replay_exception()) { | |
ea284766 | 508 | CPUClass *cc = CPU_GET_CLASS(cpu); |
17b50b0c | 509 | qemu_mutex_lock_iothread(); |
ea284766 | 510 | cc->do_interrupt(cpu); |
17b50b0c | 511 | qemu_mutex_unlock_iothread(); |
ea284766 | 512 | cpu->exception_index = -1; |
a7ba744f LM |
513 | |
514 | if (unlikely(cpu->singlestep_enabled)) { | |
515 | /* | |
516 | * After processing the exception, ensure an EXCP_DEBUG is | |
517 | * raised when single-stepping so that GDB doesn't miss the | |
518 | * next instruction. | |
519 | */ | |
520 | *ret = EXCP_DEBUG; | |
521 | cpu_handle_debug_exception(cpu); | |
522 | return true; | |
523 | } | |
17b50b0c PD |
524 | } else if (!replay_has_interrupt()) { |
525 | /* give a chance to iothread in replay mode */ | |
526 | *ret = EXCP_INTERRUPT; | |
ea284766 | 527 | return true; |
ea284766 | 528 | } |
ea284766 SF |
529 | #endif |
530 | } | |
531 | ||
532 | return false; | |
533 | } | |
534 | ||
4084893d PD |
535 | /* |
536 | * CPU_INTERRUPT_POLL is a virtual event which gets converted into a | |
537 | * "real" interrupt event later. It does not need to be recorded for | |
538 | * replay purposes. | |
539 | */ | |
540 | static inline bool need_replay_interrupt(int interrupt_request) | |
541 | { | |
542 | #if defined(TARGET_I386) | |
543 | return !(interrupt_request & CPU_INTERRUPT_POLL); | |
544 | #else | |
545 | return true; | |
546 | #endif | |
547 | } | |
548 | ||
209b71b6 | 549 | static inline bool cpu_handle_interrupt(CPUState *cpu, |
c385e6e4 SF |
550 | TranslationBlock **last_tb) |
551 | { | |
552 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
17b50b0c PD |
553 | |
554 | /* Clear the interrupt flag now since we're processing | |
555 | * cpu->interrupt_request and cpu->exit_request. | |
d84be02d DH |
556 | * Ensure zeroing happens before reading cpu->exit_request or |
557 | * cpu->interrupt_request (see also smp_wmb in cpu_exit()) | |
17b50b0c | 558 | */ |
d73415a3 | 559 | qatomic_mb_set(&cpu_neg(cpu)->icount_decr.u16.high, 0); |
c385e6e4 | 560 | |
d73415a3 | 561 | if (unlikely(qatomic_read(&cpu->interrupt_request))) { |
8d04fb55 JK |
562 | int interrupt_request; |
563 | qemu_mutex_lock_iothread(); | |
564 | interrupt_request = cpu->interrupt_request; | |
c385e6e4 SF |
565 | if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) { |
566 | /* Mask out external interrupts for this step. */ | |
567 | interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK; | |
568 | } | |
569 | if (interrupt_request & CPU_INTERRUPT_DEBUG) { | |
570 | cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; | |
571 | cpu->exception_index = EXCP_DEBUG; | |
8d04fb55 | 572 | qemu_mutex_unlock_iothread(); |
209b71b6 | 573 | return true; |
c385e6e4 SF |
574 | } |
575 | if (replay_mode == REPLAY_MODE_PLAY && !replay_has_interrupt()) { | |
576 | /* Do nothing */ | |
577 | } else if (interrupt_request & CPU_INTERRUPT_HALT) { | |
578 | replay_interrupt(); | |
579 | cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; | |
580 | cpu->halted = 1; | |
581 | cpu->exception_index = EXCP_HLT; | |
8d04fb55 | 582 | qemu_mutex_unlock_iothread(); |
209b71b6 | 583 | return true; |
c385e6e4 SF |
584 | } |
585 | #if defined(TARGET_I386) | |
586 | else if (interrupt_request & CPU_INTERRUPT_INIT) { | |
587 | X86CPU *x86_cpu = X86_CPU(cpu); | |
588 | CPUArchState *env = &x86_cpu->env; | |
589 | replay_interrupt(); | |
65c9d60a | 590 | cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); |
c385e6e4 SF |
591 | do_cpu_init(x86_cpu); |
592 | cpu->exception_index = EXCP_HALTED; | |
8d04fb55 | 593 | qemu_mutex_unlock_iothread(); |
209b71b6 | 594 | return true; |
c385e6e4 SF |
595 | } |
596 | #else | |
597 | else if (interrupt_request & CPU_INTERRUPT_RESET) { | |
598 | replay_interrupt(); | |
599 | cpu_reset(cpu); | |
8d04fb55 | 600 | qemu_mutex_unlock_iothread(); |
209b71b6 | 601 | return true; |
c385e6e4 SF |
602 | } |
603 | #endif | |
604 | /* The target hook has 3 exit conditions: | |
605 | False when the interrupt isn't processed, | |
606 | True when it is, and we should restart on a new TB, | |
607 | and via longjmp via cpu_loop_exit. */ | |
608 | else { | |
c385e6e4 | 609 | if (cc->cpu_exec_interrupt(cpu, interrupt_request)) { |
4084893d PD |
610 | if (need_replay_interrupt(interrupt_request)) { |
611 | replay_interrupt(); | |
612 | } | |
ba3c35d9 RH |
613 | /* |
614 | * After processing the interrupt, ensure an EXCP_DEBUG is | |
615 | * raised when single-stepping so that GDB doesn't miss the | |
616 | * next instruction. | |
617 | */ | |
618 | cpu->exception_index = | |
619 | (cpu->singlestep_enabled ? EXCP_DEBUG : -1); | |
c385e6e4 SF |
620 | *last_tb = NULL; |
621 | } | |
8b1fe3f4 SF |
622 | /* The target hook may have updated the 'cpu->interrupt_request'; |
623 | * reload the 'interrupt_request' value */ | |
624 | interrupt_request = cpu->interrupt_request; | |
c385e6e4 | 625 | } |
8b1fe3f4 | 626 | if (interrupt_request & CPU_INTERRUPT_EXITTB) { |
c385e6e4 SF |
627 | cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
628 | /* ensure that no TB jump will be modified as | |
629 | the program flow was changed */ | |
630 | *last_tb = NULL; | |
631 | } | |
8d04fb55 JK |
632 | |
633 | /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */ | |
634 | qemu_mutex_unlock_iothread(); | |
c385e6e4 | 635 | } |
8d04fb55 | 636 | |
cfb2d02b | 637 | /* Finally, check if we need to exit to the main loop. */ |
d73415a3 | 638 | if (unlikely(qatomic_read(&cpu->exit_request)) |
740b1759 | 639 | || (icount_enabled() |
5e140196 | 640 | && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0)) { |
d73415a3 | 641 | qatomic_set(&cpu->exit_request, 0); |
5f3bdfd4 PD |
642 | if (cpu->exception_index == -1) { |
643 | cpu->exception_index = EXCP_INTERRUPT; | |
644 | } | |
209b71b6 | 645 | return true; |
c385e6e4 | 646 | } |
209b71b6 PB |
647 | |
648 | return false; | |
c385e6e4 SF |
649 | } |
650 | ||
928de9ee | 651 | static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, |
cfb2d02b | 652 | TranslationBlock **last_tb, int *tb_exit) |
928de9ee SF |
653 | { |
654 | uintptr_t ret; | |
1aab16c2 | 655 | int32_t insns_left; |
928de9ee SF |
656 | |
657 | trace_exec_tb(tb, tb->pc); | |
658 | ret = cpu_tb_exec(cpu, tb); | |
43d70ddf | 659 | tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK); |
928de9ee | 660 | *tb_exit = ret & TB_EXIT_MASK; |
1aab16c2 PB |
661 | if (*tb_exit != TB_EXIT_REQUESTED) { |
662 | *last_tb = tb; | |
663 | return; | |
664 | } | |
665 | ||
666 | *last_tb = NULL; | |
d73415a3 | 667 | insns_left = qatomic_read(&cpu_neg(cpu)->icount_decr.u32); |
1aab16c2 | 668 | if (insns_left < 0) { |
e5143e30 AB |
669 | /* Something asked us to stop executing chained TBs; just |
670 | * continue round the main loop. Whatever requested the exit | |
30f3dda2 | 671 | * will also have set something else (eg exit_request or |
17b50b0c PD |
672 | * interrupt_request) which will be handled by |
673 | * cpu_handle_interrupt. cpu_handle_interrupt will also | |
674 | * clear cpu->icount_decr.u16.high. | |
928de9ee | 675 | */ |
1aab16c2 | 676 | return; |
928de9ee | 677 | } |
1aab16c2 PB |
678 | |
679 | /* Instruction counter expired. */ | |
740b1759 | 680 | assert(icount_enabled()); |
1aab16c2 | 681 | #ifndef CONFIG_USER_ONLY |
eda5f7c6 | 682 | /* Ensure global icount has gone forward */ |
8191d368 | 683 | icount_update(cpu); |
eda5f7c6 AB |
684 | /* Refill decrementer and continue execution. */ |
685 | insns_left = MIN(0xffff, cpu->icount_budget); | |
5e140196 | 686 | cpu_neg(cpu)->icount_decr.u16.low = insns_left; |
eda5f7c6 | 687 | cpu->icount_extra = cpu->icount_budget - insns_left; |
835cbd8d | 688 | if (!cpu->icount_extra && insns_left < tb->icount) { |
1aab16c2 PB |
689 | /* Execute any remaining instructions, then let the main loop |
690 | * handle the next event. | |
691 | */ | |
692 | if (insns_left > 0) { | |
693 | cpu_exec_nocache(cpu, insns_left, tb, false); | |
1aab16c2 | 694 | } |
928de9ee | 695 | } |
1aab16c2 | 696 | #endif |
928de9ee SF |
697 | } |
698 | ||
7d13299d FB |
699 | /* main execution loop */ |
700 | ||
ea3e9847 | 701 | int cpu_exec(CPUState *cpu) |
7d13299d | 702 | { |
97a8ea5a | 703 | CPUClass *cc = CPU_GET_CLASS(cpu); |
c385e6e4 | 704 | int ret; |
cfb2d02b | 705 | SyncClocks sc = { 0 }; |
c2aa5f81 | 706 | |
6f060969 PD |
707 | /* replay_interrupt may need current_cpu */ |
708 | current_cpu = cpu; | |
709 | ||
8b2d34e9 SF |
710 | if (cpu_handle_halt(cpu)) { |
711 | return EXCP_HALTED; | |
eda48c34 | 712 | } |
5a1e3cfc | 713 | |
79e2b9ae PB |
714 | rcu_read_lock(); |
715 | ||
cffe7b32 | 716 | cc->cpu_exec_enter(cpu); |
9d27abd9 | 717 | |
c2aa5f81 ST |
718 | /* Calculate difference between guest clock and host clock. |
719 | * This delay includes the delay of the last cycle, so | |
720 | * what we have to do is sleep until it is 0. As for the | |
721 | * advance/delay we gain here, we try to fix it next time. | |
722 | */ | |
723 | init_delay_params(&sc, cpu); | |
724 | ||
4515e58d PB |
725 | /* prepare setjmp context for exception handling */ |
726 | if (sigsetjmp(cpu->jmp_env, 0) != 0) { | |
0448f5f8 | 727 | #if defined(__clang__) || !QEMU_GNUC_PREREQ(4, 6) |
4515e58d PB |
728 | /* Some compilers wrongly smash all local variables after |
729 | * siglongjmp. There were bug reports for gcc 4.5.0 and clang. | |
730 | * Reload essential local variables here for those compilers. | |
731 | * Newer versions of gcc would complain about this code (-Wclobbered). */ | |
732 | cpu = current_cpu; | |
733 | cc = CPU_GET_CLASS(cpu); | |
0448f5f8 | 734 | #else /* buggy compiler */ |
4515e58d PB |
735 | /* Assert that the compiler does not smash local variables. */ |
736 | g_assert(cpu == current_cpu); | |
737 | g_assert(cc == CPU_GET_CLASS(cpu)); | |
0448f5f8 | 738 | #endif /* buggy compiler */ |
0ac20318 EC |
739 | #ifndef CONFIG_SOFTMMU |
740 | tcg_debug_assert(!have_mmap_lock()); | |
741 | #endif | |
8d04fb55 JK |
742 | if (qemu_mutex_iothread_locked()) { |
743 | qemu_mutex_unlock_iothread(); | |
744 | } | |
e6d86bed EC |
745 | qemu_plugin_disable_mem_helpers(cpu); |
746 | ||
8fd3a9b8 | 747 | assert_no_pages_locked(); |
4515e58d PB |
748 | } |
749 | ||
750 | /* if an exception is pending, we execute it here */ | |
751 | while (!cpu_handle_exception(cpu, &ret)) { | |
752 | TranslationBlock *last_tb = NULL; | |
753 | int tb_exit = 0; | |
754 | ||
755 | while (!cpu_handle_interrupt(cpu, &last_tb)) { | |
9b990ee5 RH |
756 | uint32_t cflags = cpu->cflags_next_tb; |
757 | TranslationBlock *tb; | |
758 | ||
759 | /* When requested, use an exact setting for cflags for the next | |
760 | execution. This is used for icount, precise smc, and stop- | |
761 | after-access watchpoints. Since this request should never | |
762 | have CF_INVALID set, -1 is a convenient invalid value that | |
763 | does not require tcg headers for cpu_common_reset. */ | |
764 | if (cflags == -1) { | |
765 | cflags = curr_cflags(); | |
766 | } else { | |
767 | cpu->cflags_next_tb = -1; | |
768 | } | |
769 | ||
770 | tb = tb_find(cpu, last_tb, tb_exit, cflags); | |
cfb2d02b | 771 | cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit); |
4515e58d PB |
772 | /* Try to align the host and virtual clocks |
773 | if the guest is in advance */ | |
774 | align_clocks(&sc, cpu); | |
7d13299d | 775 | } |
4515e58d | 776 | } |
3fb2ded1 | 777 | |
cffe7b32 | 778 | cc->cpu_exec_exit(cpu); |
79e2b9ae | 779 | rcu_read_unlock(); |
1057eaa7 | 780 | |
7d13299d FB |
781 | return ret; |
782 | } | |
740b1759 CF |
783 | |
784 | #ifndef CONFIG_USER_ONLY | |
785 | ||
786 | void dump_drift_info(void) | |
787 | { | |
788 | if (!icount_enabled()) { | |
789 | return; | |
790 | } | |
791 | ||
792 | qemu_printf("Host - Guest clock %"PRIi64" ms\n", | |
8191d368 | 793 | (cpu_get_clock() - icount_get()) / SCALE_MS); |
740b1759 CF |
794 | if (icount_align_option) { |
795 | qemu_printf("Max guest delay %"PRIi64" ms\n", | |
796 | -max_delay / SCALE_MS); | |
797 | qemu_printf("Max guest advance %"PRIi64" ms\n", | |
798 | max_advance / SCALE_MS); | |
799 | } else { | |
800 | qemu_printf("Max guest delay NA\n"); | |
801 | qemu_printf("Max guest advance NA\n"); | |
802 | } | |
803 | } | |
804 | ||
805 | #endif /* !CONFIG_USER_ONLY */ |