]> git.proxmox.com Git - mirror_qemu.git/blame - accel/tcg/cpu-exec.c
accel/tcg: actually cache our partial icount TB
[mirror_qemu.git] / accel / tcg / cpu-exec.c
CommitLineData
7d13299d 1/*
e965fc38 2 * emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
fb0343d5 9 * version 2.1 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
a8d25326 19
7b31bbc2 20#include "qemu/osdep.h"
a8d25326 21#include "qemu-common.h"
740b1759 22#include "qemu/qemu-print.h"
cea5f9a2 23#include "cpu.h"
78271684 24#include "hw/core/tcg-cpu-ops.h"
d9bb58e5 25#include "trace.h"
76cad711 26#include "disas/disas.h"
63c91552 27#include "exec/exec-all.h"
dcb32f1d 28#include "tcg/tcg.h"
1de7afc9 29#include "qemu/atomic.h"
c905a368 30#include "qemu/compiler.h"
9c17d615 31#include "sysemu/qtest.h"
c2aa5f81 32#include "qemu/timer.h"
79e2b9ae 33#include "qemu/rcu.h"
e1b89321 34#include "exec/tb-hash.h"
f6bb84d5 35#include "exec/tb-lookup.h"
508127e2 36#include "exec/log.h"
8d04fb55 37#include "qemu/main-loop.h"
6220e900
PD
38#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
39#include "hw/i386/apic.h"
40#endif
d2528bdc 41#include "sysemu/cpus.h"
740b1759
CF
42#include "exec/cpu-all.h"
43#include "sysemu/cpu-timers.h"
6f060969 44#include "sysemu/replay.h"
c03f041f 45#include "internal.h"
c2aa5f81
ST
46
47/* -icount align implementation. */
48
49typedef struct SyncClocks {
50 int64_t diff_clk;
51 int64_t last_cpu_icount;
7f7bc144 52 int64_t realtime_clock;
c2aa5f81
ST
53} SyncClocks;
54
55#if !defined(CONFIG_USER_ONLY)
56/* Allow the guest to have a max 3ms advance.
57 * The difference between the 2 clocks could therefore
58 * oscillate around 0.
59 */
60#define VM_CLOCK_ADVANCE 3000000
7f7bc144
ST
61#define THRESHOLD_REDUCE 1.5
62#define MAX_DELAY_PRINT_RATE 2000000000LL
63#define MAX_NB_PRINTS 100
c2aa5f81 64
740b1759
CF
65static int64_t max_delay;
66static int64_t max_advance;
67
5e140196 68static void align_clocks(SyncClocks *sc, CPUState *cpu)
c2aa5f81
ST
69{
70 int64_t cpu_icount;
71
72 if (!icount_align_option) {
73 return;
74 }
75
5e140196 76 cpu_icount = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low;
8191d368 77 sc->diff_clk += icount_to_ns(sc->last_cpu_icount - cpu_icount);
c2aa5f81
ST
78 sc->last_cpu_icount = cpu_icount;
79
80 if (sc->diff_clk > VM_CLOCK_ADVANCE) {
81#ifndef _WIN32
82 struct timespec sleep_delay, rem_delay;
83 sleep_delay.tv_sec = sc->diff_clk / 1000000000LL;
84 sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL;
85 if (nanosleep(&sleep_delay, &rem_delay) < 0) {
a498d0ef 86 sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec;
c2aa5f81
ST
87 } else {
88 sc->diff_clk = 0;
89 }
90#else
91 Sleep(sc->diff_clk / SCALE_MS);
92 sc->diff_clk = 0;
93#endif
94 }
95}
96
7f7bc144
ST
97static void print_delay(const SyncClocks *sc)
98{
99 static float threshold_delay;
100 static int64_t last_realtime_clock;
101 static int nb_prints;
102
103 if (icount_align_option &&
104 sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE &&
105 nb_prints < MAX_NB_PRINTS) {
106 if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) ||
107 (-sc->diff_clk / (float)1000000000LL <
108 (threshold_delay - THRESHOLD_REDUCE))) {
109 threshold_delay = (-sc->diff_clk / 1000000000LL) + 1;
740b1759
CF
110 qemu_printf("Warning: The guest is now late by %.1f to %.1f seconds\n",
111 threshold_delay - 1,
112 threshold_delay);
7f7bc144
ST
113 nb_prints++;
114 last_realtime_clock = sc->realtime_clock;
115 }
116 }
117}
118
5e140196 119static void init_delay_params(SyncClocks *sc, CPUState *cpu)
c2aa5f81
ST
120{
121 if (!icount_align_option) {
122 return;
123 }
2e91cc62
PB
124 sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
125 sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
5e140196
RH
126 sc->last_cpu_icount
127 = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low;
27498bef
ST
128 if (sc->diff_clk < max_delay) {
129 max_delay = sc->diff_clk;
130 }
131 if (sc->diff_clk > max_advance) {
132 max_advance = sc->diff_clk;
133 }
7f7bc144
ST
134
135 /* Print every 2s max if the guest is late. We limit the number
136 of printed messages to NB_PRINT_MAX(currently 100) */
137 print_delay(sc);
c2aa5f81
ST
138}
139#else
140static void align_clocks(SyncClocks *sc, const CPUState *cpu)
141{
142}
143
144static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
145{
146}
147#endif /* CONFIG USER ONLY */
7d13299d 148
77211379 149/* Execute a TB, and fix up the CPU state afterwards if necessary */
c905a368
DB
150/*
151 * Disable CFI checks.
152 * TCG creates binary blobs at runtime, with the transformed code.
153 * A TB is a blob of binary code, created at runtime and called with an
154 * indirect function call. Since such function did not exist at compile time,
155 * the CFI runtime has no way to verify its signature and would fail.
156 * TCG is not considered a security-sensitive part of QEMU so this does not
157 * affect the impact of CFI in environment with high security requirements
158 */
eba40358
RH
159static inline TranslationBlock * QEMU_DISABLE_CFI
160cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
77211379
PM
161{
162 CPUArchState *env = cpu->env_ptr;
819af24b
SF
163 uintptr_t ret;
164 TranslationBlock *last_tb;
db0c51a3 165 const void *tb_ptr = itb->tc.ptr;
1a830635 166
d977e1c2 167 qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
4fad446b
PB
168 "Trace %d: %p ["
169 TARGET_FMT_lx "/" TARGET_FMT_lx "/%#x] %s\n",
170 cpu->cpu_index, itb->tc.ptr,
171 itb->cs_base, itb->pc, itb->flags,
4426f83a 172 lookup_symbol(itb->pc));
03afa5f8
RH
173
174#if defined(DEBUG_DISAS)
be2208e2
RH
175 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
176 && qemu_log_in_addr_range(itb->pc)) {
fc59d2d8 177 FILE *logfile = qemu_log_lock();
ae765180
PM
178 int flags = 0;
179 if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
180 flags |= CPU_DUMP_FPU;
181 }
03afa5f8 182#if defined(TARGET_I386)
ae765180 183 flags |= CPU_DUMP_CCOP;
03afa5f8 184#endif
ae765180 185 log_cpu_state(cpu, flags);
fc59d2d8 186 qemu_log_unlock(logfile);
03afa5f8
RH
187 }
188#endif /* DEBUG_DISAS */
189
653b87eb 190 qemu_thread_jit_execute();
819af24b 191 ret = tcg_qemu_tb_exec(env, tb_ptr);
626cf8f4 192 cpu->can_do_io = 1;
eba40358
RH
193 /*
194 * TODO: Delay swapping back to the read-write region of the TB
195 * until we actually need to modify the TB. The read-only copy,
196 * coming from the rx region, shares the same host TLB entry as
197 * the code that executed the exit_tb opcode that arrived here.
198 * If we insist on touching both the RX and the RW pages, we
199 * double the host TLB pressure.
200 */
201 last_tb = tcg_splitwx_to_rw((void *)(ret & ~TB_EXIT_MASK));
202 *tb_exit = ret & TB_EXIT_MASK;
203
204 trace_exec_tb_exit(last_tb, *tb_exit);
6db8b538 205
eba40358 206 if (*tb_exit > TB_EXIT_IDX1) {
77211379
PM
207 /* We didn't start executing this TB (eg because the instruction
208 * counter hit zero); we must restore the guest PC to the address
209 * of the start of the TB.
210 */
bdf7ae5b 211 CPUClass *cc = CPU_GET_CLASS(cpu);
819af24b 212 qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc,
d977e1c2
AB
213 "Stopped execution of TB chain before %p ["
214 TARGET_FMT_lx "] %s\n",
e7e168f4 215 last_tb->tc.ptr, last_tb->pc,
819af24b 216 lookup_symbol(last_tb->pc));
78271684
CF
217 if (cc->tcg_ops->synchronize_from_tb) {
218 cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
bdf7ae5b
AF
219 } else {
220 assert(cc->set_pc);
819af24b 221 cc->set_pc(cpu, last_tb->pc);
bdf7ae5b 222 }
77211379 223 }
eba40358 224 return last_tb;
77211379
PM
225}
226
7687bf52 227#ifndef CONFIG_USER_ONLY
2e70f6ef
PB
228/* Execute the code without caching the generated code. An interpreter
229 could be used if available. */
ea3e9847 230static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
56c0269a 231 TranslationBlock *orig_tb, bool ignore_icount)
2e70f6ef 232{
2e70f6ef 233 TranslationBlock *tb;
416986d3 234 uint32_t cflags = curr_cflags() | CF_NOCACHE;
eba40358 235 int tb_exit;
416986d3
RH
236
237 if (ignore_icount) {
238 cflags &= ~CF_USE_ICOUNT;
239 }
2e70f6ef
PB
240
241 /* Should never happen.
242 We only end up here when an existing TB is too long. */
416986d3 243 cflags |= MIN(max_cycles, CF_COUNT_MASK);
2e70f6ef 244
0ac20318 245 mmap_lock();
416986d3
RH
246 tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base,
247 orig_tb->flags, cflags);
3359baad 248 tb->orig_tb = orig_tb;
0ac20318 249 mmap_unlock();
a5e99826 250
2e70f6ef 251 /* execute the generated code */
6db8b538 252 trace_exec_tb_nocache(tb, tb->pc);
eba40358 253 cpu_tb_exec(cpu, tb, &tb_exit);
a5e99826 254
0ac20318 255 mmap_lock();
2e70f6ef 256 tb_phys_invalidate(tb, -1);
0ac20318 257 mmap_unlock();
be2cdc5e 258 tcg_tb_remove(tb);
2e70f6ef 259}
7687bf52 260#endif
2e70f6ef 261
035ba06c
EH
262static void cpu_exec_enter(CPUState *cpu)
263{
264 CPUClass *cc = CPU_GET_CLASS(cpu);
265
78271684
CF
266 if (cc->tcg_ops->cpu_exec_enter) {
267 cc->tcg_ops->cpu_exec_enter(cpu);
80c4750b 268 }
035ba06c
EH
269}
270
271static void cpu_exec_exit(CPUState *cpu)
fdbc2b57 272{
08e73c48 273 CPUClass *cc = CPU_GET_CLASS(cpu);
035ba06c 274
78271684
CF
275 if (cc->tcg_ops->cpu_exec_exit) {
276 cc->tcg_ops->cpu_exec_exit(cpu);
80c4750b 277 }
035ba06c
EH
278}
279
280void cpu_exec_step_atomic(CPUState *cpu)
281{
fdbc2b57
RH
282 TranslationBlock *tb;
283 target_ulong cs_base, pc;
284 uint32_t flags;
416986d3 285 uint32_t cflags = 1;
ac03ee53 286 uint32_t cf_mask = cflags & CF_HASH_MASK;
eba40358 287 int tb_exit;
fdbc2b57 288
08e73c48 289 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
886cc689 290 start_exclusive();
bfff072c
DC
291 g_assert(cpu == current_cpu);
292 g_assert(!cpu->running);
293 cpu->running = true;
886cc689 294
ac03ee53 295 tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
4e2ca83e
EC
296 if (tb == NULL) {
297 mmap_lock();
95590e24 298 tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
4e2ca83e
EC
299 mmap_unlock();
300 }
08e73c48 301
ac03ee53
EC
302 /* Since we got here, we know that parallel_cpus must be true. */
303 parallel_cpus = false;
035ba06c 304 cpu_exec_enter(cpu);
08e73c48 305 /* execute the generated code */
4e2ca83e 306 trace_exec_tb(tb, pc);
eba40358 307 cpu_tb_exec(cpu, tb, &tb_exit);
035ba06c 308 cpu_exec_exit(cpu);
08e73c48 309 } else {
0ac20318 310 /*
08e73c48
PK
311 * The mmap_lock is dropped by tb_gen_code if it runs out of
312 * memory.
313 */
314#ifndef CONFIG_SOFTMMU
315 tcg_debug_assert(!have_mmap_lock());
316#endif
6aaa24f9
EC
317 if (qemu_mutex_iothread_locked()) {
318 qemu_mutex_unlock_iothread();
319 }
faa9372c 320 assert_no_pages_locked();
e6d86bed 321 qemu_plugin_disable_mem_helpers(cpu);
08e73c48 322 }
426eeecd 323
886cc689
AB
324
325 /*
326 * As we start the exclusive region before codegen we must still
327 * be in the region if we longjump out of either the codegen or
328 * the execution.
329 */
330 g_assert(cpu_in_exclusive_context(cpu));
331 parallel_cpus = true;
bfff072c 332 cpu->running = false;
886cc689 333 end_exclusive();
fdbc2b57
RH
334}
335
909eaac9
EC
336struct tb_desc {
337 target_ulong pc;
338 target_ulong cs_base;
339 CPUArchState *env;
340 tb_page_addr_t phys_page1;
341 uint32_t flags;
4e2ca83e 342 uint32_t cf_mask;
61a67f71 343 uint32_t trace_vcpu_dstate;
909eaac9
EC
344};
345
61b8cef1 346static bool tb_lookup_cmp(const void *p, const void *d)
909eaac9
EC
347{
348 const TranslationBlock *tb = p;
349 const struct tb_desc *desc = d;
350
351 if (tb->pc == desc->pc &&
352 tb->page_addr[0] == desc->phys_page1 &&
353 tb->cs_base == desc->cs_base &&
6d21e420 354 tb->flags == desc->flags &&
61a67f71 355 tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
4e2ca83e 356 (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == desc->cf_mask) {
909eaac9
EC
357 /* check next page if needed */
358 if (tb->page_addr[1] == -1) {
359 return true;
360 } else {
361 tb_page_addr_t phys_page2;
362 target_ulong virt_page2;
363
364 virt_page2 = (desc->pc & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
365 phys_page2 = get_page_addr_code(desc->env, virt_page2);
366 if (tb->page_addr[1] == phys_page2) {
367 return true;
368 }
369 }
370 }
371 return false;
372}
373
cedbcb01 374TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
4e2ca83e
EC
375 target_ulong cs_base, uint32_t flags,
376 uint32_t cf_mask)
8a40a180 377{
909eaac9
EC
378 tb_page_addr_t phys_pc;
379 struct tb_desc desc;
42bd3228 380 uint32_t h;
3b46e624 381
909eaac9
EC
382 desc.env = (CPUArchState *)cpu->env_ptr;
383 desc.cs_base = cs_base;
384 desc.flags = flags;
4e2ca83e 385 desc.cf_mask = cf_mask;
61a67f71 386 desc.trace_vcpu_dstate = *cpu->trace_dstate;
909eaac9
EC
387 desc.pc = pc;
388 phys_pc = get_page_addr_code(desc.env, pc);
7252f2de
PM
389 if (phys_pc == -1) {
390 return NULL;
391 }
909eaac9 392 desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
4e2ca83e 393 h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate);
61b8cef1 394 return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
9fd1a948
PB
395}
396
a8583393
RH
397void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr)
398{
399 if (TCG_TARGET_HAS_direct_jump) {
400 uintptr_t offset = tb->jmp_target_arg[n];
e7e168f4 401 uintptr_t tc_ptr = (uintptr_t)tb->tc.ptr;
1acbad0f
RH
402 uintptr_t jmp_rx = tc_ptr + offset;
403 uintptr_t jmp_rw = jmp_rx - tcg_splitwx_diff;
404 tb_target_set_jmp_target(tc_ptr, jmp_rx, jmp_rw, addr);
a8583393
RH
405 } else {
406 tb->jmp_target_arg[n] = addr;
407 }
408}
409
a8583393
RH
410static inline void tb_add_jump(TranslationBlock *tb, int n,
411 TranslationBlock *tb_next)
412{
194125e3
EC
413 uintptr_t old;
414
653b87eb 415 qemu_thread_jit_write();
a8583393 416 assert(n < ARRAY_SIZE(tb->jmp_list_next));
194125e3
EC
417 qemu_spin_lock(&tb_next->jmp_lock);
418
419 /* make sure the destination TB is valid */
420 if (tb_next->cflags & CF_INVALID) {
421 goto out_unlock_next;
422 }
423 /* Atomically claim the jump destination slot only if it was NULL */
d73415a3
SH
424 old = qatomic_cmpxchg(&tb->jmp_dest[n], (uintptr_t)NULL,
425 (uintptr_t)tb_next);
194125e3
EC
426 if (old) {
427 goto out_unlock_next;
a8583393 428 }
194125e3
EC
429
430 /* patch the native jump address */
431 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr);
432
433 /* add in TB jmp list */
434 tb->jmp_list_next[n] = tb_next->jmp_list_head;
435 tb_next->jmp_list_head = (uintptr_t)tb | n;
436
437 qemu_spin_unlock(&tb_next->jmp_lock);
438
a8583393
RH
439 qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
440 "Linking TBs %p [" TARGET_FMT_lx
441 "] index %d -> %p [" TARGET_FMT_lx "]\n",
e7e168f4
EC
442 tb->tc.ptr, tb->pc, n,
443 tb_next->tc.ptr, tb_next->pc);
194125e3 444 return;
a8583393 445
194125e3
EC
446 out_unlock_next:
447 qemu_spin_unlock(&tb_next->jmp_lock);
448 return;
a8583393
RH
449}
450
bd2710d5
SF
451static inline TranslationBlock *tb_find(CPUState *cpu,
452 TranslationBlock *last_tb,
9b990ee5 453 int tb_exit, uint32_t cf_mask)
8a40a180
FB
454{
455 TranslationBlock *tb;
456 target_ulong cs_base, pc;
89fee74a 457 uint32_t flags;
8a40a180 458
4e2ca83e 459 tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
f6bb84d5 460 if (tb == NULL) {
f6bb84d5 461 mmap_lock();
95590e24 462 tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask);
f6bb84d5 463 mmap_unlock();
bd2710d5 464 /* We add the TB in the virtual pc hash table for the fast lookup */
d73415a3 465 qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb);
8a40a180 466 }
c88c67e5
SF
467#ifndef CONFIG_USER_ONLY
468 /* We don't take care of direct jumps when address mapping changes in
469 * system emulation. So it's not safe to make a direct jump to a TB
470 * spanning two pages because the mapping for the second page can change.
471 */
472 if (tb->page_addr[1] != -1) {
4b7e6950 473 last_tb = NULL;
c88c67e5
SF
474 }
475#endif
a0522c7a 476 /* See if we can patch the calling TB. */
d7f425fd 477 if (last_tb) {
194125e3 478 tb_add_jump(last_tb, tb_exit, tb);
74d356dd 479 }
8a40a180
FB
480 return tb;
481}
482
8b2d34e9
SF
483static inline bool cpu_handle_halt(CPUState *cpu)
484{
485 if (cpu->halted) {
486#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
4084893d 487 if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
8b2d34e9 488 X86CPU *x86_cpu = X86_CPU(cpu);
8d04fb55 489 qemu_mutex_lock_iothread();
8b2d34e9
SF
490 apic_poll_irq(x86_cpu->apic_state);
491 cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
8d04fb55 492 qemu_mutex_unlock_iothread();
8b2d34e9
SF
493 }
494#endif
495 if (!cpu_has_work(cpu)) {
8b2d34e9
SF
496 return true;
497 }
498
499 cpu->halted = 0;
500 }
501
502 return false;
503}
504
ea284766 505static inline void cpu_handle_debug_exception(CPUState *cpu)
1009d2ed 506{
86025ee4 507 CPUClass *cc = CPU_GET_CLASS(cpu);
1009d2ed
JK
508 CPUWatchpoint *wp;
509
ff4700b0
AF
510 if (!cpu->watchpoint_hit) {
511 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1009d2ed
JK
512 wp->flags &= ~BP_WATCHPOINT_HIT;
513 }
514 }
86025ee4 515
78271684
CF
516 if (cc->tcg_ops->debug_excp_handler) {
517 cc->tcg_ops->debug_excp_handler(cpu);
710384d0 518 }
1009d2ed
JK
519}
520
ea284766
SF
521static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
522{
17b50b0c
PD
523 if (cpu->exception_index < 0) {
524#ifndef CONFIG_USER_ONLY
525 if (replay_has_exception()
5e140196 526 && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) {
17b50b0c
PD
527 /* try to cause an exception pending in the log */
528 cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true);
529 }
530#endif
531 if (cpu->exception_index < 0) {
532 return false;
533 }
534 }
535
536 if (cpu->exception_index >= EXCP_INTERRUPT) {
537 /* exit request from the cpu execution loop */
538 *ret = cpu->exception_index;
539 if (*ret == EXCP_DEBUG) {
540 cpu_handle_debug_exception(cpu);
541 }
542 cpu->exception_index = -1;
543 return true;
544 } else {
ea284766 545#if defined(CONFIG_USER_ONLY)
17b50b0c
PD
546 /* if user mode only, we simulate a fake exception
547 which will be handled outside the cpu execution
548 loop */
ea284766 549#if defined(TARGET_I386)
17b50b0c 550 CPUClass *cc = CPU_GET_CLASS(cpu);
78271684 551 cc->tcg_ops->do_interrupt(cpu);
17b50b0c
PD
552#endif
553 *ret = cpu->exception_index;
554 cpu->exception_index = -1;
555 return true;
556#else
557 if (replay_exception()) {
ea284766 558 CPUClass *cc = CPU_GET_CLASS(cpu);
17b50b0c 559 qemu_mutex_lock_iothread();
78271684 560 cc->tcg_ops->do_interrupt(cpu);
17b50b0c 561 qemu_mutex_unlock_iothread();
ea284766 562 cpu->exception_index = -1;
a7ba744f
LM
563
564 if (unlikely(cpu->singlestep_enabled)) {
565 /*
566 * After processing the exception, ensure an EXCP_DEBUG is
567 * raised when single-stepping so that GDB doesn't miss the
568 * next instruction.
569 */
570 *ret = EXCP_DEBUG;
571 cpu_handle_debug_exception(cpu);
572 return true;
573 }
17b50b0c
PD
574 } else if (!replay_has_interrupt()) {
575 /* give a chance to iothread in replay mode */
576 *ret = EXCP_INTERRUPT;
ea284766 577 return true;
ea284766 578 }
ea284766
SF
579#endif
580 }
581
582 return false;
583}
584
4084893d
PD
585/*
586 * CPU_INTERRUPT_POLL is a virtual event which gets converted into a
587 * "real" interrupt event later. It does not need to be recorded for
588 * replay purposes.
589 */
590static inline bool need_replay_interrupt(int interrupt_request)
591{
592#if defined(TARGET_I386)
593 return !(interrupt_request & CPU_INTERRUPT_POLL);
594#else
595 return true;
596#endif
597}
598
209b71b6 599static inline bool cpu_handle_interrupt(CPUState *cpu,
c385e6e4
SF
600 TranslationBlock **last_tb)
601{
602 CPUClass *cc = CPU_GET_CLASS(cpu);
17b50b0c
PD
603
604 /* Clear the interrupt flag now since we're processing
605 * cpu->interrupt_request and cpu->exit_request.
d84be02d
DH
606 * Ensure zeroing happens before reading cpu->exit_request or
607 * cpu->interrupt_request (see also smp_wmb in cpu_exit())
17b50b0c 608 */
d73415a3 609 qatomic_mb_set(&cpu_neg(cpu)->icount_decr.u16.high, 0);
c385e6e4 610
d73415a3 611 if (unlikely(qatomic_read(&cpu->interrupt_request))) {
8d04fb55
JK
612 int interrupt_request;
613 qemu_mutex_lock_iothread();
614 interrupt_request = cpu->interrupt_request;
c385e6e4
SF
615 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
616 /* Mask out external interrupts for this step. */
617 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
618 }
619 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
620 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
621 cpu->exception_index = EXCP_DEBUG;
8d04fb55 622 qemu_mutex_unlock_iothread();
209b71b6 623 return true;
c385e6e4
SF
624 }
625 if (replay_mode == REPLAY_MODE_PLAY && !replay_has_interrupt()) {
626 /* Do nothing */
627 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
628 replay_interrupt();
629 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
630 cpu->halted = 1;
631 cpu->exception_index = EXCP_HLT;
8d04fb55 632 qemu_mutex_unlock_iothread();
209b71b6 633 return true;
c385e6e4
SF
634 }
635#if defined(TARGET_I386)
636 else if (interrupt_request & CPU_INTERRUPT_INIT) {
637 X86CPU *x86_cpu = X86_CPU(cpu);
638 CPUArchState *env = &x86_cpu->env;
639 replay_interrupt();
65c9d60a 640 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0);
c385e6e4
SF
641 do_cpu_init(x86_cpu);
642 cpu->exception_index = EXCP_HALTED;
8d04fb55 643 qemu_mutex_unlock_iothread();
209b71b6 644 return true;
c385e6e4
SF
645 }
646#else
647 else if (interrupt_request & CPU_INTERRUPT_RESET) {
648 replay_interrupt();
649 cpu_reset(cpu);
8d04fb55 650 qemu_mutex_unlock_iothread();
209b71b6 651 return true;
c385e6e4
SF
652 }
653#endif
654 /* The target hook has 3 exit conditions:
655 False when the interrupt isn't processed,
656 True when it is, and we should restart on a new TB,
657 and via longjmp via cpu_loop_exit. */
658 else {
78271684
CF
659 if (cc->tcg_ops->cpu_exec_interrupt &&
660 cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
4084893d
PD
661 if (need_replay_interrupt(interrupt_request)) {
662 replay_interrupt();
663 }
ba3c35d9
RH
664 /*
665 * After processing the interrupt, ensure an EXCP_DEBUG is
666 * raised when single-stepping so that GDB doesn't miss the
667 * next instruction.
668 */
669 cpu->exception_index =
670 (cpu->singlestep_enabled ? EXCP_DEBUG : -1);
c385e6e4
SF
671 *last_tb = NULL;
672 }
8b1fe3f4
SF
673 /* The target hook may have updated the 'cpu->interrupt_request';
674 * reload the 'interrupt_request' value */
675 interrupt_request = cpu->interrupt_request;
c385e6e4 676 }
8b1fe3f4 677 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
c385e6e4
SF
678 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
679 /* ensure that no TB jump will be modified as
680 the program flow was changed */
681 *last_tb = NULL;
682 }
8d04fb55
JK
683
684 /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */
685 qemu_mutex_unlock_iothread();
c385e6e4 686 }
8d04fb55 687
cfb2d02b 688 /* Finally, check if we need to exit to the main loop. */
d73415a3 689 if (unlikely(qatomic_read(&cpu->exit_request))
740b1759 690 || (icount_enabled()
5e140196 691 && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0)) {
d73415a3 692 qatomic_set(&cpu->exit_request, 0);
5f3bdfd4
PD
693 if (cpu->exception_index == -1) {
694 cpu->exception_index = EXCP_INTERRUPT;
695 }
209b71b6 696 return true;
c385e6e4 697 }
209b71b6
PB
698
699 return false;
c385e6e4
SF
700}
701
928de9ee 702static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
cfb2d02b 703 TranslationBlock **last_tb, int *tb_exit)
928de9ee 704{
1aab16c2 705 int32_t insns_left;
928de9ee
SF
706
707 trace_exec_tb(tb, tb->pc);
eba40358 708 tb = cpu_tb_exec(cpu, tb, tb_exit);
1aab16c2
PB
709 if (*tb_exit != TB_EXIT_REQUESTED) {
710 *last_tb = tb;
711 return;
712 }
713
714 *last_tb = NULL;
d73415a3 715 insns_left = qatomic_read(&cpu_neg(cpu)->icount_decr.u32);
1aab16c2 716 if (insns_left < 0) {
e5143e30
AB
717 /* Something asked us to stop executing chained TBs; just
718 * continue round the main loop. Whatever requested the exit
30f3dda2 719 * will also have set something else (eg exit_request or
17b50b0c
PD
720 * interrupt_request) which will be handled by
721 * cpu_handle_interrupt. cpu_handle_interrupt will also
722 * clear cpu->icount_decr.u16.high.
928de9ee 723 */
1aab16c2 724 return;
928de9ee 725 }
1aab16c2
PB
726
727 /* Instruction counter expired. */
740b1759 728 assert(icount_enabled());
1aab16c2 729#ifndef CONFIG_USER_ONLY
eda5f7c6 730 /* Ensure global icount has gone forward */
8191d368 731 icount_update(cpu);
eda5f7c6 732 /* Refill decrementer and continue execution. */
bc662a33 733 insns_left = MIN(CF_COUNT_MASK, cpu->icount_budget);
5e140196 734 cpu_neg(cpu)->icount_decr.u16.low = insns_left;
eda5f7c6 735 cpu->icount_extra = cpu->icount_budget - insns_left;
bc662a33
AB
736
737 /*
738 * If the next tb has more instructions than we have left to
739 * execute we need to ensure we find/generate a TB with exactly
740 * insns_left instructions in it.
741 */
742 if (!cpu->icount_extra && insns_left > 0 && insns_left < tb->icount) {
743 cpu->cflags_next_tb = (tb->cflags & ~CF_COUNT_MASK) | insns_left;
928de9ee 744 }
1aab16c2 745#endif
928de9ee
SF
746}
747
7d13299d
FB
748/* main execution loop */
749
ea3e9847 750int cpu_exec(CPUState *cpu)
7d13299d 751{
97a8ea5a 752 CPUClass *cc = CPU_GET_CLASS(cpu);
c385e6e4 753 int ret;
cfb2d02b 754 SyncClocks sc = { 0 };
c2aa5f81 755
6f060969
PD
756 /* replay_interrupt may need current_cpu */
757 current_cpu = cpu;
758
8b2d34e9
SF
759 if (cpu_handle_halt(cpu)) {
760 return EXCP_HALTED;
eda48c34 761 }
5a1e3cfc 762
79e2b9ae
PB
763 rcu_read_lock();
764
035ba06c 765 cpu_exec_enter(cpu);
9d27abd9 766
c2aa5f81
ST
767 /* Calculate difference between guest clock and host clock.
768 * This delay includes the delay of the last cycle, so
769 * what we have to do is sleep until it is 0. As for the
770 * advance/delay we gain here, we try to fix it next time.
771 */
772 init_delay_params(&sc, cpu);
773
4515e58d
PB
774 /* prepare setjmp context for exception handling */
775 if (sigsetjmp(cpu->jmp_env, 0) != 0) {
19a84318 776#if defined(__clang__)
e6a41a04
PM
777 /*
778 * Some compilers wrongly smash all local variables after
779 * siglongjmp (the spec requires that only non-volatile locals
780 * which are changed between the sigsetjmp and siglongjmp are
781 * permitted to be trashed). There were bug reports for gcc
782 * 4.5.0 and clang. The bug is fixed in all versions of gcc
783 * that we support, but is still unfixed in clang:
784 * https://bugs.llvm.org/show_bug.cgi?id=21183
785 *
4515e58d 786 * Reload essential local variables here for those compilers.
e6a41a04
PM
787 * Newer versions of gcc would complain about this code (-Wclobbered),
788 * so we only perform the workaround for clang.
789 */
4515e58d
PB
790 cpu = current_cpu;
791 cc = CPU_GET_CLASS(cpu);
e6a41a04
PM
792#else
793 /*
794 * Non-buggy compilers preserve these locals; assert that
795 * they have the correct value.
796 */
4515e58d
PB
797 g_assert(cpu == current_cpu);
798 g_assert(cc == CPU_GET_CLASS(cpu));
e6a41a04
PM
799#endif
800
0ac20318
EC
801#ifndef CONFIG_SOFTMMU
802 tcg_debug_assert(!have_mmap_lock());
803#endif
8d04fb55
JK
804 if (qemu_mutex_iothread_locked()) {
805 qemu_mutex_unlock_iothread();
806 }
e6d86bed
EC
807 qemu_plugin_disable_mem_helpers(cpu);
808
8fd3a9b8 809 assert_no_pages_locked();
4515e58d
PB
810 }
811
812 /* if an exception is pending, we execute it here */
813 while (!cpu_handle_exception(cpu, &ret)) {
814 TranslationBlock *last_tb = NULL;
815 int tb_exit = 0;
816
817 while (!cpu_handle_interrupt(cpu, &last_tb)) {
9b990ee5
RH
818 uint32_t cflags = cpu->cflags_next_tb;
819 TranslationBlock *tb;
820
821 /* When requested, use an exact setting for cflags for the next
822 execution. This is used for icount, precise smc, and stop-
823 after-access watchpoints. Since this request should never
824 have CF_INVALID set, -1 is a convenient invalid value that
825 does not require tcg headers for cpu_common_reset. */
826 if (cflags == -1) {
827 cflags = curr_cflags();
828 } else {
829 cpu->cflags_next_tb = -1;
830 }
831
832 tb = tb_find(cpu, last_tb, tb_exit, cflags);
cfb2d02b 833 cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit);
4515e58d
PB
834 /* Try to align the host and virtual clocks
835 if the guest is in advance */
836 align_clocks(&sc, cpu);
7d13299d 837 }
4515e58d 838 }
3fb2ded1 839
035ba06c 840 cpu_exec_exit(cpu);
79e2b9ae 841 rcu_read_unlock();
1057eaa7 842
7d13299d
FB
843 return ret;
844}
740b1759 845
7df5e3d6
CF
846void tcg_exec_realizefn(CPUState *cpu, Error **errp)
847{
848 static bool tcg_target_initialized;
849 CPUClass *cc = CPU_GET_CLASS(cpu);
850
851 if (!tcg_target_initialized) {
78271684 852 cc->tcg_ops->initialize();
7df5e3d6
CF
853 tcg_target_initialized = true;
854 }
855 tlb_init(cpu);
856 qemu_plugin_vcpu_init_hook(cpu);
857
858#ifndef CONFIG_USER_ONLY
859 tcg_iommu_init_notifier_list(cpu);
860#endif /* !CONFIG_USER_ONLY */
861}
862
863/* undo the initializations in reverse order */
864void tcg_exec_unrealizefn(CPUState *cpu)
865{
866#ifndef CONFIG_USER_ONLY
867 tcg_iommu_free_notifier_list(cpu);
868#endif /* !CONFIG_USER_ONLY */
869
870 qemu_plugin_vcpu_exit_hook(cpu);
871 tlb_destroy(cpu);
872}
873
740b1759
CF
874#ifndef CONFIG_USER_ONLY
875
876void dump_drift_info(void)
877{
878 if (!icount_enabled()) {
879 return;
880 }
881
882 qemu_printf("Host - Guest clock %"PRIi64" ms\n",
8191d368 883 (cpu_get_clock() - icount_get()) / SCALE_MS);
740b1759
CF
884 if (icount_align_option) {
885 qemu_printf("Max guest delay %"PRIi64" ms\n",
886 -max_delay / SCALE_MS);
887 qemu_printf("Max guest advance %"PRIi64" ms\n",
888 max_advance / SCALE_MS);
889 } else {
890 qemu_printf("Max guest delay NA\n");
891 qemu_printf("Max guest advance NA\n");
892 }
893}
894
895#endif /* !CONFIG_USER_ONLY */