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Commit | Line | Data |
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0cac1b66 BS |
1 | /* |
2 | * Common CPU TLB handling | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
fb0343d5 | 9 | * version 2.1 of the License, or (at your option) any later version. |
0cac1b66 BS |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
7b31bbc2 | 20 | #include "qemu/osdep.h" |
8d04fb55 | 21 | #include "qemu/main-loop.h" |
78271684 | 22 | #include "hw/core/tcg-cpu-ops.h" |
022c62cb PB |
23 | #include "exec/exec-all.h" |
24 | #include "exec/memory.h" | |
f08b6170 | 25 | #include "exec/cpu_ldst.h" |
022c62cb | 26 | #include "exec/cputlb.h" |
022c62cb | 27 | #include "exec/memory-internal.h" |
220c3ebd | 28 | #include "exec/ram_addr.h" |
0f590e74 | 29 | #include "tcg/tcg.h" |
d7f30403 PM |
30 | #include "qemu/error-report.h" |
31 | #include "exec/log.h" | |
c213ee2d | 32 | #include "exec/helper-proto-common.h" |
c482cb11 | 33 | #include "qemu/atomic.h" |
e6cd4bb5 | 34 | #include "qemu/atomic128.h" |
3b9bd3f4 | 35 | #include "exec/translate-all.h" |
51807763 | 36 | #include "trace.h" |
e5ceadff | 37 | #include "tb-hash.h" |
65269192 | 38 | #include "internal.h" |
235537fa AB |
39 | #ifdef CONFIG_PLUGIN |
40 | #include "qemu/plugin-memory.h" | |
41 | #endif | |
d2ba8026 | 42 | #include "tcg/tcg-ldst.h" |
70f168f8 | 43 | #include "tcg/oversized-guest.h" |
0cac1b66 | 44 | |
8526e1f4 AB |
45 | /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ |
46 | /* #define DEBUG_TLB */ | |
47 | /* #define DEBUG_TLB_LOG */ | |
48 | ||
49 | #ifdef DEBUG_TLB | |
50 | # define DEBUG_TLB_GATE 1 | |
51 | # ifdef DEBUG_TLB_LOG | |
52 | # define DEBUG_TLB_LOG_GATE 1 | |
53 | # else | |
54 | # define DEBUG_TLB_LOG_GATE 0 | |
55 | # endif | |
56 | #else | |
57 | # define DEBUG_TLB_GATE 0 | |
58 | # define DEBUG_TLB_LOG_GATE 0 | |
59 | #endif | |
60 | ||
61 | #define tlb_debug(fmt, ...) do { \ | |
62 | if (DEBUG_TLB_LOG_GATE) { \ | |
63 | qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \ | |
64 | ## __VA_ARGS__); \ | |
65 | } else if (DEBUG_TLB_GATE) { \ | |
66 | fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ | |
67 | } \ | |
68 | } while (0) | |
0cac1b66 | 69 | |
ea9025cb | 70 | #define assert_cpu_is_self(cpu) do { \ |
f0aff0f1 | 71 | if (DEBUG_TLB_GATE) { \ |
ea9025cb | 72 | g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \ |
f0aff0f1 AB |
73 | } \ |
74 | } while (0) | |
75 | ||
e3b9ca81 FK |
76 | /* run_on_cpu_data.target_ptr should always be big enough for a |
77 | * target_ulong even on 32 bit builds */ | |
78 | QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data)); | |
79 | ||
e7218445 AB |
80 | /* We currently can't handle more than 16 bits in the MMUIDX bitmask. |
81 | */ | |
82 | QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); | |
83 | #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1) | |
84 | ||
722a1c1e | 85 | static inline size_t tlb_n_entries(CPUTLBDescFast *fast) |
7a1efe1b | 86 | { |
722a1c1e | 87 | return (fast->mask >> CPU_TLB_ENTRY_BITS) + 1; |
7a1efe1b RH |
88 | } |
89 | ||
722a1c1e | 90 | static inline size_t sizeof_tlb(CPUTLBDescFast *fast) |
86e1eff8 | 91 | { |
722a1c1e | 92 | return fast->mask + (1 << CPU_TLB_ENTRY_BITS); |
86e1eff8 EC |
93 | } |
94 | ||
79e42085 | 95 | static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, |
86e1eff8 EC |
96 | size_t max_entries) |
97 | { | |
79e42085 RH |
98 | desc->window_begin_ns = ns; |
99 | desc->window_max_entries = max_entries; | |
86e1eff8 EC |
100 | } |
101 | ||
06f3831c | 102 | static void tb_jmp_cache_clear_page(CPUState *cpu, vaddr page_addr) |
0f4abea8 | 103 | { |
a976a99a | 104 | CPUJumpCache *jc = cpu->tb_jmp_cache; |
99ab4d50 | 105 | int i, i0; |
0f4abea8 | 106 | |
99ab4d50 EA |
107 | if (unlikely(!jc)) { |
108 | return; | |
109 | } | |
110 | ||
111 | i0 = tb_jmp_cache_hash_page(page_addr); | |
0f4abea8 | 112 | for (i = 0; i < TB_JMP_PAGE_SIZE; i++) { |
a976a99a | 113 | qatomic_set(&jc->array[i0 + i].tb, NULL); |
0f4abea8 RH |
114 | } |
115 | } | |
116 | ||
86e1eff8 EC |
117 | /** |
118 | * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary | |
71ccd47b RH |
119 | * @desc: The CPUTLBDesc portion of the TLB |
120 | * @fast: The CPUTLBDescFast portion of the same TLB | |
86e1eff8 EC |
121 | * |
122 | * Called with tlb_lock_held. | |
123 | * | |
124 | * We have two main constraints when resizing a TLB: (1) we only resize it | |
125 | * on a TLB flush (otherwise we'd have to take a perf hit by either rehashing | |
126 | * the array or unnecessarily flushing it), which means we do not control how | |
127 | * frequently the resizing can occur; (2) we don't have access to the guest's | |
128 | * future scheduling decisions, and therefore have to decide the magnitude of | |
129 | * the resize based on past observations. | |
130 | * | |
131 | * In general, a memory-hungry process can benefit greatly from an appropriately | |
132 | * sized TLB, since a guest TLB miss is very expensive. This doesn't mean that | |
133 | * we just have to make the TLB as large as possible; while an oversized TLB | |
134 | * results in minimal TLB miss rates, it also takes longer to be flushed | |
135 | * (flushes can be _very_ frequent), and the reduced locality can also hurt | |
136 | * performance. | |
137 | * | |
138 | * To achieve near-optimal performance for all kinds of workloads, we: | |
139 | * | |
140 | * 1. Aggressively increase the size of the TLB when the use rate of the | |
141 | * TLB being flushed is high, since it is likely that in the near future this | |
142 | * memory-hungry process will execute again, and its memory hungriness will | |
143 | * probably be similar. | |
144 | * | |
145 | * 2. Slowly reduce the size of the TLB as the use rate declines over a | |
146 | * reasonably large time window. The rationale is that if in such a time window | |
147 | * we have not observed a high TLB use rate, it is likely that we won't observe | |
148 | * it in the near future. In that case, once a time window expires we downsize | |
149 | * the TLB to match the maximum use rate observed in the window. | |
150 | * | |
151 | * 3. Try to keep the maximum use rate in a time window in the 30-70% range, | |
152 | * since in that range performance is likely near-optimal. Recall that the TLB | |
153 | * is direct mapped, so we want the use rate to be low (or at least not too | |
154 | * high), since otherwise we are likely to have a significant amount of | |
155 | * conflict misses. | |
156 | */ | |
3c3959f2 RH |
157 | static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast, |
158 | int64_t now) | |
86e1eff8 | 159 | { |
71ccd47b | 160 | size_t old_size = tlb_n_entries(fast); |
86e1eff8 EC |
161 | size_t rate; |
162 | size_t new_size = old_size; | |
86e1eff8 EC |
163 | int64_t window_len_ms = 100; |
164 | int64_t window_len_ns = window_len_ms * 1000 * 1000; | |
79e42085 | 165 | bool window_expired = now > desc->window_begin_ns + window_len_ns; |
86e1eff8 | 166 | |
79e42085 RH |
167 | if (desc->n_used_entries > desc->window_max_entries) { |
168 | desc->window_max_entries = desc->n_used_entries; | |
86e1eff8 | 169 | } |
79e42085 | 170 | rate = desc->window_max_entries * 100 / old_size; |
86e1eff8 EC |
171 | |
172 | if (rate > 70) { | |
173 | new_size = MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS); | |
174 | } else if (rate < 30 && window_expired) { | |
79e42085 RH |
175 | size_t ceil = pow2ceil(desc->window_max_entries); |
176 | size_t expected_rate = desc->window_max_entries * 100 / ceil; | |
86e1eff8 EC |
177 | |
178 | /* | |
179 | * Avoid undersizing when the max number of entries seen is just below | |
180 | * a pow2. For instance, if max_entries == 1025, the expected use rate | |
181 | * would be 1025/2048==50%. However, if max_entries == 1023, we'd get | |
182 | * 1023/1024==99.9% use rate, so we'd likely end up doubling the size | |
183 | * later. Thus, make sure that the expected use rate remains below 70%. | |
184 | * (and since we double the size, that means the lowest rate we'd | |
185 | * expect to get is 35%, which is still in the 30-70% range where | |
186 | * we consider that the size is appropriate.) | |
187 | */ | |
188 | if (expected_rate > 70) { | |
189 | ceil *= 2; | |
190 | } | |
191 | new_size = MAX(ceil, 1 << CPU_TLB_DYN_MIN_BITS); | |
192 | } | |
193 | ||
194 | if (new_size == old_size) { | |
195 | if (window_expired) { | |
79e42085 | 196 | tlb_window_reset(desc, now, desc->n_used_entries); |
86e1eff8 EC |
197 | } |
198 | return; | |
199 | } | |
200 | ||
71ccd47b | 201 | g_free(fast->table); |
25d3ec58 | 202 | g_free(desc->fulltlb); |
86e1eff8 | 203 | |
79e42085 | 204 | tlb_window_reset(desc, now, 0); |
86e1eff8 | 205 | /* desc->n_used_entries is cleared by the caller */ |
71ccd47b RH |
206 | fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS; |
207 | fast->table = g_try_new(CPUTLBEntry, new_size); | |
25d3ec58 | 208 | desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size); |
71ccd47b | 209 | |
86e1eff8 EC |
210 | /* |
211 | * If the allocations fail, try smaller sizes. We just freed some | |
212 | * memory, so going back to half of new_size has a good chance of working. | |
213 | * Increased memory pressure elsewhere in the system might cause the | |
214 | * allocations to fail though, so we progressively reduce the allocation | |
215 | * size, aborting if we cannot even allocate the smallest TLB we support. | |
216 | */ | |
25d3ec58 | 217 | while (fast->table == NULL || desc->fulltlb == NULL) { |
86e1eff8 EC |
218 | if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) { |
219 | error_report("%s: %s", __func__, strerror(errno)); | |
220 | abort(); | |
221 | } | |
222 | new_size = MAX(new_size >> 1, 1 << CPU_TLB_DYN_MIN_BITS); | |
71ccd47b | 223 | fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS; |
86e1eff8 | 224 | |
71ccd47b | 225 | g_free(fast->table); |
25d3ec58 | 226 | g_free(desc->fulltlb); |
71ccd47b | 227 | fast->table = g_try_new(CPUTLBEntry, new_size); |
25d3ec58 | 228 | desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size); |
86e1eff8 EC |
229 | } |
230 | } | |
231 | ||
bbf021b0 | 232 | static void tlb_mmu_flush_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast) |
86e1eff8 | 233 | { |
5c948e31 RH |
234 | desc->n_used_entries = 0; |
235 | desc->large_page_addr = -1; | |
236 | desc->large_page_mask = -1; | |
237 | desc->vindex = 0; | |
238 | memset(fast->table, -1, sizeof_tlb(fast)); | |
239 | memset(desc->vtable, -1, sizeof(desc->vtable)); | |
86e1eff8 EC |
240 | } |
241 | ||
3c3959f2 RH |
242 | static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx, |
243 | int64_t now) | |
bbf021b0 RH |
244 | { |
245 | CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx]; | |
246 | CPUTLBDescFast *fast = &env_tlb(env)->f[mmu_idx]; | |
247 | ||
3c3959f2 | 248 | tlb_mmu_resize_locked(desc, fast, now); |
bbf021b0 RH |
249 | tlb_mmu_flush_locked(desc, fast); |
250 | } | |
251 | ||
56e89f76 RH |
252 | static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now) |
253 | { | |
254 | size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS; | |
255 | ||
256 | tlb_window_reset(desc, now, 0); | |
257 | desc->n_used_entries = 0; | |
258 | fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS; | |
259 | fast->table = g_new(CPUTLBEntry, n_entries); | |
25d3ec58 | 260 | desc->fulltlb = g_new(CPUTLBEntryFull, n_entries); |
3c16304a | 261 | tlb_mmu_flush_locked(desc, fast); |
56e89f76 RH |
262 | } |
263 | ||
86e1eff8 EC |
264 | static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx) |
265 | { | |
a40ec84e | 266 | env_tlb(env)->d[mmu_idx].n_used_entries++; |
86e1eff8 EC |
267 | } |
268 | ||
269 | static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu_idx) | |
270 | { | |
a40ec84e | 271 | env_tlb(env)->d[mmu_idx].n_used_entries--; |
86e1eff8 EC |
272 | } |
273 | ||
5005e253 EC |
274 | void tlb_init(CPUState *cpu) |
275 | { | |
71aec354 | 276 | CPUArchState *env = cpu->env_ptr; |
56e89f76 RH |
277 | int64_t now = get_clock_realtime(); |
278 | int i; | |
71aec354 | 279 | |
a40ec84e | 280 | qemu_spin_init(&env_tlb(env)->c.lock); |
3d1523ce | 281 | |
3c16304a RH |
282 | /* All tlbs are initialized flushed. */ |
283 | env_tlb(env)->c.dirty = 0; | |
86e1eff8 | 284 | |
56e89f76 RH |
285 | for (i = 0; i < NB_MMU_MODES; i++) { |
286 | tlb_mmu_init(&env_tlb(env)->d[i], &env_tlb(env)->f[i], now); | |
287 | } | |
5005e253 EC |
288 | } |
289 | ||
816d9be5 EC |
290 | void tlb_destroy(CPUState *cpu) |
291 | { | |
292 | CPUArchState *env = cpu->env_ptr; | |
293 | int i; | |
294 | ||
295 | qemu_spin_destroy(&env_tlb(env)->c.lock); | |
296 | for (i = 0; i < NB_MMU_MODES; i++) { | |
297 | CPUTLBDesc *desc = &env_tlb(env)->d[i]; | |
298 | CPUTLBDescFast *fast = &env_tlb(env)->f[i]; | |
299 | ||
300 | g_free(fast->table); | |
25d3ec58 | 301 | g_free(desc->fulltlb); |
816d9be5 EC |
302 | } |
303 | } | |
304 | ||
c3b9a07a AB |
305 | /* flush_all_helper: run fn across all cpus |
306 | * | |
307 | * If the wait flag is set then the src cpu's helper will be queued as | |
308 | * "safe" work and the loop exited creating a synchronisation point | |
309 | * where all queued work will be finished before execution starts | |
310 | * again. | |
311 | */ | |
312 | static void flush_all_helper(CPUState *src, run_on_cpu_func fn, | |
313 | run_on_cpu_data d) | |
314 | { | |
315 | CPUState *cpu; | |
316 | ||
317 | CPU_FOREACH(cpu) { | |
318 | if (cpu != src) { | |
319 | async_run_on_cpu(cpu, fn, d); | |
320 | } | |
321 | } | |
322 | } | |
323 | ||
e09de0a2 | 324 | void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide) |
83974cf4 EC |
325 | { |
326 | CPUState *cpu; | |
e09de0a2 | 327 | size_t full = 0, part = 0, elide = 0; |
83974cf4 EC |
328 | |
329 | CPU_FOREACH(cpu) { | |
330 | CPUArchState *env = cpu->env_ptr; | |
331 | ||
d73415a3 SH |
332 | full += qatomic_read(&env_tlb(env)->c.full_flush_count); |
333 | part += qatomic_read(&env_tlb(env)->c.part_flush_count); | |
334 | elide += qatomic_read(&env_tlb(env)->c.elide_flush_count); | |
83974cf4 | 335 | } |
e09de0a2 RH |
336 | *pfull = full; |
337 | *ppart = part; | |
338 | *pelide = elide; | |
83974cf4 | 339 | } |
0cac1b66 | 340 | |
e7218445 | 341 | static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) |
d7a74a9d PM |
342 | { |
343 | CPUArchState *env = cpu->env_ptr; | |
3d1523ce RH |
344 | uint16_t asked = data.host_int; |
345 | uint16_t all_dirty, work, to_clean; | |
3c3959f2 | 346 | int64_t now = get_clock_realtime(); |
d7a74a9d | 347 | |
f0aff0f1 | 348 | assert_cpu_is_self(cpu); |
d7a74a9d | 349 | |
3d1523ce | 350 | tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked); |
e7218445 | 351 | |
a40ec84e | 352 | qemu_spin_lock(&env_tlb(env)->c.lock); |
60a2ad7d | 353 | |
a40ec84e | 354 | all_dirty = env_tlb(env)->c.dirty; |
3d1523ce RH |
355 | to_clean = asked & all_dirty; |
356 | all_dirty &= ~to_clean; | |
a40ec84e | 357 | env_tlb(env)->c.dirty = all_dirty; |
3d1523ce RH |
358 | |
359 | for (work = to_clean; work != 0; work &= work - 1) { | |
360 | int mmu_idx = ctz32(work); | |
3c3959f2 | 361 | tlb_flush_one_mmuidx_locked(env, mmu_idx, now); |
d7a74a9d | 362 | } |
3d1523ce | 363 | |
a40ec84e | 364 | qemu_spin_unlock(&env_tlb(env)->c.lock); |
d7a74a9d | 365 | |
a976a99a | 366 | tcg_flush_jmp_cache(cpu); |
64f2674b | 367 | |
3d1523ce | 368 | if (to_clean == ALL_MMUIDX_BITS) { |
d73415a3 | 369 | qatomic_set(&env_tlb(env)->c.full_flush_count, |
a40ec84e | 370 | env_tlb(env)->c.full_flush_count + 1); |
e09de0a2 | 371 | } else { |
d73415a3 | 372 | qatomic_set(&env_tlb(env)->c.part_flush_count, |
a40ec84e | 373 | env_tlb(env)->c.part_flush_count + ctpop16(to_clean)); |
3d1523ce | 374 | if (to_clean != asked) { |
d73415a3 | 375 | qatomic_set(&env_tlb(env)->c.elide_flush_count, |
a40ec84e | 376 | env_tlb(env)->c.elide_flush_count + |
3d1523ce RH |
377 | ctpop16(asked & ~to_clean)); |
378 | } | |
64f2674b | 379 | } |
d7a74a9d PM |
380 | } |
381 | ||
0336cbf8 | 382 | void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) |
d7a74a9d | 383 | { |
e7218445 AB |
384 | tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap); |
385 | ||
64f2674b | 386 | if (cpu->created && !qemu_cpu_is_self(cpu)) { |
ab651105 RH |
387 | async_run_on_cpu(cpu, tlb_flush_by_mmuidx_async_work, |
388 | RUN_ON_CPU_HOST_INT(idxmap)); | |
e7218445 | 389 | } else { |
60a2ad7d | 390 | tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(idxmap)); |
e7218445 | 391 | } |
d7a74a9d PM |
392 | } |
393 | ||
64f2674b RH |
394 | void tlb_flush(CPUState *cpu) |
395 | { | |
396 | tlb_flush_by_mmuidx(cpu, ALL_MMUIDX_BITS); | |
397 | } | |
398 | ||
c3b9a07a AB |
399 | void tlb_flush_by_mmuidx_all_cpus(CPUState *src_cpu, uint16_t idxmap) |
400 | { | |
401 | const run_on_cpu_func fn = tlb_flush_by_mmuidx_async_work; | |
402 | ||
403 | tlb_debug("mmu_idx: 0x%"PRIx16"\n", idxmap); | |
404 | ||
405 | flush_all_helper(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap)); | |
406 | fn(src_cpu, RUN_ON_CPU_HOST_INT(idxmap)); | |
407 | } | |
408 | ||
64f2674b RH |
409 | void tlb_flush_all_cpus(CPUState *src_cpu) |
410 | { | |
411 | tlb_flush_by_mmuidx_all_cpus(src_cpu, ALL_MMUIDX_BITS); | |
412 | } | |
413 | ||
414 | void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxmap) | |
c3b9a07a AB |
415 | { |
416 | const run_on_cpu_func fn = tlb_flush_by_mmuidx_async_work; | |
417 | ||
418 | tlb_debug("mmu_idx: 0x%"PRIx16"\n", idxmap); | |
419 | ||
420 | flush_all_helper(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap)); | |
421 | async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap)); | |
422 | } | |
423 | ||
64f2674b RH |
424 | void tlb_flush_all_cpus_synced(CPUState *src_cpu) |
425 | { | |
426 | tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS); | |
427 | } | |
428 | ||
3ab6e68c | 429 | static bool tlb_hit_page_mask_anyprot(CPUTLBEntry *tlb_entry, |
732d5487 | 430 | vaddr page, vaddr mask) |
3ab6e68c RH |
431 | { |
432 | page &= mask; | |
433 | mask &= TARGET_PAGE_MASK | TLB_INVALID_MASK; | |
434 | ||
435 | return (page == (tlb_entry->addr_read & mask) || | |
436 | page == (tlb_addr_write(tlb_entry) & mask) || | |
437 | page == (tlb_entry->addr_code & mask)); | |
438 | } | |
439 | ||
732d5487 | 440 | static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry, vaddr page) |
68fea038 | 441 | { |
3ab6e68c | 442 | return tlb_hit_page_mask_anyprot(tlb_entry, page, -1); |
68fea038 | 443 | } |
c3b9a07a | 444 | |
3cea94bb EC |
445 | /** |
446 | * tlb_entry_is_empty - return true if the entry is not in use | |
447 | * @te: pointer to CPUTLBEntry | |
448 | */ | |
449 | static inline bool tlb_entry_is_empty(const CPUTLBEntry *te) | |
450 | { | |
451 | return te->addr_read == -1 && te->addr_write == -1 && te->addr_code == -1; | |
452 | } | |
453 | ||
53d28455 | 454 | /* Called with tlb_c.lock held */ |
3ab6e68c | 455 | static bool tlb_flush_entry_mask_locked(CPUTLBEntry *tlb_entry, |
732d5487 AJ |
456 | vaddr page, |
457 | vaddr mask) | |
0cac1b66 | 458 | { |
3ab6e68c | 459 | if (tlb_hit_page_mask_anyprot(tlb_entry, page, mask)) { |
4fadb3bb | 460 | memset(tlb_entry, -1, sizeof(*tlb_entry)); |
86e1eff8 | 461 | return true; |
0cac1b66 | 462 | } |
86e1eff8 | 463 | return false; |
0cac1b66 BS |
464 | } |
465 | ||
732d5487 | 466 | static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, vaddr page) |
3ab6e68c RH |
467 | { |
468 | return tlb_flush_entry_mask_locked(tlb_entry, page, -1); | |
469 | } | |
470 | ||
53d28455 | 471 | /* Called with tlb_c.lock held */ |
3ab6e68c | 472 | static void tlb_flush_vtlb_page_mask_locked(CPUArchState *env, int mmu_idx, |
732d5487 AJ |
473 | vaddr page, |
474 | vaddr mask) | |
68fea038 | 475 | { |
a40ec84e | 476 | CPUTLBDesc *d = &env_tlb(env)->d[mmu_idx]; |
68fea038 | 477 | int k; |
71aec354 | 478 | |
29a0af61 | 479 | assert_cpu_is_self(env_cpu(env)); |
68fea038 | 480 | for (k = 0; k < CPU_VTLB_SIZE; k++) { |
3ab6e68c | 481 | if (tlb_flush_entry_mask_locked(&d->vtable[k], page, mask)) { |
86e1eff8 EC |
482 | tlb_n_used_entries_dec(env, mmu_idx); |
483 | } | |
68fea038 RH |
484 | } |
485 | } | |
486 | ||
3ab6e68c | 487 | static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx, |
732d5487 | 488 | vaddr page) |
3ab6e68c RH |
489 | { |
490 | tlb_flush_vtlb_page_mask_locked(env, mmu_idx, page, -1); | |
491 | } | |
492 | ||
732d5487 | 493 | static void tlb_flush_page_locked(CPUArchState *env, int midx, vaddr page) |
1308e026 | 494 | { |
732d5487 AJ |
495 | vaddr lp_addr = env_tlb(env)->d[midx].large_page_addr; |
496 | vaddr lp_mask = env_tlb(env)->d[midx].large_page_mask; | |
1308e026 RH |
497 | |
498 | /* Check if we need to flush due to large pages. */ | |
499 | if ((page & lp_mask) == lp_addr) { | |
732d5487 AJ |
500 | tlb_debug("forcing full flush midx %d (%" |
501 | VADDR_PRIx "/%" VADDR_PRIx ")\n", | |
1308e026 | 502 | midx, lp_addr, lp_mask); |
3c3959f2 | 503 | tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); |
1308e026 | 504 | } else { |
86e1eff8 EC |
505 | if (tlb_flush_entry_locked(tlb_entry(env, midx, page), page)) { |
506 | tlb_n_used_entries_dec(env, midx); | |
507 | } | |
1308e026 RH |
508 | tlb_flush_vtlb_page_locked(env, midx, page); |
509 | } | |
510 | } | |
511 | ||
7b7d00e0 RH |
512 | /** |
513 | * tlb_flush_page_by_mmuidx_async_0: | |
514 | * @cpu: cpu on which to flush | |
515 | * @addr: page of virtual address to flush | |
516 | * @idxmap: set of mmu_idx to flush | |
517 | * | |
518 | * Helper for tlb_flush_page_by_mmuidx and friends, flush one page | |
519 | * at @addr from the tlbs indicated by @idxmap from @cpu. | |
e7218445 | 520 | */ |
7b7d00e0 | 521 | static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu, |
732d5487 | 522 | vaddr addr, |
7b7d00e0 | 523 | uint16_t idxmap) |
d7a74a9d PM |
524 | { |
525 | CPUArchState *env = cpu->env_ptr; | |
e7218445 | 526 | int mmu_idx; |
d7a74a9d | 527 | |
f0aff0f1 | 528 | assert_cpu_is_self(cpu); |
d7a74a9d | 529 | |
732d5487 | 530 | tlb_debug("page addr: %" VADDR_PRIx " mmu_map:0x%x\n", addr, idxmap); |
d7a74a9d | 531 | |
a40ec84e | 532 | qemu_spin_lock(&env_tlb(env)->c.lock); |
0336cbf8 | 533 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
7b7d00e0 | 534 | if ((idxmap >> mmu_idx) & 1) { |
1308e026 | 535 | tlb_flush_page_locked(env, mmu_idx, addr); |
d7a74a9d PM |
536 | } |
537 | } | |
a40ec84e | 538 | qemu_spin_unlock(&env_tlb(env)->c.lock); |
d7a74a9d | 539 | |
1d41a79b RH |
540 | /* |
541 | * Discard jump cache entries for any tb which might potentially | |
542 | * overlap the flushed page, which includes the previous. | |
543 | */ | |
544 | tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE); | |
545 | tb_jmp_cache_clear_page(cpu, addr); | |
d7a74a9d PM |
546 | } |
547 | ||
7b7d00e0 RH |
548 | /** |
549 | * tlb_flush_page_by_mmuidx_async_1: | |
550 | * @cpu: cpu on which to flush | |
551 | * @data: encoded addr + idxmap | |
552 | * | |
553 | * Helper for tlb_flush_page_by_mmuidx and friends, called through | |
554 | * async_run_on_cpu. The idxmap parameter is encoded in the page | |
555 | * offset of the target_ptr field. This limits the set of mmu_idx | |
556 | * that can be passed via this method. | |
557 | */ | |
558 | static void tlb_flush_page_by_mmuidx_async_1(CPUState *cpu, | |
559 | run_on_cpu_data data) | |
560 | { | |
732d5487 AJ |
561 | vaddr addr_and_idxmap = data.target_ptr; |
562 | vaddr addr = addr_and_idxmap & TARGET_PAGE_MASK; | |
7b7d00e0 RH |
563 | uint16_t idxmap = addr_and_idxmap & ~TARGET_PAGE_MASK; |
564 | ||
565 | tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap); | |
566 | } | |
567 | ||
568 | typedef struct { | |
732d5487 | 569 | vaddr addr; |
7b7d00e0 RH |
570 | uint16_t idxmap; |
571 | } TLBFlushPageByMMUIdxData; | |
572 | ||
573 | /** | |
574 | * tlb_flush_page_by_mmuidx_async_2: | |
575 | * @cpu: cpu on which to flush | |
576 | * @data: allocated addr + idxmap | |
577 | * | |
578 | * Helper for tlb_flush_page_by_mmuidx and friends, called through | |
579 | * async_run_on_cpu. The addr+idxmap parameters are stored in a | |
580 | * TLBFlushPageByMMUIdxData structure that has been allocated | |
581 | * specifically for this helper. Free the structure when done. | |
582 | */ | |
583 | static void tlb_flush_page_by_mmuidx_async_2(CPUState *cpu, | |
584 | run_on_cpu_data data) | |
e7218445 | 585 | { |
7b7d00e0 RH |
586 | TLBFlushPageByMMUIdxData *d = data.host_ptr; |
587 | ||
588 | tlb_flush_page_by_mmuidx_async_0(cpu, d->addr, d->idxmap); | |
589 | g_free(d); | |
590 | } | |
e7218445 | 591 | |
732d5487 | 592 | void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, uint16_t idxmap) |
7b7d00e0 | 593 | { |
732d5487 | 594 | tlb_debug("addr: %" VADDR_PRIx " mmu_idx:%" PRIx16 "\n", addr, idxmap); |
e7218445 AB |
595 | |
596 | /* This should already be page aligned */ | |
7b7d00e0 | 597 | addr &= TARGET_PAGE_MASK; |
e7218445 | 598 | |
7b7d00e0 RH |
599 | if (qemu_cpu_is_self(cpu)) { |
600 | tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap); | |
601 | } else if (idxmap < TARGET_PAGE_SIZE) { | |
602 | /* | |
603 | * Most targets have only a few mmu_idx. In the case where | |
604 | * we can stuff idxmap into the low TARGET_PAGE_BITS, avoid | |
605 | * allocating memory for this operation. | |
606 | */ | |
607 | async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_1, | |
608 | RUN_ON_CPU_TARGET_PTR(addr | idxmap)); | |
e7218445 | 609 | } else { |
7b7d00e0 RH |
610 | TLBFlushPageByMMUIdxData *d = g_new(TLBFlushPageByMMUIdxData, 1); |
611 | ||
612 | /* Otherwise allocate a structure, freed by the worker. */ | |
613 | d->addr = addr; | |
614 | d->idxmap = idxmap; | |
615 | async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_2, | |
616 | RUN_ON_CPU_HOST_PTR(d)); | |
e7218445 AB |
617 | } |
618 | } | |
619 | ||
732d5487 | 620 | void tlb_flush_page(CPUState *cpu, vaddr addr) |
f8144c6c RH |
621 | { |
622 | tlb_flush_page_by_mmuidx(cpu, addr, ALL_MMUIDX_BITS); | |
623 | } | |
624 | ||
732d5487 | 625 | void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, vaddr addr, |
c3b9a07a | 626 | uint16_t idxmap) |
e3b9ca81 | 627 | { |
732d5487 | 628 | tlb_debug("addr: %" VADDR_PRIx " mmu_idx:%"PRIx16"\n", addr, idxmap); |
c3b9a07a AB |
629 | |
630 | /* This should already be page aligned */ | |
7b7d00e0 RH |
631 | addr &= TARGET_PAGE_MASK; |
632 | ||
633 | /* | |
634 | * Allocate memory to hold addr+idxmap only when needed. | |
635 | * See tlb_flush_page_by_mmuidx for details. | |
636 | */ | |
637 | if (idxmap < TARGET_PAGE_SIZE) { | |
638 | flush_all_helper(src_cpu, tlb_flush_page_by_mmuidx_async_1, | |
639 | RUN_ON_CPU_TARGET_PTR(addr | idxmap)); | |
640 | } else { | |
641 | CPUState *dst_cpu; | |
642 | ||
643 | /* Allocate a separate data block for each destination cpu. */ | |
644 | CPU_FOREACH(dst_cpu) { | |
645 | if (dst_cpu != src_cpu) { | |
646 | TLBFlushPageByMMUIdxData *d | |
647 | = g_new(TLBFlushPageByMMUIdxData, 1); | |
648 | ||
649 | d->addr = addr; | |
650 | d->idxmap = idxmap; | |
651 | async_run_on_cpu(dst_cpu, tlb_flush_page_by_mmuidx_async_2, | |
652 | RUN_ON_CPU_HOST_PTR(d)); | |
653 | } | |
654 | } | |
655 | } | |
c3b9a07a | 656 | |
7b7d00e0 | 657 | tlb_flush_page_by_mmuidx_async_0(src_cpu, addr, idxmap); |
c3b9a07a AB |
658 | } |
659 | ||
732d5487 | 660 | void tlb_flush_page_all_cpus(CPUState *src, vaddr addr) |
f8144c6c RH |
661 | { |
662 | tlb_flush_page_by_mmuidx_all_cpus(src, addr, ALL_MMUIDX_BITS); | |
663 | } | |
664 | ||
c3b9a07a | 665 | void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu, |
732d5487 | 666 | vaddr addr, |
1308e026 | 667 | uint16_t idxmap) |
c3b9a07a | 668 | { |
732d5487 | 669 | tlb_debug("addr: %" VADDR_PRIx " mmu_idx:%"PRIx16"\n", addr, idxmap); |
c3b9a07a AB |
670 | |
671 | /* This should already be page aligned */ | |
7b7d00e0 | 672 | addr &= TARGET_PAGE_MASK; |
c3b9a07a | 673 | |
7b7d00e0 RH |
674 | /* |
675 | * Allocate memory to hold addr+idxmap only when needed. | |
676 | * See tlb_flush_page_by_mmuidx for details. | |
677 | */ | |
678 | if (idxmap < TARGET_PAGE_SIZE) { | |
679 | flush_all_helper(src_cpu, tlb_flush_page_by_mmuidx_async_1, | |
680 | RUN_ON_CPU_TARGET_PTR(addr | idxmap)); | |
681 | async_safe_run_on_cpu(src_cpu, tlb_flush_page_by_mmuidx_async_1, | |
682 | RUN_ON_CPU_TARGET_PTR(addr | idxmap)); | |
683 | } else { | |
684 | CPUState *dst_cpu; | |
685 | TLBFlushPageByMMUIdxData *d; | |
686 | ||
687 | /* Allocate a separate data block for each destination cpu. */ | |
688 | CPU_FOREACH(dst_cpu) { | |
689 | if (dst_cpu != src_cpu) { | |
690 | d = g_new(TLBFlushPageByMMUIdxData, 1); | |
691 | d->addr = addr; | |
692 | d->idxmap = idxmap; | |
693 | async_run_on_cpu(dst_cpu, tlb_flush_page_by_mmuidx_async_2, | |
694 | RUN_ON_CPU_HOST_PTR(d)); | |
695 | } | |
696 | } | |
697 | ||
698 | d = g_new(TLBFlushPageByMMUIdxData, 1); | |
699 | d->addr = addr; | |
700 | d->idxmap = idxmap; | |
701 | async_safe_run_on_cpu(src_cpu, tlb_flush_page_by_mmuidx_async_2, | |
702 | RUN_ON_CPU_HOST_PTR(d)); | |
703 | } | |
c3b9a07a AB |
704 | } |
705 | ||
732d5487 | 706 | void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr) |
c3b9a07a | 707 | { |
f8144c6c | 708 | tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); |
e3b9ca81 FK |
709 | } |
710 | ||
3c4ddec1 | 711 | static void tlb_flush_range_locked(CPUArchState *env, int midx, |
732d5487 | 712 | vaddr addr, vaddr len, |
3c4ddec1 | 713 | unsigned bits) |
3ab6e68c RH |
714 | { |
715 | CPUTLBDesc *d = &env_tlb(env)->d[midx]; | |
716 | CPUTLBDescFast *f = &env_tlb(env)->f[midx]; | |
732d5487 | 717 | vaddr mask = MAKE_64BIT_MASK(0, bits); |
3ab6e68c RH |
718 | |
719 | /* | |
720 | * If @bits is smaller than the tlb size, there may be multiple entries | |
721 | * within the TLB; otherwise all addresses that match under @mask hit | |
722 | * the same TLB entry. | |
3ab6e68c RH |
723 | * TODO: Perhaps allow bits to be a few bits less than the size. |
724 | * For now, just flush the entire TLB. | |
3c4ddec1 RH |
725 | * |
726 | * If @len is larger than the tlb size, then it will take longer to | |
727 | * test all of the entries in the TLB than it will to flush it all. | |
3ab6e68c | 728 | */ |
3c4ddec1 | 729 | if (mask < f->mask || len > f->mask) { |
3ab6e68c | 730 | tlb_debug("forcing full flush midx %d (" |
732d5487 | 731 | "%" VADDR_PRIx "/%" VADDR_PRIx "+%" VADDR_PRIx ")\n", |
3c4ddec1 | 732 | midx, addr, mask, len); |
3ab6e68c RH |
733 | tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); |
734 | return; | |
735 | } | |
736 | ||
3c4ddec1 RH |
737 | /* |
738 | * Check if we need to flush due to large pages. | |
739 | * Because large_page_mask contains all 1's from the msb, | |
740 | * we only need to test the end of the range. | |
741 | */ | |
742 | if (((addr + len - 1) & d->large_page_mask) == d->large_page_addr) { | |
3ab6e68c | 743 | tlb_debug("forcing full flush midx %d (" |
732d5487 | 744 | "%" VADDR_PRIx "/%" VADDR_PRIx ")\n", |
3ab6e68c RH |
745 | midx, d->large_page_addr, d->large_page_mask); |
746 | tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); | |
747 | return; | |
748 | } | |
749 | ||
732d5487 AJ |
750 | for (vaddr i = 0; i < len; i += TARGET_PAGE_SIZE) { |
751 | vaddr page = addr + i; | |
3c4ddec1 RH |
752 | CPUTLBEntry *entry = tlb_entry(env, midx, page); |
753 | ||
754 | if (tlb_flush_entry_mask_locked(entry, page, mask)) { | |
755 | tlb_n_used_entries_dec(env, midx); | |
756 | } | |
757 | tlb_flush_vtlb_page_mask_locked(env, midx, page, mask); | |
3ab6e68c | 758 | } |
3ab6e68c RH |
759 | } |
760 | ||
761 | typedef struct { | |
732d5487 AJ |
762 | vaddr addr; |
763 | vaddr len; | |
3ab6e68c RH |
764 | uint16_t idxmap; |
765 | uint16_t bits; | |
3960a59f | 766 | } TLBFlushRangeData; |
3ab6e68c | 767 | |
6be48e45 RH |
768 | static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu, |
769 | TLBFlushRangeData d) | |
3ab6e68c RH |
770 | { |
771 | CPUArchState *env = cpu->env_ptr; | |
772 | int mmu_idx; | |
773 | ||
774 | assert_cpu_is_self(cpu); | |
775 | ||
732d5487 | 776 | tlb_debug("range: %" VADDR_PRIx "/%u+%" VADDR_PRIx " mmu_map:0x%x\n", |
3c4ddec1 | 777 | d.addr, d.bits, d.len, d.idxmap); |
3ab6e68c RH |
778 | |
779 | qemu_spin_lock(&env_tlb(env)->c.lock); | |
780 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
781 | if ((d.idxmap >> mmu_idx) & 1) { | |
3c4ddec1 | 782 | tlb_flush_range_locked(env, mmu_idx, d.addr, d.len, d.bits); |
3ab6e68c RH |
783 | } |
784 | } | |
785 | qemu_spin_unlock(&env_tlb(env)->c.lock); | |
786 | ||
cfc2a2d6 IH |
787 | /* |
788 | * If the length is larger than the jump cache size, then it will take | |
789 | * longer to clear each entry individually than it will to clear it all. | |
790 | */ | |
791 | if (d.len >= (TARGET_PAGE_SIZE * TB_JMP_CACHE_SIZE)) { | |
a976a99a | 792 | tcg_flush_jmp_cache(cpu); |
cfc2a2d6 IH |
793 | return; |
794 | } | |
795 | ||
1d41a79b RH |
796 | /* |
797 | * Discard jump cache entries for any tb which might potentially | |
798 | * overlap the flushed pages, which includes the previous. | |
799 | */ | |
800 | d.addr -= TARGET_PAGE_SIZE; | |
732d5487 | 801 | for (vaddr i = 0, n = d.len / TARGET_PAGE_SIZE + 1; i < n; i++) { |
1d41a79b RH |
802 | tb_jmp_cache_clear_page(cpu, d.addr); |
803 | d.addr += TARGET_PAGE_SIZE; | |
3c4ddec1 | 804 | } |
3ab6e68c RH |
805 | } |
806 | ||
206a583d RH |
807 | static void tlb_flush_range_by_mmuidx_async_1(CPUState *cpu, |
808 | run_on_cpu_data data) | |
3ab6e68c | 809 | { |
3960a59f | 810 | TLBFlushRangeData *d = data.host_ptr; |
6be48e45 | 811 | tlb_flush_range_by_mmuidx_async_0(cpu, *d); |
3ab6e68c RH |
812 | g_free(d); |
813 | } | |
814 | ||
732d5487 AJ |
815 | void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, |
816 | vaddr len, uint16_t idxmap, | |
e5b1921b | 817 | unsigned bits) |
3ab6e68c | 818 | { |
3960a59f | 819 | TLBFlushRangeData d; |
3ab6e68c | 820 | |
e5b1921b RH |
821 | /* |
822 | * If all bits are significant, and len is small, | |
823 | * this devolves to tlb_flush_page. | |
824 | */ | |
825 | if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { | |
3ab6e68c RH |
826 | tlb_flush_page_by_mmuidx(cpu, addr, idxmap); |
827 | return; | |
828 | } | |
829 | /* If no page bits are significant, this devolves to tlb_flush. */ | |
830 | if (bits < TARGET_PAGE_BITS) { | |
831 | tlb_flush_by_mmuidx(cpu, idxmap); | |
832 | return; | |
833 | } | |
834 | ||
835 | /* This should already be page aligned */ | |
836 | d.addr = addr & TARGET_PAGE_MASK; | |
e5b1921b | 837 | d.len = len; |
3ab6e68c RH |
838 | d.idxmap = idxmap; |
839 | d.bits = bits; | |
840 | ||
841 | if (qemu_cpu_is_self(cpu)) { | |
6be48e45 | 842 | tlb_flush_range_by_mmuidx_async_0(cpu, d); |
3ab6e68c | 843 | } else { |
3ab6e68c | 844 | /* Otherwise allocate a structure, freed by the worker. */ |
3960a59f | 845 | TLBFlushRangeData *p = g_memdup(&d, sizeof(d)); |
206a583d | 846 | async_run_on_cpu(cpu, tlb_flush_range_by_mmuidx_async_1, |
3ab6e68c RH |
847 | RUN_ON_CPU_HOST_PTR(p)); |
848 | } | |
849 | } | |
850 | ||
732d5487 | 851 | void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, |
e5b1921b RH |
852 | uint16_t idxmap, unsigned bits) |
853 | { | |
854 | tlb_flush_range_by_mmuidx(cpu, addr, TARGET_PAGE_SIZE, idxmap, bits); | |
855 | } | |
856 | ||
600b819f | 857 | void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu, |
732d5487 | 858 | vaddr addr, vaddr len, |
600b819f | 859 | uint16_t idxmap, unsigned bits) |
3ab6e68c | 860 | { |
3960a59f | 861 | TLBFlushRangeData d; |
d34e4d1a | 862 | CPUState *dst_cpu; |
3ab6e68c | 863 | |
600b819f RH |
864 | /* |
865 | * If all bits are significant, and len is small, | |
866 | * this devolves to tlb_flush_page. | |
867 | */ | |
868 | if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { | |
3ab6e68c RH |
869 | tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap); |
870 | return; | |
871 | } | |
872 | /* If no page bits are significant, this devolves to tlb_flush. */ | |
873 | if (bits < TARGET_PAGE_BITS) { | |
874 | tlb_flush_by_mmuidx_all_cpus(src_cpu, idxmap); | |
875 | return; | |
876 | } | |
877 | ||
878 | /* This should already be page aligned */ | |
879 | d.addr = addr & TARGET_PAGE_MASK; | |
600b819f | 880 | d.len = len; |
3ab6e68c RH |
881 | d.idxmap = idxmap; |
882 | d.bits = bits; | |
883 | ||
d34e4d1a RH |
884 | /* Allocate a separate data block for each destination cpu. */ |
885 | CPU_FOREACH(dst_cpu) { | |
886 | if (dst_cpu != src_cpu) { | |
887 | TLBFlushRangeData *p = g_memdup(&d, sizeof(d)); | |
888 | async_run_on_cpu(dst_cpu, | |
206a583d | 889 | tlb_flush_range_by_mmuidx_async_1, |
d34e4d1a | 890 | RUN_ON_CPU_HOST_PTR(p)); |
3ab6e68c RH |
891 | } |
892 | } | |
893 | ||
6be48e45 | 894 | tlb_flush_range_by_mmuidx_async_0(src_cpu, d); |
3ab6e68c RH |
895 | } |
896 | ||
600b819f | 897 | void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, |
732d5487 AJ |
898 | vaddr addr, uint16_t idxmap, |
899 | unsigned bits) | |
600b819f RH |
900 | { |
901 | tlb_flush_range_by_mmuidx_all_cpus(src_cpu, addr, TARGET_PAGE_SIZE, | |
902 | idxmap, bits); | |
903 | } | |
904 | ||
c13b27d8 | 905 | void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, |
732d5487 AJ |
906 | vaddr addr, |
907 | vaddr len, | |
c13b27d8 RH |
908 | uint16_t idxmap, |
909 | unsigned bits) | |
3ab6e68c | 910 | { |
d34e4d1a RH |
911 | TLBFlushRangeData d, *p; |
912 | CPUState *dst_cpu; | |
3ab6e68c | 913 | |
c13b27d8 RH |
914 | /* |
915 | * If all bits are significant, and len is small, | |
916 | * this devolves to tlb_flush_page. | |
917 | */ | |
918 | if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { | |
3ab6e68c RH |
919 | tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); |
920 | return; | |
921 | } | |
922 | /* If no page bits are significant, this devolves to tlb_flush. */ | |
923 | if (bits < TARGET_PAGE_BITS) { | |
924 | tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, idxmap); | |
925 | return; | |
926 | } | |
927 | ||
928 | /* This should already be page aligned */ | |
929 | d.addr = addr & TARGET_PAGE_MASK; | |
c13b27d8 | 930 | d.len = len; |
3ab6e68c RH |
931 | d.idxmap = idxmap; |
932 | d.bits = bits; | |
933 | ||
d34e4d1a RH |
934 | /* Allocate a separate data block for each destination cpu. */ |
935 | CPU_FOREACH(dst_cpu) { | |
936 | if (dst_cpu != src_cpu) { | |
937 | p = g_memdup(&d, sizeof(d)); | |
206a583d | 938 | async_run_on_cpu(dst_cpu, tlb_flush_range_by_mmuidx_async_1, |
d34e4d1a | 939 | RUN_ON_CPU_HOST_PTR(p)); |
3ab6e68c | 940 | } |
3ab6e68c | 941 | } |
d34e4d1a RH |
942 | |
943 | p = g_memdup(&d, sizeof(d)); | |
206a583d | 944 | async_safe_run_on_cpu(src_cpu, tlb_flush_range_by_mmuidx_async_1, |
d34e4d1a | 945 | RUN_ON_CPU_HOST_PTR(p)); |
3ab6e68c RH |
946 | } |
947 | ||
c13b27d8 | 948 | void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, |
732d5487 | 949 | vaddr addr, |
c13b27d8 RH |
950 | uint16_t idxmap, |
951 | unsigned bits) | |
952 | { | |
953 | tlb_flush_range_by_mmuidx_all_cpus_synced(src_cpu, addr, TARGET_PAGE_SIZE, | |
954 | idxmap, bits); | |
955 | } | |
956 | ||
0cac1b66 BS |
957 | /* update the TLBs so that writes to code in the virtual page 'addr' |
958 | can be detected */ | |
959 | void tlb_protect_code(ram_addr_t ram_addr) | |
960 | { | |
93b99616 RH |
961 | cpu_physical_memory_test_and_clear_dirty(ram_addr & TARGET_PAGE_MASK, |
962 | TARGET_PAGE_SIZE, | |
03eebc9e | 963 | DIRTY_MEMORY_CODE); |
0cac1b66 BS |
964 | } |
965 | ||
966 | /* update the TLB so that writes in physical page 'phys_addr' are no longer | |
967 | tested for self modifying code */ | |
9564f52d | 968 | void tlb_unprotect_code(ram_addr_t ram_addr) |
0cac1b66 | 969 | { |
52159192 | 970 | cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE); |
0cac1b66 BS |
971 | } |
972 | ||
0cac1b66 | 973 | |
b0706b71 AB |
974 | /* |
975 | * Dirty write flag handling | |
976 | * | |
977 | * When the TCG code writes to a location it looks up the address in | |
978 | * the TLB and uses that data to compute the final address. If any of | |
979 | * the lower bits of the address are set then the slow path is forced. | |
980 | * There are a number of reasons to do this but for normal RAM the | |
981 | * most usual is detecting writes to code regions which may invalidate | |
982 | * generated code. | |
983 | * | |
71aec354 | 984 | * Other vCPUs might be reading their TLBs during guest execution, so we update |
d73415a3 | 985 | * te->addr_write with qatomic_set. We don't need to worry about this for |
71aec354 | 986 | * oversized guests as MTTCG is disabled for them. |
b0706b71 | 987 | * |
53d28455 | 988 | * Called with tlb_c.lock held. |
b0706b71 | 989 | */ |
71aec354 EC |
990 | static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, |
991 | uintptr_t start, uintptr_t length) | |
0cac1b66 | 992 | { |
b0706b71 | 993 | uintptr_t addr = tlb_entry->addr_write; |
0cac1b66 | 994 | |
7b0d792c RH |
995 | if ((addr & (TLB_INVALID_MASK | TLB_MMIO | |
996 | TLB_DISCARD_WRITE | TLB_NOTDIRTY)) == 0) { | |
b0706b71 AB |
997 | addr &= TARGET_PAGE_MASK; |
998 | addr += tlb_entry->addend; | |
0cac1b66 | 999 | if ((addr - start) < length) { |
238f4380 RH |
1000 | #if TARGET_LONG_BITS == 32 |
1001 | uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write; | |
1002 | ptr_write += HOST_BIG_ENDIAN; | |
1003 | qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY); | |
1004 | #elif TCG_OVERSIZED_GUEST | |
0cac1b66 | 1005 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
b0706b71 | 1006 | #else |
d73415a3 | 1007 | qatomic_set(&tlb_entry->addr_write, |
238f4380 | 1008 | tlb_entry->addr_write | TLB_NOTDIRTY); |
71aec354 | 1009 | #endif |
b0706b71 AB |
1010 | } |
1011 | } | |
b0706b71 AB |
1012 | } |
1013 | ||
71aec354 | 1014 | /* |
53d28455 | 1015 | * Called with tlb_c.lock held. |
71aec354 EC |
1016 | * Called only from the vCPU context, i.e. the TLB's owner thread. |
1017 | */ | |
1018 | static inline void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntry *s) | |
b0706b71 | 1019 | { |
b0706b71 | 1020 | *d = *s; |
0cac1b66 BS |
1021 | } |
1022 | ||
b0706b71 | 1023 | /* This is a cross vCPU call (i.e. another vCPU resetting the flags of |
71aec354 | 1024 | * the target vCPU). |
53d28455 | 1025 | * We must take tlb_c.lock to avoid racing with another vCPU update. The only |
71aec354 | 1026 | * thing actually updated is the target TLB entry ->addr_write flags. |
b0706b71 | 1027 | */ |
9a13565d | 1028 | void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) |
0cac1b66 BS |
1029 | { |
1030 | CPUArchState *env; | |
1031 | ||
9a13565d | 1032 | int mmu_idx; |
0cac1b66 | 1033 | |
9a13565d | 1034 | env = cpu->env_ptr; |
a40ec84e | 1035 | qemu_spin_lock(&env_tlb(env)->c.lock); |
9a13565d PC |
1036 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
1037 | unsigned int i; | |
722a1c1e | 1038 | unsigned int n = tlb_n_entries(&env_tlb(env)->f[mmu_idx]); |
0cac1b66 | 1039 | |
86e1eff8 | 1040 | for (i = 0; i < n; i++) { |
a40ec84e RH |
1041 | tlb_reset_dirty_range_locked(&env_tlb(env)->f[mmu_idx].table[i], |
1042 | start1, length); | |
9a13565d | 1043 | } |
88e89a57 | 1044 | |
9a13565d | 1045 | for (i = 0; i < CPU_VTLB_SIZE; i++) { |
a40ec84e RH |
1046 | tlb_reset_dirty_range_locked(&env_tlb(env)->d[mmu_idx].vtable[i], |
1047 | start1, length); | |
0cac1b66 BS |
1048 | } |
1049 | } | |
a40ec84e | 1050 | qemu_spin_unlock(&env_tlb(env)->c.lock); |
0cac1b66 BS |
1051 | } |
1052 | ||
53d28455 | 1053 | /* Called with tlb_c.lock held */ |
71aec354 | 1054 | static inline void tlb_set_dirty1_locked(CPUTLBEntry *tlb_entry, |
732d5487 | 1055 | vaddr addr) |
0cac1b66 | 1056 | { |
732d5487 AJ |
1057 | if (tlb_entry->addr_write == (addr | TLB_NOTDIRTY)) { |
1058 | tlb_entry->addr_write = addr; | |
0cac1b66 BS |
1059 | } |
1060 | } | |
1061 | ||
1062 | /* update the TLB corresponding to virtual page vaddr | |
1063 | so that it is no longer dirty */ | |
732d5487 | 1064 | void tlb_set_dirty(CPUState *cpu, vaddr addr) |
0cac1b66 | 1065 | { |
bcae01e4 | 1066 | CPUArchState *env = cpu->env_ptr; |
0cac1b66 BS |
1067 | int mmu_idx; |
1068 | ||
f0aff0f1 AB |
1069 | assert_cpu_is_self(cpu); |
1070 | ||
732d5487 | 1071 | addr &= TARGET_PAGE_MASK; |
a40ec84e | 1072 | qemu_spin_lock(&env_tlb(env)->c.lock); |
0cac1b66 | 1073 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
732d5487 | 1074 | tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, addr), addr); |
0cac1b66 | 1075 | } |
88e89a57 XT |
1076 | |
1077 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
1078 | int k; | |
1079 | for (k = 0; k < CPU_VTLB_SIZE; k++) { | |
732d5487 | 1080 | tlb_set_dirty1_locked(&env_tlb(env)->d[mmu_idx].vtable[k], addr); |
88e89a57 XT |
1081 | } |
1082 | } | |
a40ec84e | 1083 | qemu_spin_unlock(&env_tlb(env)->c.lock); |
0cac1b66 BS |
1084 | } |
1085 | ||
1086 | /* Our TLB does not support large pages, so remember the area covered by | |
1087 | large pages and trigger a full TLB flush if these are invalidated. */ | |
1308e026 | 1088 | static void tlb_add_large_page(CPUArchState *env, int mmu_idx, |
732d5487 | 1089 | vaddr addr, uint64_t size) |
0cac1b66 | 1090 | { |
732d5487 AJ |
1091 | vaddr lp_addr = env_tlb(env)->d[mmu_idx].large_page_addr; |
1092 | vaddr lp_mask = ~(size - 1); | |
0cac1b66 | 1093 | |
732d5487 | 1094 | if (lp_addr == (vaddr)-1) { |
1308e026 | 1095 | /* No previous large page. */ |
732d5487 | 1096 | lp_addr = addr; |
1308e026 RH |
1097 | } else { |
1098 | /* Extend the existing region to include the new page. | |
1099 | This is a compromise between unnecessary flushes and | |
1100 | the cost of maintaining a full variable size TLB. */ | |
a40ec84e | 1101 | lp_mask &= env_tlb(env)->d[mmu_idx].large_page_mask; |
732d5487 | 1102 | while (((lp_addr ^ addr) & lp_mask) != 0) { |
1308e026 RH |
1103 | lp_mask <<= 1; |
1104 | } | |
0cac1b66 | 1105 | } |
a40ec84e RH |
1106 | env_tlb(env)->d[mmu_idx].large_page_addr = lp_addr & lp_mask; |
1107 | env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask; | |
0cac1b66 BS |
1108 | } |
1109 | ||
58e8f1f6 RH |
1110 | static inline void tlb_set_compare(CPUTLBEntryFull *full, CPUTLBEntry *ent, |
1111 | target_ulong address, int flags, | |
1112 | MMUAccessType access_type, bool enable) | |
1113 | { | |
1114 | if (enable) { | |
1115 | address |= flags & TLB_FLAGS_MASK; | |
1116 | flags &= TLB_SLOW_FLAGS_MASK; | |
1117 | if (flags) { | |
1118 | address |= TLB_FORCE_SLOW; | |
1119 | } | |
1120 | } else { | |
1121 | address = -1; | |
1122 | flags = 0; | |
1123 | } | |
1124 | ent->addr_idx[access_type] = address; | |
1125 | full->slow_flags[access_type] = flags; | |
1126 | } | |
1127 | ||
40473689 RH |
1128 | /* |
1129 | * Add a new TLB entry. At most one entry for a given virtual address | |
79e2b9ae PB |
1130 | * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the |
1131 | * supplied size is only used by tlb_flush_page. | |
1132 | * | |
1133 | * Called from TCG-generated code, which is under an RCU read-side | |
1134 | * critical section. | |
1135 | */ | |
40473689 | 1136 | void tlb_set_page_full(CPUState *cpu, int mmu_idx, |
732d5487 | 1137 | vaddr addr, CPUTLBEntryFull *full) |
0cac1b66 | 1138 | { |
0c591eb0 | 1139 | CPUArchState *env = cpu->env_ptr; |
a40ec84e RH |
1140 | CPUTLB *tlb = env_tlb(env); |
1141 | CPUTLBDesc *desc = &tlb->d[mmu_idx]; | |
0cac1b66 | 1142 | MemoryRegionSection *section; |
58e8f1f6 | 1143 | unsigned int index, read_flags, write_flags; |
0cac1b66 | 1144 | uintptr_t addend; |
68fea038 | 1145 | CPUTLBEntry *te, tn; |
55df6fcf | 1146 | hwaddr iotlb, xlat, sz, paddr_page; |
732d5487 | 1147 | vaddr addr_page; |
40473689 | 1148 | int asidx, wp_flags, prot; |
8f5db641 | 1149 | bool is_ram, is_romd; |
0cac1b66 | 1150 | |
f0aff0f1 | 1151 | assert_cpu_is_self(cpu); |
55df6fcf | 1152 | |
40473689 | 1153 | if (full->lg_page_size <= TARGET_PAGE_BITS) { |
55df6fcf PM |
1154 | sz = TARGET_PAGE_SIZE; |
1155 | } else { | |
40473689 | 1156 | sz = (hwaddr)1 << full->lg_page_size; |
732d5487 | 1157 | tlb_add_large_page(env, mmu_idx, addr, sz); |
0cac1b66 | 1158 | } |
732d5487 | 1159 | addr_page = addr & TARGET_PAGE_MASK; |
40473689 | 1160 | paddr_page = full->phys_addr & TARGET_PAGE_MASK; |
149f54b5 | 1161 | |
40473689 RH |
1162 | prot = full->prot; |
1163 | asidx = cpu_asidx_from_attrs(cpu, full->attrs); | |
55df6fcf | 1164 | section = address_space_translate_for_iotlb(cpu, asidx, paddr_page, |
40473689 | 1165 | &xlat, &sz, full->attrs, &prot); |
149f54b5 PB |
1166 | assert(sz >= TARGET_PAGE_SIZE); |
1167 | ||
732d5487 | 1168 | tlb_debug("vaddr=%" VADDR_PRIx " paddr=0x" HWADDR_FMT_plx |
8526e1f4 | 1169 | " prot=%x idx=%d\n", |
732d5487 | 1170 | addr, full->phys_addr, prot, mmu_idx); |
0cac1b66 | 1171 | |
58e8f1f6 | 1172 | read_flags = 0; |
40473689 | 1173 | if (full->lg_page_size < TARGET_PAGE_BITS) { |
30d7e098 | 1174 | /* Repeat the MMU check and TLB fill on every access. */ |
58e8f1f6 | 1175 | read_flags |= TLB_INVALID_MASK; |
55df6fcf | 1176 | } |
40473689 | 1177 | if (full->attrs.byte_swap) { |
58e8f1f6 | 1178 | read_flags |= TLB_BSWAP; |
a26fc6f5 | 1179 | } |
8f5db641 RH |
1180 | |
1181 | is_ram = memory_region_is_ram(section->mr); | |
1182 | is_romd = memory_region_is_romd(section->mr); | |
1183 | ||
1184 | if (is_ram || is_romd) { | |
1185 | /* RAM and ROMD both have associated host memory. */ | |
1186 | addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat; | |
1187 | } else { | |
1188 | /* I/O does not; force the host address to NULL. */ | |
8f3e03cb | 1189 | addend = 0; |
8f5db641 RH |
1190 | } |
1191 | ||
58e8f1f6 | 1192 | write_flags = read_flags; |
8f5db641 RH |
1193 | if (is_ram) { |
1194 | iotlb = memory_region_get_ram_addr(section->mr) + xlat; | |
1195 | /* | |
1196 | * Computing is_clean is expensive; avoid all that unless | |
1197 | * the page is actually writable. | |
1198 | */ | |
1199 | if (prot & PAGE_WRITE) { | |
1200 | if (section->readonly) { | |
58e8f1f6 | 1201 | write_flags |= TLB_DISCARD_WRITE; |
8f5db641 | 1202 | } else if (cpu_physical_memory_is_clean(iotlb)) { |
58e8f1f6 | 1203 | write_flags |= TLB_NOTDIRTY; |
8f5db641 RH |
1204 | } |
1205 | } | |
8f3e03cb | 1206 | } else { |
8f5db641 RH |
1207 | /* I/O or ROMD */ |
1208 | iotlb = memory_region_section_get_iotlb(cpu, section) + xlat; | |
1209 | /* | |
1210 | * Writes to romd devices must go through MMIO to enable write. | |
1211 | * Reads to romd devices go through the ram_ptr found above, | |
1212 | * but of course reads to I/O must go through MMIO. | |
1213 | */ | |
58e8f1f6 | 1214 | write_flags |= TLB_MMIO; |
8f5db641 | 1215 | if (!is_romd) { |
58e8f1f6 | 1216 | read_flags = write_flags; |
8f5db641 | 1217 | } |
0cac1b66 | 1218 | } |
0cac1b66 | 1219 | |
732d5487 | 1220 | wp_flags = cpu_watchpoint_address_matches(cpu, addr_page, |
50b107c5 | 1221 | TARGET_PAGE_SIZE); |
0cac1b66 | 1222 | |
732d5487 AJ |
1223 | index = tlb_index(env, mmu_idx, addr_page); |
1224 | te = tlb_entry(env, mmu_idx, addr_page); | |
b0706b71 | 1225 | |
71aec354 EC |
1226 | /* |
1227 | * Hold the TLB lock for the rest of the function. We could acquire/release | |
1228 | * the lock several times in the function, but it is faster to amortize the | |
1229 | * acquisition cost by acquiring it just once. Note that this leads to | |
1230 | * a longer critical section, but this is not a concern since the TLB lock | |
1231 | * is unlikely to be contended. | |
1232 | */ | |
a40ec84e | 1233 | qemu_spin_lock(&tlb->c.lock); |
71aec354 | 1234 | |
3d1523ce | 1235 | /* Note that the tlb is no longer clean. */ |
a40ec84e | 1236 | tlb->c.dirty |= 1 << mmu_idx; |
3d1523ce | 1237 | |
71aec354 | 1238 | /* Make sure there's no cached translation for the new page. */ |
732d5487 | 1239 | tlb_flush_vtlb_page_locked(env, mmu_idx, addr_page); |
71aec354 | 1240 | |
68fea038 RH |
1241 | /* |
1242 | * Only evict the old entry to the victim tlb if it's for a | |
1243 | * different page; otherwise just overwrite the stale data. | |
1244 | */ | |
732d5487 | 1245 | if (!tlb_hit_page_anyprot(te, addr_page) && !tlb_entry_is_empty(te)) { |
a40ec84e RH |
1246 | unsigned vidx = desc->vindex++ % CPU_VTLB_SIZE; |
1247 | CPUTLBEntry *tv = &desc->vtable[vidx]; | |
b0706b71 | 1248 | |
68fea038 | 1249 | /* Evict the old entry into the victim tlb. */ |
71aec354 | 1250 | copy_tlb_helper_locked(tv, te); |
25d3ec58 | 1251 | desc->vfulltlb[vidx] = desc->fulltlb[index]; |
86e1eff8 | 1252 | tlb_n_used_entries_dec(env, mmu_idx); |
68fea038 | 1253 | } |
88e89a57 XT |
1254 | |
1255 | /* refill the tlb */ | |
ace41090 PM |
1256 | /* |
1257 | * At this point iotlb contains a physical section number in the lower | |
1258 | * TARGET_PAGE_BITS, and either | |
8f5db641 RH |
1259 | * + the ram_addr_t of the page base of the target RAM (RAM) |
1260 | * + the offset within section->mr of the page base (I/O, ROMD) | |
58e8f1f6 | 1261 | * We subtract addr_page (which is page aligned and thus won't |
ace41090 PM |
1262 | * disturb the low bits) to give an offset which can be added to the |
1263 | * (non-page-aligned) vaddr of the eventual memory access to get | |
1264 | * the MemoryRegion offset for the access. Note that the vaddr we | |
1265 | * subtract here is that of the page base, and not the same as the | |
1266 | * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). | |
1267 | */ | |
40473689 | 1268 | desc->fulltlb[index] = *full; |
58e8f1f6 RH |
1269 | full = &desc->fulltlb[index]; |
1270 | full->xlat_section = iotlb - addr_page; | |
1271 | full->phys_addr = paddr_page; | |
b0706b71 AB |
1272 | |
1273 | /* Now calculate the new entry */ | |
732d5487 | 1274 | tn.addend = addend - addr_page; |
0cac1b66 | 1275 | |
58e8f1f6 RH |
1276 | tlb_set_compare(full, &tn, addr_page, read_flags, |
1277 | MMU_INST_FETCH, prot & PAGE_EXEC); | |
1278 | ||
1279 | if (wp_flags & BP_MEM_READ) { | |
1280 | read_flags |= TLB_WATCHPOINT; | |
0cac1b66 | 1281 | } |
58e8f1f6 RH |
1282 | tlb_set_compare(full, &tn, addr_page, read_flags, |
1283 | MMU_DATA_LOAD, prot & PAGE_READ); | |
b0706b71 | 1284 | |
58e8f1f6 RH |
1285 | if (prot & PAGE_WRITE_INV) { |
1286 | write_flags |= TLB_INVALID_MASK; | |
1287 | } | |
1288 | if (wp_flags & BP_MEM_WRITE) { | |
1289 | write_flags |= TLB_WATCHPOINT; | |
0cac1b66 | 1290 | } |
58e8f1f6 RH |
1291 | tlb_set_compare(full, &tn, addr_page, write_flags, |
1292 | MMU_DATA_STORE, prot & PAGE_WRITE); | |
b0706b71 | 1293 | |
71aec354 | 1294 | copy_tlb_helper_locked(te, &tn); |
86e1eff8 | 1295 | tlb_n_used_entries_inc(env, mmu_idx); |
a40ec84e | 1296 | qemu_spin_unlock(&tlb->c.lock); |
0cac1b66 BS |
1297 | } |
1298 | ||
732d5487 | 1299 | void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, |
40473689 | 1300 | hwaddr paddr, MemTxAttrs attrs, int prot, |
732d5487 | 1301 | int mmu_idx, uint64_t size) |
40473689 RH |
1302 | { |
1303 | CPUTLBEntryFull full = { | |
1304 | .phys_addr = paddr, | |
1305 | .attrs = attrs, | |
1306 | .prot = prot, | |
1307 | .lg_page_size = ctz64(size) | |
1308 | }; | |
1309 | ||
1310 | assert(is_power_of_2(size)); | |
732d5487 | 1311 | tlb_set_page_full(cpu, mmu_idx, addr, &full); |
40473689 RH |
1312 | } |
1313 | ||
732d5487 | 1314 | void tlb_set_page(CPUState *cpu, vaddr addr, |
fadc1cbe | 1315 | hwaddr paddr, int prot, |
732d5487 | 1316 | int mmu_idx, uint64_t size) |
fadc1cbe | 1317 | { |
732d5487 | 1318 | tlb_set_page_with_attrs(cpu, addr, paddr, MEMTXATTRS_UNSPECIFIED, |
fadc1cbe PM |
1319 | prot, mmu_idx, size); |
1320 | } | |
1321 | ||
c319dc13 RH |
1322 | /* |
1323 | * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the | |
1324 | * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must | |
1325 | * be discarded and looked up again (e.g. via tlb_entry()). | |
1326 | */ | |
732d5487 | 1327 | static void tlb_fill(CPUState *cpu, vaddr addr, int size, |
c319dc13 RH |
1328 | MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) |
1329 | { | |
c319dc13 RH |
1330 | bool ok; |
1331 | ||
1332 | /* | |
1333 | * This is not a probe, so only valid return is success; failure | |
1334 | * should result in exception + longjmp to the cpu loop. | |
1335 | */ | |
8810ee2a AB |
1336 | ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, |
1337 | access_type, mmu_idx, false, retaddr); | |
c319dc13 RH |
1338 | assert(ok); |
1339 | } | |
1340 | ||
78271684 CF |
1341 | static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, |
1342 | MMUAccessType access_type, | |
1343 | int mmu_idx, uintptr_t retaddr) | |
1344 | { | |
8810ee2a AB |
1345 | cpu->cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, |
1346 | mmu_idx, retaddr); | |
78271684 CF |
1347 | } |
1348 | ||
1349 | static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, | |
1350 | vaddr addr, unsigned size, | |
1351 | MMUAccessType access_type, | |
1352 | int mmu_idx, MemTxAttrs attrs, | |
1353 | MemTxResult response, | |
1354 | uintptr_t retaddr) | |
1355 | { | |
1356 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
1357 | ||
1358 | if (!cpu->ignore_memory_transaction_failures && | |
1359 | cc->tcg_ops->do_transaction_failed) { | |
1360 | cc->tcg_ops->do_transaction_failed(cpu, physaddr, addr, size, | |
1361 | access_type, mmu_idx, attrs, | |
1362 | response, retaddr); | |
1363 | } | |
1364 | } | |
1365 | ||
25d3ec58 | 1366 | static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, |
732d5487 | 1367 | int mmu_idx, vaddr addr, uintptr_t retaddr, |
be5c4787 | 1368 | MMUAccessType access_type, MemOp op) |
82a45b96 | 1369 | { |
29a0af61 | 1370 | CPUState *cpu = env_cpu(env); |
2d54f194 PM |
1371 | hwaddr mr_offset; |
1372 | MemoryRegionSection *section; | |
1373 | MemoryRegion *mr; | |
82a45b96 | 1374 | uint64_t val; |
04e3aabd | 1375 | MemTxResult r; |
82a45b96 | 1376 | |
25d3ec58 | 1377 | section = iotlb_to_section(cpu, full->xlat_section, full->attrs); |
2d54f194 | 1378 | mr = section->mr; |
25d3ec58 | 1379 | mr_offset = (full->xlat_section & TARGET_PAGE_MASK) + addr; |
82a45b96 | 1380 | cpu->mem_io_pc = retaddr; |
08565552 | 1381 | if (!cpu->can_do_io) { |
82a45b96 RH |
1382 | cpu_io_recompile(cpu, retaddr); |
1383 | } | |
1384 | ||
61b59fb2 RH |
1385 | { |
1386 | QEMU_IOTHREAD_LOCK_GUARD(); | |
1387 | r = memory_region_dispatch_read(mr, mr_offset, &val, op, full->attrs); | |
8d04fb55 | 1388 | } |
61b59fb2 | 1389 | |
04e3aabd | 1390 | if (r != MEMTX_OK) { |
2d54f194 PM |
1391 | hwaddr physaddr = mr_offset + |
1392 | section->offset_within_address_space - | |
1393 | section->offset_within_region; | |
1394 | ||
be5c4787 | 1395 | cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access_type, |
25d3ec58 | 1396 | mmu_idx, full->attrs, r, retaddr); |
04e3aabd | 1397 | } |
82a45b96 RH |
1398 | return val; |
1399 | } | |
1400 | ||
2f3a57ee | 1401 | /* |
25d3ec58 RH |
1402 | * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin. |
1403 | * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match | |
570ef309 | 1404 | * because of the side effect of io_writex changing memory layout. |
2f3a57ee | 1405 | */ |
37523ff7 RH |
1406 | static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section, |
1407 | hwaddr mr_offset) | |
2f3a57ee AB |
1408 | { |
1409 | #ifdef CONFIG_PLUGIN | |
1410 | SavedIOTLB *saved = &cs->saved_iotlb; | |
2f3a57ee AB |
1411 | saved->section = section; |
1412 | saved->mr_offset = mr_offset; | |
1413 | #endif | |
1414 | } | |
1415 | ||
25d3ec58 | 1416 | static void io_writex(CPUArchState *env, CPUTLBEntryFull *full, |
732d5487 | 1417 | int mmu_idx, uint64_t val, vaddr addr, |
be5c4787 | 1418 | uintptr_t retaddr, MemOp op) |
82a45b96 | 1419 | { |
29a0af61 | 1420 | CPUState *cpu = env_cpu(env); |
2d54f194 PM |
1421 | hwaddr mr_offset; |
1422 | MemoryRegionSection *section; | |
1423 | MemoryRegion *mr; | |
04e3aabd | 1424 | MemTxResult r; |
82a45b96 | 1425 | |
25d3ec58 | 1426 | section = iotlb_to_section(cpu, full->xlat_section, full->attrs); |
2d54f194 | 1427 | mr = section->mr; |
25d3ec58 | 1428 | mr_offset = (full->xlat_section & TARGET_PAGE_MASK) + addr; |
08565552 | 1429 | if (!cpu->can_do_io) { |
82a45b96 RH |
1430 | cpu_io_recompile(cpu, retaddr); |
1431 | } | |
82a45b96 | 1432 | cpu->mem_io_pc = retaddr; |
8d04fb55 | 1433 | |
2f3a57ee AB |
1434 | /* |
1435 | * The memory_region_dispatch may trigger a flush/resize | |
1436 | * so for plugins we save the iotlb_data just in case. | |
1437 | */ | |
37523ff7 | 1438 | save_iotlb_data(cpu, section, mr_offset); |
2f3a57ee | 1439 | |
61b59fb2 RH |
1440 | { |
1441 | QEMU_IOTHREAD_LOCK_GUARD(); | |
1442 | r = memory_region_dispatch_write(mr, mr_offset, val, op, full->attrs); | |
8d04fb55 | 1443 | } |
61b59fb2 | 1444 | |
04e3aabd | 1445 | if (r != MEMTX_OK) { |
2d54f194 PM |
1446 | hwaddr physaddr = mr_offset + |
1447 | section->offset_within_address_space - | |
1448 | section->offset_within_region; | |
1449 | ||
be5c4787 | 1450 | cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), |
25d3ec58 | 1451 | MMU_DATA_STORE, mmu_idx, full->attrs, r, |
be5c4787 | 1452 | retaddr); |
04e3aabd | 1453 | } |
82a45b96 RH |
1454 | } |
1455 | ||
7e9a7c50 RH |
1456 | /* Return true if ADDR is present in the victim tlb, and has been copied |
1457 | back to the main tlb. */ | |
1458 | static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, | |
732d5487 | 1459 | MMUAccessType access_type, vaddr page) |
7e9a7c50 RH |
1460 | { |
1461 | size_t vidx; | |
71aec354 | 1462 | |
29a0af61 | 1463 | assert_cpu_is_self(env_cpu(env)); |
7e9a7c50 | 1464 | for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) { |
a40ec84e | 1465 | CPUTLBEntry *vtlb = &env_tlb(env)->d[mmu_idx].vtable[vidx]; |
9e39de98 | 1466 | uint64_t cmp = tlb_read_idx(vtlb, access_type); |
7e9a7c50 RH |
1467 | |
1468 | if (cmp == page) { | |
1469 | /* Found entry in victim tlb, swap tlb and iotlb. */ | |
a40ec84e | 1470 | CPUTLBEntry tmptlb, *tlb = &env_tlb(env)->f[mmu_idx].table[index]; |
b0706b71 | 1471 | |
a40ec84e | 1472 | qemu_spin_lock(&env_tlb(env)->c.lock); |
71aec354 EC |
1473 | copy_tlb_helper_locked(&tmptlb, tlb); |
1474 | copy_tlb_helper_locked(tlb, vtlb); | |
1475 | copy_tlb_helper_locked(vtlb, &tmptlb); | |
a40ec84e | 1476 | qemu_spin_unlock(&env_tlb(env)->c.lock); |
b0706b71 | 1477 | |
25d3ec58 RH |
1478 | CPUTLBEntryFull *f1 = &env_tlb(env)->d[mmu_idx].fulltlb[index]; |
1479 | CPUTLBEntryFull *f2 = &env_tlb(env)->d[mmu_idx].vfulltlb[vidx]; | |
1480 | CPUTLBEntryFull tmpf; | |
1481 | tmpf = *f1; *f1 = *f2; *f2 = tmpf; | |
7e9a7c50 RH |
1482 | return true; |
1483 | } | |
1484 | } | |
1485 | return false; | |
1486 | } | |
1487 | ||
707526ad | 1488 | static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, |
25d3ec58 | 1489 | CPUTLBEntryFull *full, uintptr_t retaddr) |
707526ad | 1490 | { |
25d3ec58 | 1491 | ram_addr_t ram_addr = mem_vaddr + full->xlat_section; |
707526ad RH |
1492 | |
1493 | trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); | |
1494 | ||
1495 | if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { | |
f349e92e | 1496 | tb_invalidate_phys_range_fast(ram_addr, size, retaddr); |
707526ad RH |
1497 | } |
1498 | ||
1499 | /* | |
1500 | * Set both VGA and migration bits for simplicity and to remove | |
1501 | * the notdirty callback faster. | |
1502 | */ | |
1503 | cpu_physical_memory_set_dirty_range(ram_addr, size, DIRTY_CLIENTS_NOCODE); | |
1504 | ||
1505 | /* We remove the notdirty callback only if the code has been flushed. */ | |
1506 | if (!cpu_physical_memory_is_clean(ram_addr)) { | |
1507 | trace_memory_notdirty_set_dirty(mem_vaddr); | |
1508 | tlb_set_dirty(cpu, mem_vaddr); | |
1509 | } | |
1510 | } | |
1511 | ||
4f8f4127 | 1512 | static int probe_access_internal(CPUArchState *env, vaddr addr, |
069cfe77 RH |
1513 | int fault_size, MMUAccessType access_type, |
1514 | int mmu_idx, bool nonfault, | |
af803a4f RH |
1515 | void **phost, CPUTLBEntryFull **pfull, |
1516 | uintptr_t retaddr) | |
3b08f0a9 | 1517 | { |
383beda9 RH |
1518 | uintptr_t index = tlb_index(env, mmu_idx, addr); |
1519 | CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); | |
9e39de98 | 1520 | uint64_t tlb_addr = tlb_read_idx(entry, access_type); |
4f8f4127 | 1521 | vaddr page_addr = addr & TARGET_PAGE_MASK; |
58e8f1f6 RH |
1522 | int flags = TLB_FLAGS_MASK & ~TLB_FORCE_SLOW; |
1523 | CPUTLBEntryFull *full; | |
c25c283d | 1524 | |
069cfe77 | 1525 | if (!tlb_hit_page(tlb_addr, page_addr)) { |
0b3c75ad | 1526 | if (!victim_tlb_hit(env, mmu_idx, index, access_type, page_addr)) { |
069cfe77 | 1527 | CPUState *cs = env_cpu(env); |
069cfe77 | 1528 | |
8810ee2a AB |
1529 | if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type, |
1530 | mmu_idx, nonfault, retaddr)) { | |
069cfe77 RH |
1531 | /* Non-faulting page table read failed. */ |
1532 | *phost = NULL; | |
af803a4f | 1533 | *pfull = NULL; |
069cfe77 RH |
1534 | return TLB_INVALID_MASK; |
1535 | } | |
1536 | ||
1537 | /* TLB resize via tlb_fill may have moved the entry. */ | |
af803a4f | 1538 | index = tlb_index(env, mmu_idx, addr); |
03a98189 | 1539 | entry = tlb_entry(env, mmu_idx, addr); |
c3c8bf57 RH |
1540 | |
1541 | /* | |
1542 | * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, | |
1543 | * to force the next access through tlb_fill. We've just | |
1544 | * called tlb_fill, so we know that this entry *is* valid. | |
1545 | */ | |
1546 | flags &= ~TLB_INVALID_MASK; | |
3b08f0a9 | 1547 | } |
0b3c75ad | 1548 | tlb_addr = tlb_read_idx(entry, access_type); |
03a98189 | 1549 | } |
c3c8bf57 | 1550 | flags &= tlb_addr; |
03a98189 | 1551 | |
58e8f1f6 RH |
1552 | *pfull = full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; |
1553 | flags |= full->slow_flags[access_type]; | |
af803a4f | 1554 | |
069cfe77 RH |
1555 | /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ |
1556 | if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { | |
1557 | *phost = NULL; | |
1558 | return TLB_MMIO; | |
fef39ccd DH |
1559 | } |
1560 | ||
069cfe77 RH |
1561 | /* Everything else is RAM. */ |
1562 | *phost = (void *)((uintptr_t)addr + entry->addend); | |
1563 | return flags; | |
1564 | } | |
1565 | ||
4f8f4127 | 1566 | int probe_access_full(CPUArchState *env, vaddr addr, int size, |
af803a4f RH |
1567 | MMUAccessType access_type, int mmu_idx, |
1568 | bool nonfault, void **phost, CPUTLBEntryFull **pfull, | |
1569 | uintptr_t retaddr) | |
069cfe77 | 1570 | { |
d507e6c5 | 1571 | int flags = probe_access_internal(env, addr, size, access_type, mmu_idx, |
af803a4f | 1572 | nonfault, phost, pfull, retaddr); |
069cfe77 RH |
1573 | |
1574 | /* Handle clean RAM pages. */ | |
1575 | if (unlikely(flags & TLB_NOTDIRTY)) { | |
af803a4f | 1576 | notdirty_write(env_cpu(env), addr, 1, *pfull, retaddr); |
069cfe77 RH |
1577 | flags &= ~TLB_NOTDIRTY; |
1578 | } | |
1579 | ||
1580 | return flags; | |
1581 | } | |
1582 | ||
4f8f4127 | 1583 | int probe_access_flags(CPUArchState *env, vaddr addr, int size, |
af803a4f RH |
1584 | MMUAccessType access_type, int mmu_idx, |
1585 | bool nonfault, void **phost, uintptr_t retaddr) | |
1586 | { | |
1587 | CPUTLBEntryFull *full; | |
1770b2f2 DHB |
1588 | int flags; |
1589 | ||
1590 | g_assert(-(addr | TARGET_PAGE_MASK) >= size); | |
1591 | ||
1592 | flags = probe_access_internal(env, addr, size, access_type, mmu_idx, | |
1593 | nonfault, phost, &full, retaddr); | |
af803a4f | 1594 | |
1770b2f2 DHB |
1595 | /* Handle clean RAM pages. */ |
1596 | if (unlikely(flags & TLB_NOTDIRTY)) { | |
1597 | notdirty_write(env_cpu(env), addr, 1, full, retaddr); | |
1598 | flags &= ~TLB_NOTDIRTY; | |
1599 | } | |
1600 | ||
1601 | return flags; | |
af803a4f RH |
1602 | } |
1603 | ||
4f8f4127 | 1604 | void *probe_access(CPUArchState *env, vaddr addr, int size, |
069cfe77 RH |
1605 | MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) |
1606 | { | |
af803a4f | 1607 | CPUTLBEntryFull *full; |
069cfe77 RH |
1608 | void *host; |
1609 | int flags; | |
1610 | ||
1611 | g_assert(-(addr | TARGET_PAGE_MASK) >= size); | |
1612 | ||
1613 | flags = probe_access_internal(env, addr, size, access_type, mmu_idx, | |
af803a4f | 1614 | false, &host, &full, retaddr); |
069cfe77 RH |
1615 | |
1616 | /* Per the interface, size == 0 merely faults the access. */ | |
1617 | if (size == 0) { | |
1618 | return NULL; | |
1619 | } | |
1620 | ||
1621 | if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { | |
73bc0bd4 | 1622 | /* Handle watchpoints. */ |
069cfe77 RH |
1623 | if (flags & TLB_WATCHPOINT) { |
1624 | int wp_access = (access_type == MMU_DATA_STORE | |
1625 | ? BP_MEM_WRITE : BP_MEM_READ); | |
73bc0bd4 | 1626 | cpu_check_watchpoint(env_cpu(env), addr, size, |
25d3ec58 | 1627 | full->attrs, wp_access, retaddr); |
73bc0bd4 RH |
1628 | } |
1629 | ||
1630 | /* Handle clean RAM pages. */ | |
069cfe77 | 1631 | if (flags & TLB_NOTDIRTY) { |
25d3ec58 | 1632 | notdirty_write(env_cpu(env), addr, 1, full, retaddr); |
73bc0bd4 | 1633 | } |
fef39ccd DH |
1634 | } |
1635 | ||
069cfe77 | 1636 | return host; |
3b08f0a9 RH |
1637 | } |
1638 | ||
4811e909 RH |
1639 | void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, |
1640 | MMUAccessType access_type, int mmu_idx) | |
1641 | { | |
af803a4f | 1642 | CPUTLBEntryFull *full; |
069cfe77 RH |
1643 | void *host; |
1644 | int flags; | |
4811e909 | 1645 | |
069cfe77 | 1646 | flags = probe_access_internal(env, addr, 0, access_type, |
af803a4f | 1647 | mmu_idx, true, &host, &full, 0); |
4811e909 | 1648 | |
069cfe77 RH |
1649 | /* No combination of flags are expected by the caller. */ |
1650 | return flags ? NULL : host; | |
4811e909 RH |
1651 | } |
1652 | ||
7e0d9973 RH |
1653 | /* |
1654 | * Return a ram_addr_t for the virtual address for execution. | |
1655 | * | |
1656 | * Return -1 if we can't translate and execute from an entire page | |
1657 | * of RAM. This will force us to execute by loading and translating | |
1658 | * one insn at a time, without caching. | |
1659 | * | |
1660 | * NOTE: This function will trigger an exception if the page is | |
1661 | * not executable. | |
1662 | */ | |
4f8f4127 | 1663 | tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, |
7e0d9973 RH |
1664 | void **hostp) |
1665 | { | |
af803a4f | 1666 | CPUTLBEntryFull *full; |
7e0d9973 RH |
1667 | void *p; |
1668 | ||
1669 | (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH, | |
af803a4f | 1670 | cpu_mmu_index(env, true), false, &p, &full, 0); |
7e0d9973 RH |
1671 | if (p == NULL) { |
1672 | return -1; | |
1673 | } | |
ac01ec6f WL |
1674 | |
1675 | if (full->lg_page_size < TARGET_PAGE_BITS) { | |
1676 | return -1; | |
1677 | } | |
1678 | ||
7e0d9973 RH |
1679 | if (hostp) { |
1680 | *hostp = p; | |
1681 | } | |
1682 | return qemu_ram_addr_from_host_nofail(p); | |
1683 | } | |
1684 | ||
cdfac37b RH |
1685 | /* Load/store with atomicity primitives. */ |
1686 | #include "ldst_atomicity.c.inc" | |
1687 | ||
235537fa AB |
1688 | #ifdef CONFIG_PLUGIN |
1689 | /* | |
1690 | * Perform a TLB lookup and populate the qemu_plugin_hwaddr structure. | |
1691 | * This should be a hot path as we will have just looked this path up | |
1692 | * in the softmmu lookup code (or helper). We don't handle re-fills or | |
1693 | * checking the victim table. This is purely informational. | |
1694 | * | |
2f3a57ee AB |
1695 | * This almost never fails as the memory access being instrumented |
1696 | * should have just filled the TLB. The one corner case is io_writex | |
1697 | * which can cause TLB flushes and potential resizing of the TLBs | |
570ef309 | 1698 | * losing the information we need. In those cases we need to recover |
25d3ec58 | 1699 | * data from a copy of the CPUTLBEntryFull. As long as this always occurs |
570ef309 | 1700 | * from the same thread (which a mem callback will be) this is safe. |
235537fa AB |
1701 | */ |
1702 | ||
732d5487 | 1703 | bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int mmu_idx, |
235537fa AB |
1704 | bool is_store, struct qemu_plugin_hwaddr *data) |
1705 | { | |
1706 | CPUArchState *env = cpu->env_ptr; | |
1707 | CPUTLBEntry *tlbe = tlb_entry(env, mmu_idx, addr); | |
1708 | uintptr_t index = tlb_index(env, mmu_idx, addr); | |
9e39de98 | 1709 | uint64_t tlb_addr = is_store ? tlb_addr_write(tlbe) : tlbe->addr_read; |
235537fa AB |
1710 | |
1711 | if (likely(tlb_hit(tlb_addr, addr))) { | |
1712 | /* We must have an iotlb entry for MMIO */ | |
1713 | if (tlb_addr & TLB_MMIO) { | |
25d3ec58 RH |
1714 | CPUTLBEntryFull *full; |
1715 | full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; | |
235537fa | 1716 | data->is_io = true; |
25d3ec58 RH |
1717 | data->v.io.section = |
1718 | iotlb_to_section(cpu, full->xlat_section, full->attrs); | |
1719 | data->v.io.offset = (full->xlat_section & TARGET_PAGE_MASK) + addr; | |
235537fa AB |
1720 | } else { |
1721 | data->is_io = false; | |
2d932039 | 1722 | data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend); |
235537fa AB |
1723 | } |
1724 | return true; | |
2f3a57ee AB |
1725 | } else { |
1726 | SavedIOTLB *saved = &cpu->saved_iotlb; | |
1727 | data->is_io = true; | |
1728 | data->v.io.section = saved->section; | |
1729 | data->v.io.offset = saved->mr_offset; | |
1730 | return true; | |
235537fa | 1731 | } |
235537fa AB |
1732 | } |
1733 | ||
1734 | #endif | |
1735 | ||
8cfdacaa RH |
1736 | /* |
1737 | * Probe for a load/store operation. | |
1738 | * Return the host address and into @flags. | |
1739 | */ | |
1740 | ||
1741 | typedef struct MMULookupPageData { | |
1742 | CPUTLBEntryFull *full; | |
1743 | void *haddr; | |
fb2c53cb | 1744 | vaddr addr; |
8cfdacaa RH |
1745 | int flags; |
1746 | int size; | |
1747 | } MMULookupPageData; | |
1748 | ||
1749 | typedef struct MMULookupLocals { | |
1750 | MMULookupPageData page[2]; | |
1751 | MemOp memop; | |
1752 | int mmu_idx; | |
1753 | } MMULookupLocals; | |
1754 | ||
1755 | /** | |
1756 | * mmu_lookup1: translate one page | |
1757 | * @env: cpu context | |
1758 | * @data: lookup parameters | |
1759 | * @mmu_idx: virtual address context | |
1760 | * @access_type: load/store/code | |
1761 | * @ra: return address into tcg generated code, or 0 | |
1762 | * | |
1763 | * Resolve the translation for the one page at @data.addr, filling in | |
1764 | * the rest of @data with the results. If the translation fails, | |
1765 | * tlb_fill will longjmp out. Return true if the softmmu tlb for | |
1766 | * @mmu_idx may have resized. | |
1767 | */ | |
1768 | static bool mmu_lookup1(CPUArchState *env, MMULookupPageData *data, | |
1769 | int mmu_idx, MMUAccessType access_type, uintptr_t ra) | |
1770 | { | |
fb2c53cb | 1771 | vaddr addr = data->addr; |
8cfdacaa RH |
1772 | uintptr_t index = tlb_index(env, mmu_idx, addr); |
1773 | CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); | |
9e39de98 | 1774 | uint64_t tlb_addr = tlb_read_idx(entry, access_type); |
8cfdacaa | 1775 | bool maybe_resized = false; |
58e8f1f6 RH |
1776 | CPUTLBEntryFull *full; |
1777 | int flags; | |
8cfdacaa RH |
1778 | |
1779 | /* If the TLB entry is for a different page, reload and try again. */ | |
1780 | if (!tlb_hit(tlb_addr, addr)) { | |
1781 | if (!victim_tlb_hit(env, mmu_idx, index, access_type, | |
1782 | addr & TARGET_PAGE_MASK)) { | |
1783 | tlb_fill(env_cpu(env), addr, data->size, access_type, mmu_idx, ra); | |
1784 | maybe_resized = true; | |
1785 | index = tlb_index(env, mmu_idx, addr); | |
1786 | entry = tlb_entry(env, mmu_idx, addr); | |
1787 | } | |
1788 | tlb_addr = tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK; | |
1789 | } | |
1790 | ||
58e8f1f6 RH |
1791 | full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; |
1792 | flags = tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); | |
1793 | flags |= full->slow_flags[access_type]; | |
1794 | ||
1795 | data->full = full; | |
1796 | data->flags = flags; | |
8cfdacaa RH |
1797 | /* Compute haddr speculatively; depending on flags it might be invalid. */ |
1798 | data->haddr = (void *)((uintptr_t)addr + entry->addend); | |
1799 | ||
1800 | return maybe_resized; | |
1801 | } | |
1802 | ||
1803 | /** | |
1804 | * mmu_watch_or_dirty | |
1805 | * @env: cpu context | |
1806 | * @data: lookup parameters | |
1807 | * @access_type: load/store/code | |
1808 | * @ra: return address into tcg generated code, or 0 | |
1809 | * | |
1810 | * Trigger watchpoints for @data.addr:@data.size; | |
1811 | * record writes to protected clean pages. | |
1812 | */ | |
1813 | static void mmu_watch_or_dirty(CPUArchState *env, MMULookupPageData *data, | |
1814 | MMUAccessType access_type, uintptr_t ra) | |
1815 | { | |
1816 | CPUTLBEntryFull *full = data->full; | |
fb2c53cb | 1817 | vaddr addr = data->addr; |
8cfdacaa RH |
1818 | int flags = data->flags; |
1819 | int size = data->size; | |
1820 | ||
1821 | /* On watchpoint hit, this will longjmp out. */ | |
1822 | if (flags & TLB_WATCHPOINT) { | |
1823 | int wp = access_type == MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ; | |
1824 | cpu_check_watchpoint(env_cpu(env), addr, size, full->attrs, wp, ra); | |
1825 | flags &= ~TLB_WATCHPOINT; | |
1826 | } | |
1827 | ||
1828 | /* Note that notdirty is only set for writes. */ | |
1829 | if (flags & TLB_NOTDIRTY) { | |
1830 | notdirty_write(env_cpu(env), addr, size, full, ra); | |
1831 | flags &= ~TLB_NOTDIRTY; | |
1832 | } | |
1833 | data->flags = flags; | |
1834 | } | |
1835 | ||
1836 | /** | |
1837 | * mmu_lookup: translate page(s) | |
1838 | * @env: cpu context | |
1839 | * @addr: virtual address | |
1840 | * @oi: combined mmu_idx and MemOp | |
1841 | * @ra: return address into tcg generated code, or 0 | |
1842 | * @access_type: load/store/code | |
1843 | * @l: output result | |
1844 | * | |
1845 | * Resolve the translation for the page(s) beginning at @addr, for MemOp.size | |
1846 | * bytes. Return true if the lookup crosses a page boundary. | |
1847 | */ | |
fb2c53cb | 1848 | static bool mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi, |
8cfdacaa RH |
1849 | uintptr_t ra, MMUAccessType type, MMULookupLocals *l) |
1850 | { | |
1851 | unsigned a_bits; | |
1852 | bool crosspage; | |
1853 | int flags; | |
1854 | ||
1855 | l->memop = get_memop(oi); | |
1856 | l->mmu_idx = get_mmuidx(oi); | |
1857 | ||
1858 | tcg_debug_assert(l->mmu_idx < NB_MMU_MODES); | |
1859 | ||
1860 | /* Handle CPU specific unaligned behaviour */ | |
1861 | a_bits = get_alignment_bits(l->memop); | |
1862 | if (addr & ((1 << a_bits) - 1)) { | |
1863 | cpu_unaligned_access(env_cpu(env), addr, type, l->mmu_idx, ra); | |
1864 | } | |
1865 | ||
1866 | l->page[0].addr = addr; | |
1867 | l->page[0].size = memop_size(l->memop); | |
1868 | l->page[1].addr = (addr + l->page[0].size - 1) & TARGET_PAGE_MASK; | |
1869 | l->page[1].size = 0; | |
1870 | crosspage = (addr ^ l->page[1].addr) & TARGET_PAGE_MASK; | |
1871 | ||
1872 | if (likely(!crosspage)) { | |
1873 | mmu_lookup1(env, &l->page[0], l->mmu_idx, type, ra); | |
1874 | ||
1875 | flags = l->page[0].flags; | |
1876 | if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { | |
1877 | mmu_watch_or_dirty(env, &l->page[0], type, ra); | |
1878 | } | |
1879 | if (unlikely(flags & TLB_BSWAP)) { | |
1880 | l->memop ^= MO_BSWAP; | |
1881 | } | |
1882 | } else { | |
1883 | /* Finish compute of page crossing. */ | |
1884 | int size0 = l->page[1].addr - addr; | |
1885 | l->page[1].size = l->page[0].size - size0; | |
1886 | l->page[0].size = size0; | |
1887 | ||
1888 | /* | |
1889 | * Lookup both pages, recognizing exceptions from either. If the | |
1890 | * second lookup potentially resized, refresh first CPUTLBEntryFull. | |
1891 | */ | |
1892 | mmu_lookup1(env, &l->page[0], l->mmu_idx, type, ra); | |
1893 | if (mmu_lookup1(env, &l->page[1], l->mmu_idx, type, ra)) { | |
1894 | uintptr_t index = tlb_index(env, l->mmu_idx, addr); | |
1895 | l->page[0].full = &env_tlb(env)->d[l->mmu_idx].fulltlb[index]; | |
1896 | } | |
1897 | ||
1898 | flags = l->page[0].flags | l->page[1].flags; | |
1899 | if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { | |
1900 | mmu_watch_or_dirty(env, &l->page[0], type, ra); | |
1901 | mmu_watch_or_dirty(env, &l->page[1], type, ra); | |
1902 | } | |
1903 | ||
1904 | /* | |
1905 | * Since target/sparc is the only user of TLB_BSWAP, and all | |
1906 | * Sparc accesses are aligned, any treatment across two pages | |
1907 | * would be arbitrary. Refuse it until there's a use. | |
1908 | */ | |
1909 | tcg_debug_assert((flags & TLB_BSWAP) == 0); | |
1910 | } | |
1911 | ||
1912 | return crosspage; | |
1913 | } | |
1914 | ||
08dff435 RH |
1915 | /* |
1916 | * Probe for an atomic operation. Do not allow unaligned operations, | |
1917 | * or io operations to proceed. Return the host address. | |
08dff435 | 1918 | */ |
b0326eb9 AJ |
1919 | static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi, |
1920 | int size, uintptr_t retaddr) | |
c482cb11 | 1921 | { |
b826044f | 1922 | uintptr_t mmu_idx = get_mmuidx(oi); |
14776ab5 | 1923 | MemOp mop = get_memop(oi); |
c482cb11 | 1924 | int a_bits = get_alignment_bits(mop); |
08dff435 RH |
1925 | uintptr_t index; |
1926 | CPUTLBEntry *tlbe; | |
b0326eb9 | 1927 | vaddr tlb_addr; |
34d49937 | 1928 | void *hostaddr; |
417aeaff | 1929 | CPUTLBEntryFull *full; |
c482cb11 | 1930 | |
b826044f RH |
1931 | tcg_debug_assert(mmu_idx < NB_MMU_MODES); |
1932 | ||
c482cb11 RH |
1933 | /* Adjust the given return address. */ |
1934 | retaddr -= GETPC_ADJ; | |
1935 | ||
1936 | /* Enforce guest required alignment. */ | |
1937 | if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) { | |
1938 | /* ??? Maybe indicate atomic op to cpu_unaligned_access */ | |
29a0af61 | 1939 | cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, |
c482cb11 RH |
1940 | mmu_idx, retaddr); |
1941 | } | |
1942 | ||
1943 | /* Enforce qemu required alignment. */ | |
08dff435 | 1944 | if (unlikely(addr & (size - 1))) { |
c482cb11 RH |
1945 | /* We get here if guest alignment was not requested, |
1946 | or was not enforced by cpu_unaligned_access above. | |
1947 | We might widen the access and emulate, but for now | |
1948 | mark an exception and exit the cpu loop. */ | |
1949 | goto stop_the_world; | |
1950 | } | |
1951 | ||
08dff435 RH |
1952 | index = tlb_index(env, mmu_idx, addr); |
1953 | tlbe = tlb_entry(env, mmu_idx, addr); | |
1954 | ||
c482cb11 | 1955 | /* Check TLB entry and enforce page permissions. */ |
7bedee32 RH |
1956 | tlb_addr = tlb_addr_write(tlbe); |
1957 | if (!tlb_hit(tlb_addr, addr)) { | |
1958 | if (!victim_tlb_hit(env, mmu_idx, index, MMU_DATA_STORE, | |
1959 | addr & TARGET_PAGE_MASK)) { | |
1960 | tlb_fill(env_cpu(env), addr, size, | |
1961 | MMU_DATA_STORE, mmu_idx, retaddr); | |
1962 | index = tlb_index(env, mmu_idx, addr); | |
1963 | tlbe = tlb_entry(env, mmu_idx, addr); | |
08dff435 | 1964 | } |
7bedee32 RH |
1965 | tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; |
1966 | } | |
08dff435 | 1967 | |
7bedee32 RH |
1968 | /* |
1969 | * Let the guest notice RMW on a write-only page. | |
1970 | * We have just verified that the page is writable. | |
1971 | * Subpage lookups may have left TLB_INVALID_MASK set, | |
1972 | * but addr_read will only be -1 if PAGE_READ was unset. | |
1973 | */ | |
1974 | if (unlikely(tlbe->addr_read == -1)) { | |
1975 | tlb_fill(env_cpu(env), addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); | |
1976 | /* | |
1977 | * Since we don't support reads and writes to different | |
1978 | * addresses, and we do have the proper page loaded for | |
1979 | * write, this shouldn't ever return. But just in case, | |
1980 | * handle via stop-the-world. | |
1981 | */ | |
1982 | goto stop_the_world; | |
c482cb11 | 1983 | } |
187ba694 | 1984 | /* Collect tlb flags for read. */ |
7bedee32 | 1985 | tlb_addr |= tlbe->addr_read; |
c482cb11 | 1986 | |
55df6fcf | 1987 | /* Notice an IO access or a needs-MMU-lookup access */ |
0953674e | 1988 | if (unlikely(tlb_addr & (TLB_MMIO | TLB_DISCARD_WRITE))) { |
c482cb11 RH |
1989 | /* There's really nothing that can be done to |
1990 | support this apart from stop-the-world. */ | |
1991 | goto stop_the_world; | |
1992 | } | |
1993 | ||
34d49937 | 1994 | hostaddr = (void *)((uintptr_t)addr + tlbe->addend); |
417aeaff | 1995 | full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; |
34d49937 | 1996 | |
34d49937 | 1997 | if (unlikely(tlb_addr & TLB_NOTDIRTY)) { |
417aeaff RH |
1998 | notdirty_write(env_cpu(env), addr, size, full, retaddr); |
1999 | } | |
2000 | ||
187ba694 RH |
2001 | if (unlikely(tlb_addr & TLB_FORCE_SLOW)) { |
2002 | int wp_flags = 0; | |
2003 | ||
2004 | if (full->slow_flags[MMU_DATA_STORE] & TLB_WATCHPOINT) { | |
2005 | wp_flags |= BP_MEM_WRITE; | |
2006 | } | |
2007 | if (full->slow_flags[MMU_DATA_LOAD] & TLB_WATCHPOINT) { | |
2008 | wp_flags |= BP_MEM_READ; | |
2009 | } | |
2010 | if (wp_flags) { | |
2011 | cpu_check_watchpoint(env_cpu(env), addr, size, | |
2012 | full->attrs, wp_flags, retaddr); | |
2013 | } | |
34d49937 PM |
2014 | } |
2015 | ||
2016 | return hostaddr; | |
c482cb11 RH |
2017 | |
2018 | stop_the_world: | |
29a0af61 | 2019 | cpu_loop_exit_atomic(env_cpu(env), retaddr); |
c482cb11 RH |
2020 | } |
2021 | ||
eed56642 AB |
2022 | /* |
2023 | * Load Helpers | |
2024 | * | |
2025 | * We support two different access types. SOFTMMU_CODE_ACCESS is | |
2026 | * specifically for reading instructions from system memory. It is | |
2027 | * called by the translation loop and in some helpers where the code | |
2028 | * is disassembled. It shouldn't be called directly by guest code. | |
cdfac37b | 2029 | * |
8cfdacaa RH |
2030 | * For the benefit of TCG generated code, we want to avoid the |
2031 | * complication of ABI-specific return type promotion and always | |
2032 | * return a value extended to the register size of the host. This is | |
2033 | * tcg_target_long, except in the case of a 32-bit host and 64-bit | |
2034 | * data, and for that we always have uint64_t. | |
2035 | * | |
2036 | * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. | |
2037 | */ | |
b826044f | 2038 | |
8cfdacaa RH |
2039 | /** |
2040 | * do_ld_mmio_beN: | |
2041 | * @env: cpu context | |
2042 | * @p: translation parameters | |
2043 | * @ret_be: accumulated data | |
2044 | * @mmu_idx: virtual address context | |
2045 | * @ra: return address into tcg generated code, or 0 | |
2046 | * | |
2047 | * Load @p->size bytes from @p->addr, which is memory-mapped i/o. | |
2048 | * The bytes are concatenated in big-endian order with @ret_be. | |
2049 | */ | |
2050 | static uint64_t do_ld_mmio_beN(CPUArchState *env, MMULookupPageData *p, | |
2051 | uint64_t ret_be, int mmu_idx, | |
2052 | MMUAccessType type, uintptr_t ra) | |
2053 | { | |
2054 | CPUTLBEntryFull *full = p->full; | |
fb2c53cb | 2055 | vaddr addr = p->addr; |
8cfdacaa | 2056 | int i, size = p->size; |
eed56642 | 2057 | |
8cfdacaa RH |
2058 | QEMU_IOTHREAD_LOCK_GUARD(); |
2059 | for (i = 0; i < size; i++) { | |
2060 | uint8_t x = io_readx(env, full, mmu_idx, addr + i, ra, type, MO_UB); | |
2061 | ret_be = (ret_be << 8) | x; | |
eed56642 | 2062 | } |
8cfdacaa RH |
2063 | return ret_be; |
2064 | } | |
0f590e74 | 2065 | |
8cfdacaa RH |
2066 | /** |
2067 | * do_ld_bytes_beN | |
2068 | * @p: translation parameters | |
2069 | * @ret_be: accumulated data | |
2070 | * | |
2071 | * Load @p->size bytes from @p->haddr, which is RAM. | |
2072 | * The bytes to concatenated in big-endian order with @ret_be. | |
2073 | */ | |
2074 | static uint64_t do_ld_bytes_beN(MMULookupPageData *p, uint64_t ret_be) | |
2075 | { | |
2076 | uint8_t *haddr = p->haddr; | |
2077 | int i, size = p->size; | |
b826044f | 2078 | |
8cfdacaa RH |
2079 | for (i = 0; i < size; i++) { |
2080 | ret_be = (ret_be << 8) | haddr[i]; | |
eed56642 | 2081 | } |
8cfdacaa RH |
2082 | return ret_be; |
2083 | } | |
eed56642 | 2084 | |
cdfac37b RH |
2085 | /** |
2086 | * do_ld_parts_beN | |
2087 | * @p: translation parameters | |
2088 | * @ret_be: accumulated data | |
2089 | * | |
2090 | * As do_ld_bytes_beN, but atomically on each aligned part. | |
2091 | */ | |
2092 | static uint64_t do_ld_parts_beN(MMULookupPageData *p, uint64_t ret_be) | |
2093 | { | |
2094 | void *haddr = p->haddr; | |
2095 | int size = p->size; | |
2096 | ||
2097 | do { | |
2098 | uint64_t x; | |
2099 | int n; | |
2100 | ||
2101 | /* | |
2102 | * Find minimum of alignment and size. | |
2103 | * This is slightly stronger than required by MO_ATOM_SUBALIGN, which | |
2104 | * would have only checked the low bits of addr|size once at the start, | |
2105 | * but is just as easy. | |
2106 | */ | |
2107 | switch (((uintptr_t)haddr | size) & 7) { | |
2108 | case 4: | |
2109 | x = cpu_to_be32(load_atomic4(haddr)); | |
2110 | ret_be = (ret_be << 32) | x; | |
2111 | n = 4; | |
2112 | break; | |
2113 | case 2: | |
2114 | case 6: | |
2115 | x = cpu_to_be16(load_atomic2(haddr)); | |
2116 | ret_be = (ret_be << 16) | x; | |
2117 | n = 2; | |
2118 | break; | |
2119 | default: | |
2120 | x = *(uint8_t *)haddr; | |
2121 | ret_be = (ret_be << 8) | x; | |
2122 | n = 1; | |
2123 | break; | |
2124 | case 0: | |
2125 | g_assert_not_reached(); | |
2126 | } | |
2127 | haddr += n; | |
2128 | size -= n; | |
2129 | } while (size != 0); | |
2130 | return ret_be; | |
2131 | } | |
2132 | ||
2133 | /** | |
2134 | * do_ld_parts_be4 | |
2135 | * @p: translation parameters | |
2136 | * @ret_be: accumulated data | |
2137 | * | |
2138 | * As do_ld_bytes_beN, but with one atomic load. | |
2139 | * Four aligned bytes are guaranteed to cover the load. | |
2140 | */ | |
2141 | static uint64_t do_ld_whole_be4(MMULookupPageData *p, uint64_t ret_be) | |
2142 | { | |
2143 | int o = p->addr & 3; | |
2144 | uint32_t x = load_atomic4(p->haddr - o); | |
2145 | ||
2146 | x = cpu_to_be32(x); | |
2147 | x <<= o * 8; | |
2148 | x >>= (4 - p->size) * 8; | |
2149 | return (ret_be << (p->size * 8)) | x; | |
2150 | } | |
2151 | ||
2152 | /** | |
2153 | * do_ld_parts_be8 | |
2154 | * @p: translation parameters | |
2155 | * @ret_be: accumulated data | |
2156 | * | |
2157 | * As do_ld_bytes_beN, but with one atomic load. | |
2158 | * Eight aligned bytes are guaranteed to cover the load. | |
2159 | */ | |
2160 | static uint64_t do_ld_whole_be8(CPUArchState *env, uintptr_t ra, | |
2161 | MMULookupPageData *p, uint64_t ret_be) | |
2162 | { | |
2163 | int o = p->addr & 7; | |
2164 | uint64_t x = load_atomic8_or_exit(env, ra, p->haddr - o); | |
2165 | ||
2166 | x = cpu_to_be64(x); | |
2167 | x <<= o * 8; | |
2168 | x >>= (8 - p->size) * 8; | |
2169 | return (ret_be << (p->size * 8)) | x; | |
2170 | } | |
2171 | ||
35c653c4 RH |
2172 | /** |
2173 | * do_ld_parts_be16 | |
2174 | * @p: translation parameters | |
2175 | * @ret_be: accumulated data | |
2176 | * | |
2177 | * As do_ld_bytes_beN, but with one atomic load. | |
2178 | * 16 aligned bytes are guaranteed to cover the load. | |
2179 | */ | |
2180 | static Int128 do_ld_whole_be16(CPUArchState *env, uintptr_t ra, | |
2181 | MMULookupPageData *p, uint64_t ret_be) | |
2182 | { | |
2183 | int o = p->addr & 15; | |
2184 | Int128 x, y = load_atomic16_or_exit(env, ra, p->haddr - o); | |
2185 | int size = p->size; | |
2186 | ||
2187 | if (!HOST_BIG_ENDIAN) { | |
2188 | y = bswap128(y); | |
2189 | } | |
2190 | y = int128_lshift(y, o * 8); | |
2191 | y = int128_urshift(y, (16 - size) * 8); | |
2192 | x = int128_make64(ret_be); | |
2193 | x = int128_lshift(x, size * 8); | |
2194 | return int128_or(x, y); | |
2195 | } | |
2196 | ||
8cfdacaa RH |
2197 | /* |
2198 | * Wrapper for the above. | |
2199 | */ | |
2200 | static uint64_t do_ld_beN(CPUArchState *env, MMULookupPageData *p, | |
cdfac37b RH |
2201 | uint64_t ret_be, int mmu_idx, MMUAccessType type, |
2202 | MemOp mop, uintptr_t ra) | |
8cfdacaa | 2203 | { |
cdfac37b RH |
2204 | MemOp atom; |
2205 | unsigned tmp, half_size; | |
2206 | ||
8cfdacaa RH |
2207 | if (unlikely(p->flags & TLB_MMIO)) { |
2208 | return do_ld_mmio_beN(env, p, ret_be, mmu_idx, type, ra); | |
cdfac37b RH |
2209 | } |
2210 | ||
2211 | /* | |
2212 | * It is a given that we cross a page and therefore there is no | |
2213 | * atomicity for the load as a whole, but subobjects may need attention. | |
2214 | */ | |
2215 | atom = mop & MO_ATOM_MASK; | |
2216 | switch (atom) { | |
2217 | case MO_ATOM_SUBALIGN: | |
2218 | return do_ld_parts_beN(p, ret_be); | |
2219 | ||
2220 | case MO_ATOM_IFALIGN_PAIR: | |
2221 | case MO_ATOM_WITHIN16_PAIR: | |
2222 | tmp = mop & MO_SIZE; | |
2223 | tmp = tmp ? tmp - 1 : 0; | |
2224 | half_size = 1 << tmp; | |
2225 | if (atom == MO_ATOM_IFALIGN_PAIR | |
2226 | ? p->size == half_size | |
2227 | : p->size >= half_size) { | |
2228 | if (!HAVE_al8_fast && p->size < 4) { | |
2229 | return do_ld_whole_be4(p, ret_be); | |
2230 | } else { | |
2231 | return do_ld_whole_be8(env, ra, p, ret_be); | |
2232 | } | |
2233 | } | |
2234 | /* fall through */ | |
2235 | ||
2236 | case MO_ATOM_IFALIGN: | |
2237 | case MO_ATOM_WITHIN16: | |
2238 | case MO_ATOM_NONE: | |
8cfdacaa | 2239 | return do_ld_bytes_beN(p, ret_be); |
cdfac37b RH |
2240 | |
2241 | default: | |
2242 | g_assert_not_reached(); | |
8cfdacaa RH |
2243 | } |
2244 | } | |
50b107c5 | 2245 | |
35c653c4 RH |
2246 | /* |
2247 | * Wrapper for the above, for 8 < size < 16. | |
2248 | */ | |
2249 | static Int128 do_ld16_beN(CPUArchState *env, MMULookupPageData *p, | |
2250 | uint64_t a, int mmu_idx, MemOp mop, uintptr_t ra) | |
2251 | { | |
2252 | int size = p->size; | |
2253 | uint64_t b; | |
2254 | MemOp atom; | |
2255 | ||
2256 | if (unlikely(p->flags & TLB_MMIO)) { | |
2257 | p->size = size - 8; | |
2258 | a = do_ld_mmio_beN(env, p, a, mmu_idx, MMU_DATA_LOAD, ra); | |
2259 | p->addr += p->size; | |
2260 | p->size = 8; | |
2261 | b = do_ld_mmio_beN(env, p, 0, mmu_idx, MMU_DATA_LOAD, ra); | |
2262 | return int128_make128(b, a); | |
2263 | } | |
2264 | ||
2265 | /* | |
2266 | * It is a given that we cross a page and therefore there is no | |
2267 | * atomicity for the load as a whole, but subobjects may need attention. | |
2268 | */ | |
2269 | atom = mop & MO_ATOM_MASK; | |
2270 | switch (atom) { | |
2271 | case MO_ATOM_SUBALIGN: | |
2272 | p->size = size - 8; | |
2273 | a = do_ld_parts_beN(p, a); | |
2274 | p->haddr += size - 8; | |
2275 | p->size = 8; | |
2276 | b = do_ld_parts_beN(p, 0); | |
2277 | break; | |
2278 | ||
2279 | case MO_ATOM_WITHIN16_PAIR: | |
2280 | /* Since size > 8, this is the half that must be atomic. */ | |
2281 | return do_ld_whole_be16(env, ra, p, a); | |
2282 | ||
2283 | case MO_ATOM_IFALIGN_PAIR: | |
2284 | /* | |
2285 | * Since size > 8, both halves are misaligned, | |
2286 | * and so neither is atomic. | |
2287 | */ | |
2288 | case MO_ATOM_IFALIGN: | |
2289 | case MO_ATOM_WITHIN16: | |
2290 | case MO_ATOM_NONE: | |
2291 | p->size = size - 8; | |
2292 | a = do_ld_bytes_beN(p, a); | |
2293 | b = ldq_be_p(p->haddr + size - 8); | |
2294 | break; | |
2295 | ||
2296 | default: | |
2297 | g_assert_not_reached(); | |
2298 | } | |
2299 | ||
2300 | return int128_make128(b, a); | |
2301 | } | |
2302 | ||
8cfdacaa RH |
2303 | static uint8_t do_ld_1(CPUArchState *env, MMULookupPageData *p, int mmu_idx, |
2304 | MMUAccessType type, uintptr_t ra) | |
2305 | { | |
2306 | if (unlikely(p->flags & TLB_MMIO)) { | |
2307 | return io_readx(env, p->full, mmu_idx, p->addr, ra, type, MO_UB); | |
2308 | } else { | |
2309 | return *(uint8_t *)p->haddr; | |
2310 | } | |
2311 | } | |
50b107c5 | 2312 | |
8cfdacaa RH |
2313 | static uint16_t do_ld_2(CPUArchState *env, MMULookupPageData *p, int mmu_idx, |
2314 | MMUAccessType type, MemOp memop, uintptr_t ra) | |
2315 | { | |
2316 | uint64_t ret; | |
50b107c5 | 2317 | |
8cfdacaa RH |
2318 | if (unlikely(p->flags & TLB_MMIO)) { |
2319 | return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop); | |
2320 | } | |
50b107c5 | 2321 | |
8cfdacaa | 2322 | /* Perform the load host endian, then swap if necessary. */ |
cdfac37b | 2323 | ret = load_atom_2(env, ra, p->haddr, memop); |
8cfdacaa RH |
2324 | if (memop & MO_BSWAP) { |
2325 | ret = bswap16(ret); | |
2326 | } | |
2327 | return ret; | |
2328 | } | |
5b87b3e6 | 2329 | |
8cfdacaa RH |
2330 | static uint32_t do_ld_4(CPUArchState *env, MMULookupPageData *p, int mmu_idx, |
2331 | MMUAccessType type, MemOp memop, uintptr_t ra) | |
2332 | { | |
2333 | uint32_t ret; | |
5b87b3e6 | 2334 | |
8cfdacaa RH |
2335 | if (unlikely(p->flags & TLB_MMIO)) { |
2336 | return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop); | |
2337 | } | |
5b87b3e6 | 2338 | |
8cfdacaa | 2339 | /* Perform the load host endian. */ |
cdfac37b | 2340 | ret = load_atom_4(env, ra, p->haddr, memop); |
8cfdacaa RH |
2341 | if (memop & MO_BSWAP) { |
2342 | ret = bswap32(ret); | |
eed56642 | 2343 | } |
8cfdacaa RH |
2344 | return ret; |
2345 | } | |
eed56642 | 2346 | |
8cfdacaa RH |
2347 | static uint64_t do_ld_8(CPUArchState *env, MMULookupPageData *p, int mmu_idx, |
2348 | MMUAccessType type, MemOp memop, uintptr_t ra) | |
2349 | { | |
2350 | uint64_t ret; | |
2351 | ||
2352 | if (unlikely(p->flags & TLB_MMIO)) { | |
2353 | return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop); | |
eed56642 AB |
2354 | } |
2355 | ||
8cfdacaa | 2356 | /* Perform the load host endian. */ |
cdfac37b | 2357 | ret = load_atom_8(env, ra, p->haddr, memop); |
8cfdacaa RH |
2358 | if (memop & MO_BSWAP) { |
2359 | ret = bswap64(ret); | |
2360 | } | |
2361 | return ret; | |
eed56642 AB |
2362 | } |
2363 | ||
fb2c53cb | 2364 | static uint8_t do_ld1_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, |
8cfdacaa | 2365 | uintptr_t ra, MMUAccessType access_type) |
2dd92606 | 2366 | { |
8cfdacaa RH |
2367 | MMULookupLocals l; |
2368 | bool crosspage; | |
2369 | ||
f86e8f3d | 2370 | cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); |
8cfdacaa RH |
2371 | crosspage = mmu_lookup(env, addr, oi, ra, access_type, &l); |
2372 | tcg_debug_assert(!crosspage); | |
2373 | ||
2374 | return do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); | |
2dd92606 RH |
2375 | } |
2376 | ||
24e46e6c | 2377 | tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, |
0cadc1ed | 2378 | MemOpIdx oi, uintptr_t retaddr) |
eed56642 | 2379 | { |
0cadc1ed | 2380 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_8); |
8cfdacaa | 2381 | return do_ld1_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); |
2dd92606 RH |
2382 | } |
2383 | ||
fb2c53cb | 2384 | static uint16_t do_ld2_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, |
8cfdacaa | 2385 | uintptr_t ra, MMUAccessType access_type) |
2dd92606 | 2386 | { |
8cfdacaa RH |
2387 | MMULookupLocals l; |
2388 | bool crosspage; | |
2389 | uint16_t ret; | |
2390 | uint8_t a, b; | |
2391 | ||
f86e8f3d | 2392 | cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); |
8cfdacaa RH |
2393 | crosspage = mmu_lookup(env, addr, oi, ra, access_type, &l); |
2394 | if (likely(!crosspage)) { | |
2395 | return do_ld_2(env, &l.page[0], l.mmu_idx, access_type, l.memop, ra); | |
2396 | } | |
2397 | ||
2398 | a = do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); | |
2399 | b = do_ld_1(env, &l.page[1], l.mmu_idx, access_type, ra); | |
2400 | ||
2401 | if ((l.memop & MO_BSWAP) == MO_LE) { | |
2402 | ret = a | (b << 8); | |
2403 | } else { | |
2404 | ret = b | (a << 8); | |
2405 | } | |
2406 | return ret; | |
eed56642 AB |
2407 | } |
2408 | ||
24e46e6c | 2409 | tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, |
0cadc1ed | 2410 | MemOpIdx oi, uintptr_t retaddr) |
eed56642 | 2411 | { |
0cadc1ed | 2412 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16); |
8cfdacaa | 2413 | return do_ld2_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); |
2dd92606 RH |
2414 | } |
2415 | ||
fb2c53cb | 2416 | static uint32_t do_ld4_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, |
8cfdacaa | 2417 | uintptr_t ra, MMUAccessType access_type) |
2dd92606 | 2418 | { |
8cfdacaa RH |
2419 | MMULookupLocals l; |
2420 | bool crosspage; | |
2421 | uint32_t ret; | |
2422 | ||
f86e8f3d | 2423 | cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); |
8cfdacaa RH |
2424 | crosspage = mmu_lookup(env, addr, oi, ra, access_type, &l); |
2425 | if (likely(!crosspage)) { | |
2426 | return do_ld_4(env, &l.page[0], l.mmu_idx, access_type, l.memop, ra); | |
2427 | } | |
2428 | ||
cdfac37b RH |
2429 | ret = do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, l.memop, ra); |
2430 | ret = do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, l.memop, ra); | |
8cfdacaa RH |
2431 | if ((l.memop & MO_BSWAP) == MO_LE) { |
2432 | ret = bswap32(ret); | |
2433 | } | |
2434 | return ret; | |
eed56642 AB |
2435 | } |
2436 | ||
24e46e6c | 2437 | tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, |
0cadc1ed | 2438 | MemOpIdx oi, uintptr_t retaddr) |
eed56642 | 2439 | { |
0cadc1ed | 2440 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32); |
8cfdacaa | 2441 | return do_ld4_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); |
eed56642 AB |
2442 | } |
2443 | ||
fb2c53cb | 2444 | static uint64_t do_ld8_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, |
8cfdacaa | 2445 | uintptr_t ra, MMUAccessType access_type) |
eed56642 | 2446 | { |
8cfdacaa RH |
2447 | MMULookupLocals l; |
2448 | bool crosspage; | |
2449 | uint64_t ret; | |
2450 | ||
f86e8f3d | 2451 | cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); |
8cfdacaa RH |
2452 | crosspage = mmu_lookup(env, addr, oi, ra, access_type, &l); |
2453 | if (likely(!crosspage)) { | |
2454 | return do_ld_8(env, &l.page[0], l.mmu_idx, access_type, l.memop, ra); | |
2455 | } | |
2456 | ||
cdfac37b RH |
2457 | ret = do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, l.memop, ra); |
2458 | ret = do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, l.memop, ra); | |
8cfdacaa RH |
2459 | if ((l.memop & MO_BSWAP) == MO_LE) { |
2460 | ret = bswap64(ret); | |
2461 | } | |
2462 | return ret; | |
eed56642 AB |
2463 | } |
2464 | ||
24e46e6c | 2465 | uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, |
0cadc1ed | 2466 | MemOpIdx oi, uintptr_t retaddr) |
eed56642 | 2467 | { |
0cadc1ed | 2468 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64); |
8cfdacaa | 2469 | return do_ld8_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); |
eed56642 AB |
2470 | } |
2471 | ||
2472 | /* | |
2473 | * Provide signed versions of the load routines as well. We can of course | |
2474 | * avoid this for 64-bit data, or for 32-bit data on 32-bit host. | |
2475 | */ | |
2476 | ||
24e46e6c | 2477 | tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, |
0cadc1ed | 2478 | MemOpIdx oi, uintptr_t retaddr) |
eed56642 | 2479 | { |
0cadc1ed | 2480 | return (int8_t)helper_ldub_mmu(env, addr, oi, retaddr); |
eed56642 AB |
2481 | } |
2482 | ||
24e46e6c | 2483 | tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, |
0cadc1ed | 2484 | MemOpIdx oi, uintptr_t retaddr) |
eed56642 | 2485 | { |
0cadc1ed | 2486 | return (int16_t)helper_lduw_mmu(env, addr, oi, retaddr); |
eed56642 AB |
2487 | } |
2488 | ||
24e46e6c | 2489 | tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, |
0cadc1ed | 2490 | MemOpIdx oi, uintptr_t retaddr) |
eed56642 | 2491 | { |
0cadc1ed | 2492 | return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr); |
eed56642 AB |
2493 | } |
2494 | ||
fb2c53cb | 2495 | static Int128 do_ld16_mmu(CPUArchState *env, vaddr addr, |
35c653c4 RH |
2496 | MemOpIdx oi, uintptr_t ra) |
2497 | { | |
2498 | MMULookupLocals l; | |
2499 | bool crosspage; | |
2500 | uint64_t a, b; | |
2501 | Int128 ret; | |
2502 | int first; | |
2503 | ||
f86e8f3d | 2504 | cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); |
35c653c4 RH |
2505 | crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD, &l); |
2506 | if (likely(!crosspage)) { | |
2507 | /* Perform the load host endian. */ | |
2508 | if (unlikely(l.page[0].flags & TLB_MMIO)) { | |
2509 | QEMU_IOTHREAD_LOCK_GUARD(); | |
2510 | a = io_readx(env, l.page[0].full, l.mmu_idx, addr, | |
2511 | ra, MMU_DATA_LOAD, MO_64); | |
2512 | b = io_readx(env, l.page[0].full, l.mmu_idx, addr + 8, | |
2513 | ra, MMU_DATA_LOAD, MO_64); | |
2514 | ret = int128_make128(HOST_BIG_ENDIAN ? b : a, | |
2515 | HOST_BIG_ENDIAN ? a : b); | |
2516 | } else { | |
2517 | ret = load_atom_16(env, ra, l.page[0].haddr, l.memop); | |
2518 | } | |
2519 | if (l.memop & MO_BSWAP) { | |
2520 | ret = bswap128(ret); | |
2521 | } | |
2522 | return ret; | |
2523 | } | |
2524 | ||
2525 | first = l.page[0].size; | |
2526 | if (first == 8) { | |
2527 | MemOp mop8 = (l.memop & ~MO_SIZE) | MO_64; | |
2528 | ||
2529 | a = do_ld_8(env, &l.page[0], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); | |
2530 | b = do_ld_8(env, &l.page[1], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); | |
2531 | if ((mop8 & MO_BSWAP) == MO_LE) { | |
2532 | ret = int128_make128(a, b); | |
2533 | } else { | |
2534 | ret = int128_make128(b, a); | |
2535 | } | |
2536 | return ret; | |
2537 | } | |
2538 | ||
2539 | if (first < 8) { | |
2540 | a = do_ld_beN(env, &l.page[0], 0, l.mmu_idx, | |
2541 | MMU_DATA_LOAD, l.memop, ra); | |
2542 | ret = do_ld16_beN(env, &l.page[1], a, l.mmu_idx, l.memop, ra); | |
2543 | } else { | |
2544 | ret = do_ld16_beN(env, &l.page[0], 0, l.mmu_idx, l.memop, ra); | |
2545 | b = int128_getlo(ret); | |
2546 | ret = int128_lshift(ret, l.page[1].size * 8); | |
2547 | a = int128_gethi(ret); | |
2548 | b = do_ld_beN(env, &l.page[1], b, l.mmu_idx, | |
2549 | MMU_DATA_LOAD, l.memop, ra); | |
2550 | ret = int128_make128(b, a); | |
2551 | } | |
2552 | if ((l.memop & MO_BSWAP) == MO_LE) { | |
2553 | ret = bswap128(ret); | |
2554 | } | |
2555 | return ret; | |
2556 | } | |
2557 | ||
24e46e6c | 2558 | Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, |
35c653c4 RH |
2559 | uint32_t oi, uintptr_t retaddr) |
2560 | { | |
2561 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128); | |
2562 | return do_ld16_mmu(env, addr, oi, retaddr); | |
2563 | } | |
2564 | ||
e570597a | 2565 | Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, uint32_t oi) |
35c653c4 RH |
2566 | { |
2567 | return helper_ld16_mmu(env, addr, oi, GETPC()); | |
2568 | } | |
2569 | ||
d03f1408 RH |
2570 | /* |
2571 | * Load helpers for cpu_ldst.h. | |
2572 | */ | |
2573 | ||
8cfdacaa | 2574 | static void plugin_load_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi) |
d03f1408 | 2575 | { |
37aff087 | 2576 | qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); |
d03f1408 RH |
2577 | } |
2578 | ||
f83bcecb | 2579 | uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) |
d03f1408 | 2580 | { |
8cfdacaa RH |
2581 | uint8_t ret; |
2582 | ||
0cadc1ed | 2583 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_UB); |
8cfdacaa RH |
2584 | ret = do_ld1_mmu(env, addr, oi, ra, MMU_DATA_LOAD); |
2585 | plugin_load_cb(env, addr, oi); | |
2586 | return ret; | |
d03f1408 RH |
2587 | } |
2588 | ||
fbea7a40 RH |
2589 | uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, |
2590 | MemOpIdx oi, uintptr_t ra) | |
cfe04a4b | 2591 | { |
8cfdacaa RH |
2592 | uint16_t ret; |
2593 | ||
fbea7a40 | 2594 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16); |
8cfdacaa RH |
2595 | ret = do_ld2_mmu(env, addr, oi, ra, MMU_DATA_LOAD); |
2596 | plugin_load_cb(env, addr, oi); | |
2597 | return ret; | |
cfe04a4b RH |
2598 | } |
2599 | ||
fbea7a40 RH |
2600 | uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, |
2601 | MemOpIdx oi, uintptr_t ra) | |
cfe04a4b | 2602 | { |
8cfdacaa RH |
2603 | uint32_t ret; |
2604 | ||
fbea7a40 | 2605 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32); |
8cfdacaa RH |
2606 | ret = do_ld4_mmu(env, addr, oi, ra, MMU_DATA_LOAD); |
2607 | plugin_load_cb(env, addr, oi); | |
2608 | return ret; | |
cfe04a4b RH |
2609 | } |
2610 | ||
fbea7a40 RH |
2611 | uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, |
2612 | MemOpIdx oi, uintptr_t ra) | |
cfe04a4b | 2613 | { |
8cfdacaa RH |
2614 | uint64_t ret; |
2615 | ||
fbea7a40 | 2616 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64); |
8cfdacaa RH |
2617 | ret = do_ld8_mmu(env, addr, oi, ra, MMU_DATA_LOAD); |
2618 | plugin_load_cb(env, addr, oi); | |
2619 | return ret; | |
cfe04a4b RH |
2620 | } |
2621 | ||
fbea7a40 RH |
2622 | Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, |
2623 | MemOpIdx oi, uintptr_t ra) | |
cb48f365 | 2624 | { |
35c653c4 | 2625 | Int128 ret; |
cb48f365 | 2626 | |
fbea7a40 | 2627 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128); |
35c653c4 RH |
2628 | ret = do_ld16_mmu(env, addr, oi, ra); |
2629 | plugin_load_cb(env, addr, oi); | |
2630 | return ret; | |
cb48f365 RH |
2631 | } |
2632 | ||
eed56642 AB |
2633 | /* |
2634 | * Store Helpers | |
2635 | */ | |
2636 | ||
59213461 RH |
2637 | /** |
2638 | * do_st_mmio_leN: | |
2639 | * @env: cpu context | |
2640 | * @p: translation parameters | |
2641 | * @val_le: data to store | |
2642 | * @mmu_idx: virtual address context | |
2643 | * @ra: return address into tcg generated code, or 0 | |
2644 | * | |
2645 | * Store @p->size bytes at @p->addr, which is memory-mapped i/o. | |
2646 | * The bytes to store are extracted in little-endian order from @val_le; | |
2647 | * return the bytes of @val_le beyond @p->size that have not been stored. | |
2648 | */ | |
2649 | static uint64_t do_st_mmio_leN(CPUArchState *env, MMULookupPageData *p, | |
2650 | uint64_t val_le, int mmu_idx, uintptr_t ra) | |
2651 | { | |
2652 | CPUTLBEntryFull *full = p->full; | |
fb2c53cb | 2653 | vaddr addr = p->addr; |
59213461 | 2654 | int i, size = p->size; |
6b8b622e | 2655 | |
59213461 RH |
2656 | QEMU_IOTHREAD_LOCK_GUARD(); |
2657 | for (i = 0; i < size; i++, val_le >>= 8) { | |
2658 | io_writex(env, full, mmu_idx, val_le, addr + i, ra, MO_UB); | |
6b8b622e | 2659 | } |
59213461 RH |
2660 | return val_le; |
2661 | } | |
6b8b622e | 2662 | |
59213461 RH |
2663 | /* |
2664 | * Wrapper for the above. | |
2665 | */ | |
2666 | static uint64_t do_st_leN(CPUArchState *env, MMULookupPageData *p, | |
5b36f268 RH |
2667 | uint64_t val_le, int mmu_idx, |
2668 | MemOp mop, uintptr_t ra) | |
59213461 | 2669 | { |
5b36f268 RH |
2670 | MemOp atom; |
2671 | unsigned tmp, half_size; | |
2672 | ||
59213461 RH |
2673 | if (unlikely(p->flags & TLB_MMIO)) { |
2674 | return do_st_mmio_leN(env, p, val_le, mmu_idx, ra); | |
2675 | } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { | |
2676 | return val_le >> (p->size * 8); | |
5b36f268 RH |
2677 | } |
2678 | ||
2679 | /* | |
2680 | * It is a given that we cross a page and therefore there is no atomicity | |
2681 | * for the store as a whole, but subobjects may need attention. | |
2682 | */ | |
2683 | atom = mop & MO_ATOM_MASK; | |
2684 | switch (atom) { | |
2685 | case MO_ATOM_SUBALIGN: | |
2686 | return store_parts_leN(p->haddr, p->size, val_le); | |
2687 | ||
2688 | case MO_ATOM_IFALIGN_PAIR: | |
2689 | case MO_ATOM_WITHIN16_PAIR: | |
2690 | tmp = mop & MO_SIZE; | |
2691 | tmp = tmp ? tmp - 1 : 0; | |
2692 | half_size = 1 << tmp; | |
2693 | if (atom == MO_ATOM_IFALIGN_PAIR | |
2694 | ? p->size == half_size | |
2695 | : p->size >= half_size) { | |
2696 | if (!HAVE_al8_fast && p->size <= 4) { | |
2697 | return store_whole_le4(p->haddr, p->size, val_le); | |
2698 | } else if (HAVE_al8) { | |
2699 | return store_whole_le8(p->haddr, p->size, val_le); | |
2700 | } else { | |
2701 | cpu_loop_exit_atomic(env_cpu(env), ra); | |
2702 | } | |
2703 | } | |
2704 | /* fall through */ | |
2705 | ||
2706 | case MO_ATOM_IFALIGN: | |
2707 | case MO_ATOM_WITHIN16: | |
2708 | case MO_ATOM_NONE: | |
2709 | return store_bytes_leN(p->haddr, p->size, val_le); | |
2710 | ||
2711 | default: | |
2712 | g_assert_not_reached(); | |
6b8b622e RH |
2713 | } |
2714 | } | |
2715 | ||
35c653c4 RH |
2716 | /* |
2717 | * Wrapper for the above, for 8 < size < 16. | |
2718 | */ | |
2719 | static uint64_t do_st16_leN(CPUArchState *env, MMULookupPageData *p, | |
2720 | Int128 val_le, int mmu_idx, | |
2721 | MemOp mop, uintptr_t ra) | |
2722 | { | |
2723 | int size = p->size; | |
2724 | MemOp atom; | |
2725 | ||
2726 | if (unlikely(p->flags & TLB_MMIO)) { | |
2727 | p->size = 8; | |
2728 | do_st_mmio_leN(env, p, int128_getlo(val_le), mmu_idx, ra); | |
2729 | p->size = size - 8; | |
2730 | p->addr += 8; | |
2731 | return do_st_mmio_leN(env, p, int128_gethi(val_le), mmu_idx, ra); | |
2732 | } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { | |
2733 | return int128_gethi(val_le) >> ((size - 8) * 8); | |
2734 | } | |
2735 | ||
2736 | /* | |
2737 | * It is a given that we cross a page and therefore there is no atomicity | |
2738 | * for the store as a whole, but subobjects may need attention. | |
2739 | */ | |
2740 | atom = mop & MO_ATOM_MASK; | |
2741 | switch (atom) { | |
2742 | case MO_ATOM_SUBALIGN: | |
2743 | store_parts_leN(p->haddr, 8, int128_getlo(val_le)); | |
2744 | return store_parts_leN(p->haddr + 8, p->size - 8, | |
2745 | int128_gethi(val_le)); | |
2746 | ||
2747 | case MO_ATOM_WITHIN16_PAIR: | |
2748 | /* Since size > 8, this is the half that must be atomic. */ | |
8dc24ff4 | 2749 | if (!HAVE_ATOMIC128_RW) { |
35c653c4 RH |
2750 | cpu_loop_exit_atomic(env_cpu(env), ra); |
2751 | } | |
2752 | return store_whole_le16(p->haddr, p->size, val_le); | |
2753 | ||
2754 | case MO_ATOM_IFALIGN_PAIR: | |
2755 | /* | |
2756 | * Since size > 8, both halves are misaligned, | |
2757 | * and so neither is atomic. | |
2758 | */ | |
2759 | case MO_ATOM_IFALIGN: | |
2be6a486 | 2760 | case MO_ATOM_WITHIN16: |
35c653c4 RH |
2761 | case MO_ATOM_NONE: |
2762 | stq_le_p(p->haddr, int128_getlo(val_le)); | |
2763 | return store_bytes_leN(p->haddr + 8, p->size - 8, | |
2764 | int128_gethi(val_le)); | |
2765 | ||
2766 | default: | |
2767 | g_assert_not_reached(); | |
2768 | } | |
2769 | } | |
2770 | ||
59213461 RH |
2771 | static void do_st_1(CPUArchState *env, MMULookupPageData *p, uint8_t val, |
2772 | int mmu_idx, uintptr_t ra) | |
eed56642 | 2773 | { |
59213461 RH |
2774 | if (unlikely(p->flags & TLB_MMIO)) { |
2775 | io_writex(env, p->full, mmu_idx, val, p->addr, ra, MO_UB); | |
2776 | } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { | |
2777 | /* nothing */ | |
2778 | } else { | |
2779 | *(uint8_t *)p->haddr = val; | |
eed56642 | 2780 | } |
59213461 | 2781 | } |
eed56642 | 2782 | |
59213461 RH |
2783 | static void do_st_2(CPUArchState *env, MMULookupPageData *p, uint16_t val, |
2784 | int mmu_idx, MemOp memop, uintptr_t ra) | |
2785 | { | |
2786 | if (unlikely(p->flags & TLB_MMIO)) { | |
2787 | io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop); | |
2788 | } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { | |
2789 | /* nothing */ | |
2790 | } else { | |
2791 | /* Swap to host endian if necessary, then store. */ | |
2792 | if (memop & MO_BSWAP) { | |
2793 | val = bswap16(val); | |
eed56642 | 2794 | } |
5b36f268 | 2795 | store_atom_2(env, ra, p->haddr, memop, val); |
eed56642 | 2796 | } |
59213461 | 2797 | } |
eed56642 | 2798 | |
59213461 RH |
2799 | static void do_st_4(CPUArchState *env, MMULookupPageData *p, uint32_t val, |
2800 | int mmu_idx, MemOp memop, uintptr_t ra) | |
2801 | { | |
2802 | if (unlikely(p->flags & TLB_MMIO)) { | |
2803 | io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop); | |
2804 | } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { | |
2805 | /* nothing */ | |
2806 | } else { | |
2807 | /* Swap to host endian if necessary, then store. */ | |
2808 | if (memop & MO_BSWAP) { | |
2809 | val = bswap32(val); | |
5b87b3e6 | 2810 | } |
5b36f268 | 2811 | store_atom_4(env, ra, p->haddr, memop, val); |
eed56642 | 2812 | } |
eed56642 AB |
2813 | } |
2814 | ||
59213461 RH |
2815 | static void do_st_8(CPUArchState *env, MMULookupPageData *p, uint64_t val, |
2816 | int mmu_idx, MemOp memop, uintptr_t ra) | |
eed56642 | 2817 | { |
59213461 RH |
2818 | if (unlikely(p->flags & TLB_MMIO)) { |
2819 | io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop); | |
2820 | } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { | |
2821 | /* nothing */ | |
2822 | } else { | |
2823 | /* Swap to host endian if necessary, then store. */ | |
2824 | if (memop & MO_BSWAP) { | |
2825 | val = bswap64(val); | |
2826 | } | |
5b36f268 | 2827 | store_atom_8(env, ra, p->haddr, memop, val); |
59213461 | 2828 | } |
eed56642 AB |
2829 | } |
2830 | ||
24e46e6c | 2831 | void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, |
0cadc1ed | 2832 | MemOpIdx oi, uintptr_t ra) |
f83bcecb | 2833 | { |
59213461 RH |
2834 | MMULookupLocals l; |
2835 | bool crosspage; | |
2836 | ||
0cadc1ed | 2837 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_8); |
f86e8f3d | 2838 | cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); |
59213461 RH |
2839 | crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); |
2840 | tcg_debug_assert(!crosspage); | |
2841 | ||
2842 | do_st_1(env, &l.page[0], val, l.mmu_idx, ra); | |
f83bcecb RH |
2843 | } |
2844 | ||
fb2c53cb | 2845 | static void do_st2_mmu(CPUArchState *env, vaddr addr, uint16_t val, |
59213461 | 2846 | MemOpIdx oi, uintptr_t ra) |
f83bcecb | 2847 | { |
59213461 RH |
2848 | MMULookupLocals l; |
2849 | bool crosspage; | |
2850 | uint8_t a, b; | |
2851 | ||
f86e8f3d | 2852 | cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); |
59213461 RH |
2853 | crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); |
2854 | if (likely(!crosspage)) { | |
2855 | do_st_2(env, &l.page[0], val, l.mmu_idx, l.memop, ra); | |
2856 | return; | |
2857 | } | |
2858 | ||
2859 | if ((l.memop & MO_BSWAP) == MO_LE) { | |
2860 | a = val, b = val >> 8; | |
2861 | } else { | |
2862 | b = val, a = val >> 8; | |
2863 | } | |
2864 | do_st_1(env, &l.page[0], a, l.mmu_idx, ra); | |
2865 | do_st_1(env, &l.page[1], b, l.mmu_idx, ra); | |
f83bcecb RH |
2866 | } |
2867 | ||
24e46e6c | 2868 | void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, |
0cadc1ed | 2869 | MemOpIdx oi, uintptr_t retaddr) |
eed56642 | 2870 | { |
0cadc1ed | 2871 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16); |
59213461 | 2872 | do_st2_mmu(env, addr, val, oi, retaddr); |
f83bcecb RH |
2873 | } |
2874 | ||
fb2c53cb | 2875 | static void do_st4_mmu(CPUArchState *env, vaddr addr, uint32_t val, |
59213461 | 2876 | MemOpIdx oi, uintptr_t ra) |
f83bcecb | 2877 | { |
59213461 RH |
2878 | MMULookupLocals l; |
2879 | bool crosspage; | |
2880 | ||
f86e8f3d | 2881 | cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); |
59213461 RH |
2882 | crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); |
2883 | if (likely(!crosspage)) { | |
2884 | do_st_4(env, &l.page[0], val, l.mmu_idx, l.memop, ra); | |
2885 | return; | |
2886 | } | |
2887 | ||
2888 | /* Swap to little endian for simplicity, then store by bytes. */ | |
2889 | if ((l.memop & MO_BSWAP) != MO_LE) { | |
2890 | val = bswap32(val); | |
2891 | } | |
5b36f268 RH |
2892 | val = do_st_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); |
2893 | (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); | |
eed56642 AB |
2894 | } |
2895 | ||
24e46e6c | 2896 | void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, |
0cadc1ed | 2897 | MemOpIdx oi, uintptr_t retaddr) |
f83bcecb | 2898 | { |
0cadc1ed | 2899 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32); |
59213461 | 2900 | do_st4_mmu(env, addr, val, oi, retaddr); |
eed56642 AB |
2901 | } |
2902 | ||
fb2c53cb | 2903 | static void do_st8_mmu(CPUArchState *env, vaddr addr, uint64_t val, |
59213461 | 2904 | MemOpIdx oi, uintptr_t ra) |
eed56642 | 2905 | { |
59213461 RH |
2906 | MMULookupLocals l; |
2907 | bool crosspage; | |
2908 | ||
f86e8f3d | 2909 | cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); |
59213461 RH |
2910 | crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); |
2911 | if (likely(!crosspage)) { | |
2912 | do_st_8(env, &l.page[0], val, l.mmu_idx, l.memop, ra); | |
2913 | return; | |
2914 | } | |
2915 | ||
2916 | /* Swap to little endian for simplicity, then store by bytes. */ | |
2917 | if ((l.memop & MO_BSWAP) != MO_LE) { | |
2918 | val = bswap64(val); | |
2919 | } | |
5b36f268 RH |
2920 | val = do_st_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); |
2921 | (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); | |
eed56642 AB |
2922 | } |
2923 | ||
24e46e6c | 2924 | void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, |
0cadc1ed | 2925 | MemOpIdx oi, uintptr_t retaddr) |
eed56642 | 2926 | { |
0cadc1ed | 2927 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64); |
59213461 | 2928 | do_st8_mmu(env, addr, val, oi, retaddr); |
eed56642 | 2929 | } |
0f590e74 | 2930 | |
fb2c53cb | 2931 | static void do_st16_mmu(CPUArchState *env, vaddr addr, Int128 val, |
35c653c4 RH |
2932 | MemOpIdx oi, uintptr_t ra) |
2933 | { | |
2934 | MMULookupLocals l; | |
2935 | bool crosspage; | |
2936 | uint64_t a, b; | |
2937 | int first; | |
2938 | ||
f86e8f3d | 2939 | cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); |
35c653c4 RH |
2940 | crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); |
2941 | if (likely(!crosspage)) { | |
2942 | /* Swap to host endian if necessary, then store. */ | |
2943 | if (l.memop & MO_BSWAP) { | |
2944 | val = bswap128(val); | |
2945 | } | |
2946 | if (unlikely(l.page[0].flags & TLB_MMIO)) { | |
2947 | QEMU_IOTHREAD_LOCK_GUARD(); | |
2948 | if (HOST_BIG_ENDIAN) { | |
2949 | b = int128_getlo(val), a = int128_gethi(val); | |
2950 | } else { | |
2951 | a = int128_getlo(val), b = int128_gethi(val); | |
2952 | } | |
2953 | io_writex(env, l.page[0].full, l.mmu_idx, a, addr, ra, MO_64); | |
2954 | io_writex(env, l.page[0].full, l.mmu_idx, b, addr + 8, ra, MO_64); | |
2955 | } else if (unlikely(l.page[0].flags & TLB_DISCARD_WRITE)) { | |
2956 | /* nothing */ | |
2957 | } else { | |
2958 | store_atom_16(env, ra, l.page[0].haddr, l.memop, val); | |
2959 | } | |
2960 | return; | |
2961 | } | |
2962 | ||
2963 | first = l.page[0].size; | |
2964 | if (first == 8) { | |
2965 | MemOp mop8 = (l.memop & ~(MO_SIZE | MO_BSWAP)) | MO_64; | |
2966 | ||
2967 | if (l.memop & MO_BSWAP) { | |
2968 | val = bswap128(val); | |
2969 | } | |
2970 | if (HOST_BIG_ENDIAN) { | |
2971 | b = int128_getlo(val), a = int128_gethi(val); | |
2972 | } else { | |
2973 | a = int128_getlo(val), b = int128_gethi(val); | |
2974 | } | |
2975 | do_st_8(env, &l.page[0], a, l.mmu_idx, mop8, ra); | |
2976 | do_st_8(env, &l.page[1], b, l.mmu_idx, mop8, ra); | |
2977 | return; | |
2978 | } | |
2979 | ||
2980 | if ((l.memop & MO_BSWAP) != MO_LE) { | |
2981 | val = bswap128(val); | |
2982 | } | |
2983 | if (first < 8) { | |
2984 | do_st_leN(env, &l.page[0], int128_getlo(val), l.mmu_idx, l.memop, ra); | |
2985 | val = int128_urshift(val, first * 8); | |
2986 | do_st16_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); | |
2987 | } else { | |
2988 | b = do_st16_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); | |
2989 | do_st_leN(env, &l.page[1], b, l.mmu_idx, l.memop, ra); | |
2990 | } | |
2991 | } | |
2992 | ||
24e46e6c | 2993 | void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, |
35c653c4 RH |
2994 | MemOpIdx oi, uintptr_t retaddr) |
2995 | { | |
2996 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128); | |
2997 | do_st16_mmu(env, addr, val, oi, retaddr); | |
2998 | } | |
2999 | ||
e570597a | 3000 | void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx oi) |
35c653c4 RH |
3001 | { |
3002 | helper_st16_mmu(env, addr, val, oi, GETPC()); | |
3003 | } | |
3004 | ||
d03f1408 RH |
3005 | /* |
3006 | * Store Helpers for cpu_ldst.h | |
3007 | */ | |
3008 | ||
59213461 | 3009 | static void plugin_store_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi) |
f83bcecb | 3010 | { |
37aff087 | 3011 | qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); |
d03f1408 RH |
3012 | } |
3013 | ||
f83bcecb RH |
3014 | void cpu_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, |
3015 | MemOpIdx oi, uintptr_t retaddr) | |
d03f1408 | 3016 | { |
0cadc1ed | 3017 | helper_stb_mmu(env, addr, val, oi, retaddr); |
59213461 | 3018 | plugin_store_cb(env, addr, oi); |
d03f1408 RH |
3019 | } |
3020 | ||
fbea7a40 RH |
3021 | void cpu_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3022 | MemOpIdx oi, uintptr_t retaddr) | |
d03f1408 | 3023 | { |
fbea7a40 | 3024 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16); |
0cadc1ed | 3025 | do_st2_mmu(env, addr, val, oi, retaddr); |
59213461 | 3026 | plugin_store_cb(env, addr, oi); |
b9e60257 RH |
3027 | } |
3028 | ||
fbea7a40 | 3029 | void cpu_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
f83bcecb | 3030 | MemOpIdx oi, uintptr_t retaddr) |
b9e60257 | 3031 | { |
fbea7a40 | 3032 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32); |
0cadc1ed | 3033 | do_st4_mmu(env, addr, val, oi, retaddr); |
59213461 | 3034 | plugin_store_cb(env, addr, oi); |
b9e60257 RH |
3035 | } |
3036 | ||
fbea7a40 RH |
3037 | void cpu_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3038 | MemOpIdx oi, uintptr_t retaddr) | |
b9e60257 | 3039 | { |
fbea7a40 | 3040 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64); |
0cadc1ed | 3041 | do_st8_mmu(env, addr, val, oi, retaddr); |
59213461 | 3042 | plugin_store_cb(env, addr, oi); |
d03f1408 RH |
3043 | } |
3044 | ||
fbea7a40 RH |
3045 | void cpu_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, |
3046 | MemOpIdx oi, uintptr_t retaddr) | |
cb48f365 | 3047 | { |
fbea7a40 | 3048 | tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128); |
35c653c4 RH |
3049 | do_st16_mmu(env, addr, val, oi, retaddr); |
3050 | plugin_store_cb(env, addr, oi); | |
cb48f365 RH |
3051 | } |
3052 | ||
f83bcecb | 3053 | #include "ldst_common.c.inc" |
cfe04a4b | 3054 | |
be9568b4 RH |
3055 | /* |
3056 | * First set of functions passes in OI and RETADDR. | |
3057 | * This makes them callable from other helpers. | |
3058 | */ | |
c482cb11 | 3059 | |
c482cb11 | 3060 | #define ATOMIC_NAME(X) \ |
be9568b4 | 3061 | glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) |
a754f7f3 | 3062 | |
707526ad | 3063 | #define ATOMIC_MMU_CLEANUP |
c482cb11 | 3064 | |
139c1837 | 3065 | #include "atomic_common.c.inc" |
c482cb11 RH |
3066 | |
3067 | #define DATA_SIZE 1 | |
3068 | #include "atomic_template.h" | |
3069 | ||
3070 | #define DATA_SIZE 2 | |
3071 | #include "atomic_template.h" | |
3072 | ||
3073 | #define DATA_SIZE 4 | |
3074 | #include "atomic_template.h" | |
3075 | ||
df79b996 | 3076 | #ifdef CONFIG_ATOMIC64 |
c482cb11 RH |
3077 | #define DATA_SIZE 8 |
3078 | #include "atomic_template.h" | |
df79b996 | 3079 | #endif |
c482cb11 | 3080 | |
4deb39eb | 3081 | #if defined(CONFIG_ATOMIC128) || defined(CONFIG_CMPXCHG128) |
7ebee43e RH |
3082 | #define DATA_SIZE 16 |
3083 | #include "atomic_template.h" | |
3084 | #endif | |
3085 | ||
c482cb11 RH |
3086 | /* Code access functions. */ |
3087 | ||
fc4120a3 | 3088 | uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) |
eed56642 | 3089 | { |
9002ffcb | 3090 | MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true)); |
8cfdacaa | 3091 | return do_ld1_mmu(env, addr, oi, 0, MMU_INST_FETCH); |
eed56642 | 3092 | } |
0cac1b66 | 3093 | |
fc4120a3 | 3094 | uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) |
eed56642 | 3095 | { |
9002ffcb | 3096 | MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); |
8cfdacaa | 3097 | return do_ld2_mmu(env, addr, oi, 0, MMU_INST_FETCH); |
eed56642 | 3098 | } |
0cac1b66 | 3099 | |
fc4120a3 | 3100 | uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) |
eed56642 | 3101 | { |
9002ffcb | 3102 | MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); |
8cfdacaa | 3103 | return do_ld4_mmu(env, addr, oi, 0, MMU_INST_FETCH); |
eed56642 AB |
3104 | } |
3105 | ||
fc4120a3 | 3106 | uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) |
eed56642 | 3107 | { |
fc313c64 | 3108 | MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); |
8cfdacaa | 3109 | return do_ld8_mmu(env, addr, oi, 0, MMU_INST_FETCH); |
eed56642 | 3110 | } |
28990626 RH |
3111 | |
3112 | uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, | |
3113 | MemOpIdx oi, uintptr_t retaddr) | |
3114 | { | |
8cfdacaa | 3115 | return do_ld1_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); |
28990626 RH |
3116 | } |
3117 | ||
3118 | uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, | |
3119 | MemOpIdx oi, uintptr_t retaddr) | |
3120 | { | |
8cfdacaa | 3121 | return do_ld2_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); |
28990626 RH |
3122 | } |
3123 | ||
3124 | uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, | |
3125 | MemOpIdx oi, uintptr_t retaddr) | |
3126 | { | |
8cfdacaa | 3127 | return do_ld4_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); |
28990626 RH |
3128 | } |
3129 | ||
3130 | uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, | |
3131 | MemOpIdx oi, uintptr_t retaddr) | |
3132 | { | |
8cfdacaa | 3133 | return do_ld8_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); |
28990626 | 3134 | } |