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42a623c7 BS |
1 | /* |
2 | * User emulator execution | |
3 | * | |
4 | * Copyright (c) 2003-2005 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
fb0343d5 | 9 | * version 2.1 of the License, or (at your option) any later version. |
42a623c7 BS |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
d38ea87a | 19 | #include "qemu/osdep.h" |
3e457172 | 20 | #include "cpu.h" |
76cad711 | 21 | #include "disas/disas.h" |
63c91552 | 22 | #include "exec/exec-all.h" |
42a623c7 | 23 | #include "tcg.h" |
023b0ae3 | 24 | #include "qemu/bitops.h" |
f08b6170 | 25 | #include "exec/cpu_ldst.h" |
1652b974 | 26 | #include "translate-all.h" |
a411d296 | 27 | #include "exec/helper-proto.h" |
e6cd4bb5 | 28 | #include "qemu/atomic128.h" |
42a623c7 BS |
29 | |
30 | #undef EAX | |
31 | #undef ECX | |
32 | #undef EDX | |
33 | #undef EBX | |
34 | #undef ESP | |
35 | #undef EBP | |
36 | #undef ESI | |
37 | #undef EDI | |
38 | #undef EIP | |
42a623c7 BS |
39 | #ifdef __linux__ |
40 | #include <sys/ucontext.h> | |
41 | #endif | |
42 | ||
ec603b55 RH |
43 | __thread uintptr_t helper_retaddr; |
44 | ||
42a623c7 BS |
45 | //#define DEBUG_SIGNAL |
46 | ||
42a623c7 BS |
47 | /* exit the current TB from a signal handler. The host registers are |
48 | restored in a state compatible with the CPU emulator | |
49 | */ | |
a5852dc5 | 50 | static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set) |
42a623c7 | 51 | { |
f213e72f | 52 | /* XXX: use siglongjmp ? */ |
a5852dc5 | 53 | sigprocmask(SIG_SETMASK, old_set, NULL); |
6886b980 | 54 | cpu_loop_exit_noexc(cpu); |
42a623c7 BS |
55 | } |
56 | ||
57 | /* 'pc' is the host PC at which the exception was raised. 'address' is | |
58 | the effective address of the memory exception. 'is_write' is 1 if a | |
59 | write caused the exception and otherwise 0'. 'old_set' is the | |
60 | signal set which should be restored */ | |
a78b1299 | 61 | static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, |
a5852dc5 | 62 | int is_write, sigset_t *old_set) |
42a623c7 | 63 | { |
02bed6bd | 64 | CPUState *cpu = current_cpu; |
7510454e | 65 | CPUClass *cc; |
a78b1299 | 66 | unsigned long address = (unsigned long)info->si_addr; |
52ba13f0 | 67 | MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; |
42a623c7 | 68 | |
52ba13f0 RH |
69 | switch (helper_retaddr) { |
70 | default: | |
71 | /* | |
72 | * Fault during host memory operation within a helper function. | |
73 | * The helper's host return address, saved here, gives us a | |
74 | * pointer into the generated code that will unwind to the | |
75 | * correct guest pc. | |
76 | */ | |
ec603b55 | 77 | pc = helper_retaddr; |
52ba13f0 RH |
78 | break; |
79 | ||
80 | case 0: | |
81 | /* | |
82 | * Fault during host memory operation within generated code. | |
83 | * (Or, a unrelated bug within qemu, but we can't tell from here). | |
84 | * | |
85 | * We take the host pc from the signal frame. However, we cannot | |
86 | * use that value directly. Within cpu_restore_state_from_tb, we | |
87 | * assume PC comes from GETPC(), as used by the helper functions, | |
88 | * so we adjust the address by -GETPC_ADJ to form an address that | |
89 | * is within the call insn, so that the address does not accidentially | |
90 | * match the beginning of the next guest insn. However, when the | |
91 | * pc comes from the signal frame it points to the actual faulting | |
92 | * host memory insn and not the return from a call insn. | |
93 | * | |
94 | * Therefore, adjust to compensate for what will be done later | |
95 | * by cpu_restore_state_from_tb. | |
96 | */ | |
ec603b55 | 97 | pc += GETPC_ADJ; |
52ba13f0 RH |
98 | break; |
99 | ||
100 | case 1: | |
101 | /* | |
102 | * Fault during host read for translation, or loosely, "execution". | |
103 | * | |
104 | * The guest pc is already pointing to the start of the TB for which | |
105 | * code is being generated. If the guest translator manages the | |
106 | * page crossings correctly, this is exactly the correct address | |
107 | * (and if the translator doesn't handle page boundaries correctly | |
108 | * there's little we can do about that here). Therefore, do not | |
109 | * trigger the unwinder. | |
110 | * | |
111 | * Like tb_gen_code, release the memory lock before cpu_loop_exit. | |
112 | */ | |
113 | pc = 0; | |
114 | access_type = MMU_INST_FETCH; | |
115 | mmap_unlock(); | |
116 | break; | |
ec603b55 RH |
117 | } |
118 | ||
02bed6bd AB |
119 | /* For synchronous signals we expect to be coming from the vCPU |
120 | * thread (so current_cpu should be valid) and either from running | |
121 | * code or during translation which can fault as we cross pages. | |
122 | * | |
123 | * If neither is true then something has gone wrong and we should | |
124 | * abort rather than try and restart the vCPU execution. | |
125 | */ | |
126 | if (!cpu || !cpu->running) { | |
127 | printf("qemu:%s received signal outside vCPU context @ pc=0x%" | |
128 | PRIxPTR "\n", __func__, pc); | |
129 | abort(); | |
130 | } | |
131 | ||
42a623c7 | 132 | #if defined(DEBUG_SIGNAL) |
71baf787 PM |
133 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
134 | pc, address, is_write, *(unsigned long *)old_set); | |
42a623c7 BS |
135 | #endif |
136 | /* XXX: locking issue */ | |
9c4bbee9 PM |
137 | /* Note that it is important that we don't call page_unprotect() unless |
138 | * this is really a "write to nonwriteable page" fault, because | |
139 | * page_unprotect() assumes that if it is called for an access to | |
140 | * a page that's writeable this means we had two threads racing and | |
141 | * another thread got there first and already made the page writeable; | |
142 | * so we will retry the access. If we were to call page_unprotect() | |
143 | * for some other kind of fault that should really be passed to the | |
144 | * guest, we'd end up in an infinite loop of retrying the faulting | |
145 | * access. | |
146 | */ | |
147 | if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && | |
148 | h2g_valid(address)) { | |
f213e72f PM |
149 | switch (page_unprotect(h2g(address), pc)) { |
150 | case 0: | |
151 | /* Fault not caused by a page marked unwritable to protect | |
ec603b55 | 152 | * cached translations, must be the guest binary's problem. |
f213e72f PM |
153 | */ |
154 | break; | |
155 | case 1: | |
156 | /* Fault caused by protection of cached translation; TBs | |
ec603b55 RH |
157 | * invalidated, so resume execution. Retain helper_retaddr |
158 | * for a possible second fault. | |
f213e72f PM |
159 | */ |
160 | return 1; | |
161 | case 2: | |
162 | /* Fault caused by protection of cached translation, and the | |
163 | * currently executing TB was modified and must be exited | |
ec603b55 | 164 | * immediately. Clear helper_retaddr for next execution. |
f213e72f | 165 | */ |
08b97f7f | 166 | clear_helper_retaddr(); |
02bed6bd | 167 | cpu_exit_tb_from_sighandler(cpu, old_set); |
ec603b55 RH |
168 | /* NORETURN */ |
169 | ||
f213e72f PM |
170 | default: |
171 | g_assert_not_reached(); | |
172 | } | |
42a623c7 BS |
173 | } |
174 | ||
732f9e89 AG |
175 | /* Convert forcefully to guest address space, invalid addresses |
176 | are still valid segv ones */ | |
177 | address = h2g_nocheck(address); | |
178 | ||
da6bbf85 RH |
179 | /* |
180 | * There is no way the target can handle this other than raising | |
181 | * an exception. Undo signal and retaddr state prior to longjmp. | |
ec603b55 | 182 | */ |
da6bbf85 | 183 | sigprocmask(SIG_SETMASK, old_set, NULL); |
08b97f7f | 184 | clear_helper_retaddr(); |
ec603b55 | 185 | |
da6bbf85 | 186 | cc = CPU_GET_CLASS(cpu); |
69963f57 RH |
187 | cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); |
188 | g_assert_not_reached(); | |
42a623c7 BS |
189 | } |
190 | ||
59e96ac6 DH |
191 | void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, |
192 | uintptr_t retaddr) | |
193 | { | |
ca86cf32 DH |
194 | g_assert(-(addr | TARGET_PAGE_MASK) >= size); |
195 | ||
59e96ac6 DH |
196 | if (!guest_addr_valid(addr) || |
197 | page_check_range(addr, size, PAGE_WRITE) < 0) { | |
198 | CPUState *cpu = env_cpu(env); | |
199 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
200 | ||
201 | cc->tlb_fill(cpu, addr, size, MMU_DATA_STORE, MMU_USER_IDX, false, | |
202 | retaddr); | |
203 | g_assert_not_reached(); | |
204 | } | |
205 | } | |
206 | ||
42a623c7 BS |
207 | #if defined(__i386__) |
208 | ||
c5679026 | 209 | #if defined(__NetBSD__) |
42a623c7 BS |
210 | #include <ucontext.h> |
211 | ||
212 | #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) | |
213 | #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) | |
214 | #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) | |
215 | #define MASK_sig(context) ((context)->uc_sigmask) | |
216 | #elif defined(__FreeBSD__) || defined(__DragonFly__) | |
217 | #include <ucontext.h> | |
218 | ||
219 | #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) | |
220 | #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) | |
221 | #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) | |
222 | #define MASK_sig(context) ((context)->uc_sigmask) | |
223 | #elif defined(__OpenBSD__) | |
224 | #define EIP_sig(context) ((context)->sc_eip) | |
225 | #define TRAP_sig(context) ((context)->sc_trapno) | |
226 | #define ERROR_sig(context) ((context)->sc_err) | |
227 | #define MASK_sig(context) ((context)->sc_mask) | |
228 | #else | |
229 | #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) | |
230 | #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) | |
231 | #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) | |
232 | #define MASK_sig(context) ((context)->uc_sigmask) | |
233 | #endif | |
234 | ||
235 | int cpu_signal_handler(int host_signum, void *pinfo, | |
236 | void *puc) | |
237 | { | |
238 | siginfo_t *info = pinfo; | |
239 | #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) | |
240 | ucontext_t *uc = puc; | |
241 | #elif defined(__OpenBSD__) | |
242 | struct sigcontext *uc = puc; | |
243 | #else | |
04b33e21 | 244 | ucontext_t *uc = puc; |
42a623c7 BS |
245 | #endif |
246 | unsigned long pc; | |
247 | int trapno; | |
248 | ||
249 | #ifndef REG_EIP | |
250 | /* for glibc 2.1 */ | |
251 | #define REG_EIP EIP | |
252 | #define REG_ERR ERR | |
253 | #define REG_TRAPNO TRAPNO | |
254 | #endif | |
255 | pc = EIP_sig(uc); | |
256 | trapno = TRAP_sig(uc); | |
a78b1299 PM |
257 | return handle_cpu_signal(pc, info, |
258 | trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, | |
a5852dc5 | 259 | &MASK_sig(uc)); |
42a623c7 BS |
260 | } |
261 | ||
262 | #elif defined(__x86_64__) | |
263 | ||
264 | #ifdef __NetBSD__ | |
265 | #define PC_sig(context) _UC_MACHINE_PC(context) | |
266 | #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) | |
267 | #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) | |
268 | #define MASK_sig(context) ((context)->uc_sigmask) | |
269 | #elif defined(__OpenBSD__) | |
270 | #define PC_sig(context) ((context)->sc_rip) | |
271 | #define TRAP_sig(context) ((context)->sc_trapno) | |
272 | #define ERROR_sig(context) ((context)->sc_err) | |
273 | #define MASK_sig(context) ((context)->sc_mask) | |
274 | #elif defined(__FreeBSD__) || defined(__DragonFly__) | |
275 | #include <ucontext.h> | |
276 | ||
277 | #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) | |
278 | #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) | |
279 | #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) | |
280 | #define MASK_sig(context) ((context)->uc_sigmask) | |
281 | #else | |
282 | #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) | |
283 | #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) | |
284 | #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) | |
285 | #define MASK_sig(context) ((context)->uc_sigmask) | |
286 | #endif | |
287 | ||
288 | int cpu_signal_handler(int host_signum, void *pinfo, | |
289 | void *puc) | |
290 | { | |
291 | siginfo_t *info = pinfo; | |
292 | unsigned long pc; | |
293 | #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) | |
294 | ucontext_t *uc = puc; | |
295 | #elif defined(__OpenBSD__) | |
296 | struct sigcontext *uc = puc; | |
297 | #else | |
04b33e21 | 298 | ucontext_t *uc = puc; |
42a623c7 BS |
299 | #endif |
300 | ||
301 | pc = PC_sig(uc); | |
a78b1299 PM |
302 | return handle_cpu_signal(pc, info, |
303 | TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, | |
a5852dc5 | 304 | &MASK_sig(uc)); |
42a623c7 BS |
305 | } |
306 | ||
307 | #elif defined(_ARCH_PPC) | |
308 | ||
309 | /*********************************************************************** | |
310 | * signal context platform-specific definitions | |
311 | * From Wine | |
312 | */ | |
313 | #ifdef linux | |
314 | /* All Registers access - only for local access */ | |
315 | #define REG_sig(reg_name, context) \ | |
316 | ((context)->uc_mcontext.regs->reg_name) | |
317 | /* Gpr Registers access */ | |
318 | #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) | |
319 | /* Program counter */ | |
320 | #define IAR_sig(context) REG_sig(nip, context) | |
321 | /* Machine State Register (Supervisor) */ | |
322 | #define MSR_sig(context) REG_sig(msr, context) | |
323 | /* Count register */ | |
324 | #define CTR_sig(context) REG_sig(ctr, context) | |
325 | /* User's integer exception register */ | |
326 | #define XER_sig(context) REG_sig(xer, context) | |
327 | /* Link register */ | |
328 | #define LR_sig(context) REG_sig(link, context) | |
329 | /* Condition register */ | |
330 | #define CR_sig(context) REG_sig(ccr, context) | |
331 | ||
332 | /* Float Registers access */ | |
333 | #define FLOAT_sig(reg_num, context) \ | |
334 | (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) | |
335 | #define FPSCR_sig(context) \ | |
336 | (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) | |
337 | /* Exception Registers access */ | |
338 | #define DAR_sig(context) REG_sig(dar, context) | |
339 | #define DSISR_sig(context) REG_sig(dsisr, context) | |
340 | #define TRAP_sig(context) REG_sig(trap, context) | |
341 | #endif /* linux */ | |
342 | ||
343 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) | |
344 | #include <ucontext.h> | |
345 | #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) | |
346 | #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) | |
347 | #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) | |
348 | #define XER_sig(context) ((context)->uc_mcontext.mc_xer) | |
349 | #define LR_sig(context) ((context)->uc_mcontext.mc_lr) | |
350 | #define CR_sig(context) ((context)->uc_mcontext.mc_cr) | |
351 | /* Exception Registers access */ | |
352 | #define DAR_sig(context) ((context)->uc_mcontext.mc_dar) | |
353 | #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) | |
354 | #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) | |
355 | #endif /* __FreeBSD__|| __FreeBSD_kernel__ */ | |
356 | ||
42a623c7 BS |
357 | int cpu_signal_handler(int host_signum, void *pinfo, |
358 | void *puc) | |
359 | { | |
360 | siginfo_t *info = pinfo; | |
361 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) | |
362 | ucontext_t *uc = puc; | |
363 | #else | |
04b33e21 | 364 | ucontext_t *uc = puc; |
42a623c7 BS |
365 | #endif |
366 | unsigned long pc; | |
367 | int is_write; | |
368 | ||
369 | pc = IAR_sig(uc); | |
370 | is_write = 0; | |
371 | #if 0 | |
372 | /* ppc 4xx case */ | |
373 | if (DSISR_sig(uc) & 0x00800000) { | |
374 | is_write = 1; | |
375 | } | |
376 | #else | |
377 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { | |
378 | is_write = 1; | |
379 | } | |
380 | #endif | |
a78b1299 | 381 | return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); |
42a623c7 BS |
382 | } |
383 | ||
384 | #elif defined(__alpha__) | |
385 | ||
386 | int cpu_signal_handler(int host_signum, void *pinfo, | |
387 | void *puc) | |
388 | { | |
389 | siginfo_t *info = pinfo; | |
04b33e21 | 390 | ucontext_t *uc = puc; |
42a623c7 BS |
391 | uint32_t *pc = uc->uc_mcontext.sc_pc; |
392 | uint32_t insn = *pc; | |
393 | int is_write = 0; | |
394 | ||
395 | /* XXX: need kernel patch to get write flag faster */ | |
396 | switch (insn >> 26) { | |
397 | case 0x0d: /* stw */ | |
398 | case 0x0e: /* stb */ | |
399 | case 0x0f: /* stq_u */ | |
400 | case 0x24: /* stf */ | |
401 | case 0x25: /* stg */ | |
402 | case 0x26: /* sts */ | |
403 | case 0x27: /* stt */ | |
404 | case 0x2c: /* stl */ | |
405 | case 0x2d: /* stq */ | |
406 | case 0x2e: /* stl_c */ | |
407 | case 0x2f: /* stq_c */ | |
408 | is_write = 1; | |
409 | } | |
410 | ||
a78b1299 | 411 | return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); |
42a623c7 BS |
412 | } |
413 | #elif defined(__sparc__) | |
414 | ||
415 | int cpu_signal_handler(int host_signum, void *pinfo, | |
416 | void *puc) | |
417 | { | |
418 | siginfo_t *info = pinfo; | |
419 | int is_write; | |
420 | uint32_t insn; | |
421 | #if !defined(__arch64__) || defined(CONFIG_SOLARIS) | |
422 | uint32_t *regs = (uint32_t *)(info + 1); | |
423 | void *sigmask = (regs + 20); | |
424 | /* XXX: is there a standard glibc define ? */ | |
425 | unsigned long pc = regs[1]; | |
426 | #else | |
427 | #ifdef __linux__ | |
428 | struct sigcontext *sc = puc; | |
429 | unsigned long pc = sc->sigc_regs.tpc; | |
430 | void *sigmask = (void *)sc->sigc_mask; | |
431 | #elif defined(__OpenBSD__) | |
432 | struct sigcontext *uc = puc; | |
433 | unsigned long pc = uc->sc_pc; | |
434 | void *sigmask = (void *)(long)uc->sc_mask; | |
7ccfb495 TN |
435 | #elif defined(__NetBSD__) |
436 | ucontext_t *uc = puc; | |
437 | unsigned long pc = _UC_MACHINE_PC(uc); | |
438 | void *sigmask = (void *)&uc->uc_sigmask; | |
42a623c7 BS |
439 | #endif |
440 | #endif | |
441 | ||
442 | /* XXX: need kernel patch to get write flag faster */ | |
443 | is_write = 0; | |
444 | insn = *(uint32_t *)pc; | |
445 | if ((insn >> 30) == 3) { | |
446 | switch ((insn >> 19) & 0x3f) { | |
447 | case 0x05: /* stb */ | |
448 | case 0x15: /* stba */ | |
449 | case 0x06: /* sth */ | |
450 | case 0x16: /* stha */ | |
451 | case 0x04: /* st */ | |
452 | case 0x14: /* sta */ | |
453 | case 0x07: /* std */ | |
454 | case 0x17: /* stda */ | |
455 | case 0x0e: /* stx */ | |
456 | case 0x1e: /* stxa */ | |
457 | case 0x24: /* stf */ | |
458 | case 0x34: /* stfa */ | |
459 | case 0x27: /* stdf */ | |
460 | case 0x37: /* stdfa */ | |
461 | case 0x26: /* stqf */ | |
462 | case 0x36: /* stqfa */ | |
463 | case 0x25: /* stfsr */ | |
464 | case 0x3c: /* casa */ | |
465 | case 0x3e: /* casxa */ | |
466 | is_write = 1; | |
467 | break; | |
468 | } | |
469 | } | |
a78b1299 | 470 | return handle_cpu_signal(pc, info, is_write, sigmask); |
42a623c7 BS |
471 | } |
472 | ||
473 | #elif defined(__arm__) | |
474 | ||
7ccfb495 TN |
475 | #if defined(__NetBSD__) |
476 | #include <ucontext.h> | |
477 | #endif | |
478 | ||
42a623c7 BS |
479 | int cpu_signal_handler(int host_signum, void *pinfo, |
480 | void *puc) | |
481 | { | |
482 | siginfo_t *info = pinfo; | |
7ccfb495 TN |
483 | #if defined(__NetBSD__) |
484 | ucontext_t *uc = puc; | |
485 | #else | |
04b33e21 | 486 | ucontext_t *uc = puc; |
7ccfb495 | 487 | #endif |
42a623c7 BS |
488 | unsigned long pc; |
489 | int is_write; | |
490 | ||
7ccfb495 TN |
491 | #if defined(__NetBSD__) |
492 | pc = uc->uc_mcontext.__gregs[_REG_R15]; | |
493 | #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) | |
42a623c7 BS |
494 | pc = uc->uc_mcontext.gregs[R15]; |
495 | #else | |
496 | pc = uc->uc_mcontext.arm_pc; | |
497 | #endif | |
023b0ae3 PM |
498 | |
499 | /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or | |
500 | * later processor; on v5 we will always report this as a read). | |
501 | */ | |
502 | is_write = extract32(uc->uc_mcontext.error_code, 11, 1); | |
a78b1299 | 503 | return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); |
42a623c7 BS |
504 | } |
505 | ||
f129061c CF |
506 | #elif defined(__aarch64__) |
507 | ||
f454a54f PM |
508 | #ifndef ESR_MAGIC |
509 | /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ | |
510 | #define ESR_MAGIC 0x45535201 | |
511 | struct esr_context { | |
512 | struct _aarch64_ctx head; | |
513 | uint64_t esr; | |
514 | }; | |
515 | #endif | |
516 | ||
517 | static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) | |
518 | { | |
519 | return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; | |
520 | } | |
521 | ||
522 | static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) | |
523 | { | |
524 | return (struct _aarch64_ctx *)((char *)hdr + hdr->size); | |
525 | } | |
526 | ||
661f7fa4 | 527 | int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
f129061c CF |
528 | { |
529 | siginfo_t *info = pinfo; | |
04b33e21 | 530 | ucontext_t *uc = puc; |
661f7fa4 | 531 | uintptr_t pc = uc->uc_mcontext.pc; |
661f7fa4 | 532 | bool is_write; |
f454a54f PM |
533 | struct _aarch64_ctx *hdr; |
534 | struct esr_context const *esrctx = NULL; | |
661f7fa4 | 535 | |
f454a54f PM |
536 | /* Find the esr_context, which has the WnR bit in it */ |
537 | for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { | |
538 | if (hdr->magic == ESR_MAGIC) { | |
539 | esrctx = (struct esr_context const *)hdr; | |
540 | break; | |
541 | } | |
542 | } | |
661f7fa4 | 543 | |
f454a54f PM |
544 | if (esrctx) { |
545 | /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ | |
546 | uint64_t esr = esrctx->esr; | |
547 | is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; | |
548 | } else { | |
549 | /* | |
550 | * Fall back to parsing instructions; will only be needed | |
551 | * for really ancient (pre-3.16) kernels. | |
552 | */ | |
553 | uint32_t insn = *(uint32_t *)pc; | |
554 | ||
555 | is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ | |
556 | || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ | |
557 | || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ | |
558 | || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ | |
559 | || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ | |
560 | || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ | |
561 | || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ | |
562 | /* Ignore bits 10, 11 & 21, controlling indexing. */ | |
563 | || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ | |
564 | || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ | |
565 | /* Ignore bits 23 & 24, controlling indexing. */ | |
566 | || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ | |
567 | } | |
a78b1299 | 568 | return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); |
f129061c CF |
569 | } |
570 | ||
42a623c7 BS |
571 | #elif defined(__s390__) |
572 | ||
573 | int cpu_signal_handler(int host_signum, void *pinfo, | |
574 | void *puc) | |
575 | { | |
576 | siginfo_t *info = pinfo; | |
04b33e21 | 577 | ucontext_t *uc = puc; |
42a623c7 BS |
578 | unsigned long pc; |
579 | uint16_t *pinsn; | |
580 | int is_write = 0; | |
581 | ||
582 | pc = uc->uc_mcontext.psw.addr; | |
583 | ||
584 | /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead | |
585 | of the normal 2 arguments. The 3rd argument contains the "int_code" | |
586 | from the hardware which does in fact contain the is_write value. | |
587 | The rt signal handler, as far as I can tell, does not give this value | |
588 | at all. Not that we could get to it from here even if it were. */ | |
589 | /* ??? This is not even close to complete, since it ignores all | |
590 | of the read-modify-write instructions. */ | |
591 | pinsn = (uint16_t *)pc; | |
592 | switch (pinsn[0] >> 8) { | |
593 | case 0x50: /* ST */ | |
594 | case 0x42: /* STC */ | |
595 | case 0x40: /* STH */ | |
596 | is_write = 1; | |
597 | break; | |
598 | case 0xc4: /* RIL format insns */ | |
599 | switch (pinsn[0] & 0xf) { | |
600 | case 0xf: /* STRL */ | |
601 | case 0xb: /* STGRL */ | |
602 | case 0x7: /* STHRL */ | |
603 | is_write = 1; | |
604 | } | |
605 | break; | |
606 | case 0xe3: /* RXY format insns */ | |
607 | switch (pinsn[2] & 0xff) { | |
608 | case 0x50: /* STY */ | |
609 | case 0x24: /* STG */ | |
610 | case 0x72: /* STCY */ | |
611 | case 0x70: /* STHY */ | |
612 | case 0x8e: /* STPQ */ | |
613 | case 0x3f: /* STRVH */ | |
614 | case 0x3e: /* STRV */ | |
615 | case 0x2f: /* STRVG */ | |
616 | is_write = 1; | |
617 | } | |
618 | break; | |
619 | } | |
a78b1299 | 620 | return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); |
42a623c7 BS |
621 | } |
622 | ||
623 | #elif defined(__mips__) | |
624 | ||
625 | int cpu_signal_handler(int host_signum, void *pinfo, | |
626 | void *puc) | |
627 | { | |
628 | siginfo_t *info = pinfo; | |
04b33e21 | 629 | ucontext_t *uc = puc; |
42a623c7 BS |
630 | greg_t pc = uc->uc_mcontext.pc; |
631 | int is_write; | |
632 | ||
633 | /* XXX: compute is_write */ | |
634 | is_write = 0; | |
a78b1299 | 635 | return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); |
42a623c7 BS |
636 | } |
637 | ||
464e447a AF |
638 | #elif defined(__riscv) |
639 | ||
640 | int cpu_signal_handler(int host_signum, void *pinfo, | |
641 | void *puc) | |
642 | { | |
643 | siginfo_t *info = pinfo; | |
644 | ucontext_t *uc = puc; | |
645 | greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; | |
646 | uint32_t insn = *(uint32_t *)pc; | |
647 | int is_write = 0; | |
648 | ||
649 | /* Detect store by reading the instruction at the program | |
650 | counter. Note: we currently only generate 32-bit | |
651 | instructions so we thus only detect 32-bit stores */ | |
652 | switch (((insn >> 0) & 0b11)) { | |
653 | case 3: | |
654 | switch (((insn >> 2) & 0b11111)) { | |
655 | case 8: | |
656 | switch (((insn >> 12) & 0b111)) { | |
657 | case 0: /* sb */ | |
658 | case 1: /* sh */ | |
659 | case 2: /* sw */ | |
660 | case 3: /* sd */ | |
661 | case 4: /* sq */ | |
662 | is_write = 1; | |
663 | break; | |
664 | default: | |
665 | break; | |
666 | } | |
667 | break; | |
668 | case 9: | |
669 | switch (((insn >> 12) & 0b111)) { | |
670 | case 2: /* fsw */ | |
671 | case 3: /* fsd */ | |
672 | case 4: /* fsq */ | |
673 | is_write = 1; | |
674 | break; | |
675 | default: | |
676 | break; | |
677 | } | |
678 | break; | |
679 | default: | |
680 | break; | |
681 | } | |
682 | } | |
683 | ||
684 | /* Check for compressed instructions */ | |
685 | switch (((insn >> 13) & 0b111)) { | |
686 | case 7: | |
687 | switch (insn & 0b11) { | |
688 | case 0: /*c.sd */ | |
689 | case 2: /* c.sdsp */ | |
690 | is_write = 1; | |
691 | break; | |
692 | default: | |
693 | break; | |
694 | } | |
695 | break; | |
696 | case 6: | |
697 | switch (insn & 0b11) { | |
698 | case 0: /* c.sw */ | |
699 | case 3: /* c.swsp */ | |
700 | is_write = 1; | |
701 | break; | |
702 | default: | |
703 | break; | |
704 | } | |
705 | break; | |
706 | default: | |
707 | break; | |
708 | } | |
709 | ||
710 | return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); | |
711 | } | |
712 | ||
42a623c7 BS |
713 | #else |
714 | ||
715 | #error host CPU specific signal handler needed | |
716 | ||
717 | #endif | |
a411d296 PMD |
718 | |
719 | /* The softmmu versions of these helpers are in cputlb.c. */ | |
720 | ||
721 | /* Do not allow unaligned operations to proceed. Return the host address. */ | |
722 | static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, | |
723 | int size, uintptr_t retaddr) | |
724 | { | |
725 | /* Enforce qemu required alignment. */ | |
726 | if (unlikely(addr & (size - 1))) { | |
29a0af61 | 727 | cpu_loop_exit_atomic(env_cpu(env), retaddr); |
a411d296 | 728 | } |
08b97f7f RH |
729 | void *ret = g2h(addr); |
730 | set_helper_retaddr(retaddr); | |
731 | return ret; | |
a411d296 PMD |
732 | } |
733 | ||
734 | /* Macro to call the above, with local variables from the use context. */ | |
34d49937 | 735 | #define ATOMIC_MMU_DECLS do {} while (0) |
a411d296 | 736 | #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) |
08b97f7f | 737 | #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) |
a411d296 PMD |
738 | |
739 | #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) | |
740 | #define EXTRA_ARGS | |
741 | ||
742 | #define DATA_SIZE 1 | |
743 | #include "atomic_template.h" | |
744 | ||
745 | #define DATA_SIZE 2 | |
746 | #include "atomic_template.h" | |
747 | ||
748 | #define DATA_SIZE 4 | |
749 | #include "atomic_template.h" | |
750 | ||
751 | #ifdef CONFIG_ATOMIC64 | |
752 | #define DATA_SIZE 8 | |
753 | #include "atomic_template.h" | |
754 | #endif | |
755 | ||
756 | /* The following is only callable from other helpers, and matches up | |
757 | with the softmmu version. */ | |
758 | ||
e6cd4bb5 | 759 | #if HAVE_ATOMIC128 || HAVE_CMPXCHG128 |
a411d296 PMD |
760 | |
761 | #undef EXTRA_ARGS | |
762 | #undef ATOMIC_NAME | |
763 | #undef ATOMIC_MMU_LOOKUP | |
764 | ||
765 | #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr | |
766 | #define ATOMIC_NAME(X) \ | |
767 | HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) | |
768 | #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr) | |
769 | ||
770 | #define DATA_SIZE 16 | |
771 | #include "atomic_template.h" | |
e6cd4bb5 | 772 | #endif |