[mirror_ubuntu-bionic-kernel.git] / arch / alpha / kernel / sys_nautilus.c

/*
 *	linux/arch/alpha/kernel/sys_nautilus.c
 *
 *	Copyright (C) 1995 David A Rusling
 *	Copyright (C) 1998 Richard Henderson
 *	Copyright (C) 1999 Alpha Processor, Inc.,
 *		(David Daniel, Stig Telfer, Soohoon Lee)
 *
 * Code supporting NAUTILUS systems.
 *
 *
 * NAUTILUS has the following I/O features:
 *
 * a) Driven by AMD 751 aka IRONGATE (northbridge):
 *     4 PCI slots
 *     1 AGP slot
 *
 * b) Driven by ALI M1543C (southbridge)
 *     2 ISA slots
 *     2 IDE connectors
 *     1 dual drive capable FDD controller
 *     2 serial ports
 *     1 ECP/EPP/SP parallel port
 *     2 USB ports
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/reboot.h>
#include <linux/bootmem.h>
#include <linux/bitops.h>

#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/pgtable.h>
#include <asm/core_irongate.h>
#include <asm/hwrpb.h>
#include <asm/tlbflush.h>

#include "proto.h"
#include "err_impl.h"
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"


static void __init
nautilus_init_irq(void)
{
	if (alpha_using_srm) {
		alpha_mv.device_interrupt = srm_device_interrupt;
	}

	init_i8259a_irqs();
	common_init_isa_dma();
}

static int __init
nautilus_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	/* Preserve the IRQ set up by the console.  */

	u8 irq;
	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	return irq;
}

void
nautilus_kill_arch(int mode)
{
	struct pci_bus *bus = pci_isa_hose->bus;
	u32 pmuport;
	int off;

	switch (mode) {
	case LINUX_REBOOT_CMD_RESTART:
		if (! alpha_using_srm) {
			u8 t8;
			pci_bus_read_config_byte(bus, 0x38, 0x43, &t8);
			pci_bus_write_config_byte(bus, 0x38, 0x43, t8 | 0x80);
			outb(1, 0x92);
			outb(0, 0x92);
			/* NOTREACHED */
		}
		break;

	case LINUX_REBOOT_CMD_POWER_OFF:
		/* Assume M1543C */
		off = 0x2000;		/* SLP_TYPE = 0, SLP_EN = 1 */
		pci_bus_read_config_dword(bus, 0x88, 0x10, &pmuport);
		if (!pmuport) {
			/* M1535D/D+ */
			off = 0x3400;	/* SLP_TYPE = 5, SLP_EN = 1 */
			pci_bus_read_config_dword(bus, 0x88, 0xe0, &pmuport);
		}
		pmuport &= 0xfffe;
		outw(0xffff, pmuport);	/* Clear pending events. */
		outw(off, pmuport + 4);
		/* NOTREACHED */
		break;
	}
}

/* Perform analysis of a machine check that arrived from the system (NMI) */

static void
naut_sys_machine_check(unsigned long vector, unsigned long la_ptr,
		       struct pt_regs *regs)
{
	printk("PC %lx RA %lx\n", regs->pc, regs->r26);
	irongate_pci_clr_err();
}

/* Machine checks can come from two sources - those on the CPU and those
   in the system.  They are analysed separately but all starts here.  */

void
nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
{
	char *mchk_class;

	/* Now for some analysis.  Machine checks fall into two classes --
	   those picked up by the system, and those picked up by the CPU.
	   Add to that the two levels of severity - correctable or not.  */

	if (vector == SCB_Q_SYSMCHK
	    && ((IRONGATE0->dramms & 0x300) == 0x300)) {
		unsigned long nmi_ctl;

		/* Clear ALI NMI */
		nmi_ctl = inb(0x61);
		nmi_ctl |= 0x0c;
		outb(nmi_ctl, 0x61);
		nmi_ctl &= ~0x0c;
		outb(nmi_ctl, 0x61);

		/* Write again clears error bits.  */
		IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100;
		mb();
		IRONGATE0->stat_cmd;

		/* Write again clears error bits.  */
		IRONGATE0->dramms = IRONGATE0->dramms;
		mb();
		IRONGATE0->dramms;

		draina();
		wrmces(0x7);
		mb();
		return;
	}

	if (vector == SCB_Q_SYSERR)
		mchk_class = "Correctable";
	else if (vector == SCB_Q_SYSMCHK)
		mchk_class = "Fatal";
	else {
		ev6_machine_check(vector, la_ptr);
		return;
	}

	printk(KERN_CRIT "NAUTILUS Machine check 0x%lx "
			 "[%s System Machine Check (NMI)]\n",
	       vector, mchk_class);

	naut_sys_machine_check(vector, la_ptr, get_irq_regs());

	/* Tell the PALcode to clear the machine check */
	draina();
	wrmces(0x7);
	mb();
}

extern void free_reserved_mem(void *, void *);

static struct resource irongate_mem = {
	.name	= "Irongate PCI MEM",
	.flags	= IORESOURCE_MEM,
};

void __init
nautilus_init_pci(void)
{
	struct pci_controller *hose = hose_head;
	struct pci_bus *bus;
	struct pci_dev *irongate;
	unsigned long bus_align, bus_size, pci_mem;
	unsigned long memtop = max_low_pfn << PAGE_SHIFT;

	/* Scan our single hose.  */
	bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
	hose->bus = bus;

	irongate = pci_find_slot(0, 0);
	bus->self = irongate;
	bus->resource[1] = &irongate_mem;

	pci_bus_size_bridges(bus);

	/* IO port range. */
	bus->resource[0]->start = 0;
	bus->resource[0]->end = 0xffff;

	/* Set up PCI memory range - limit is hardwired to 0xffffffff,
	   base must be at aligned to 16Mb. */
	bus_align = bus->resource[1]->start;
	bus_size = bus->resource[1]->end + 1 - bus_align;
	if (bus_align < 0x1000000UL)
		bus_align = 0x1000000UL;

	pci_mem = (0x100000000UL - bus_size) & -bus_align;

	bus->resource[1]->start = pci_mem;
	bus->resource[1]->end = 0xffffffffUL;
	if (request_resource(&iomem_resource, bus->resource[1]) < 0)
		printk(KERN_ERR "Failed to request MEM on hose 0\n");

	if (pci_mem < memtop)
		memtop = pci_mem;
	if (memtop > alpha_mv.min_mem_address) {
		free_reserved_mem(__va(alpha_mv.min_mem_address),
				  __va(memtop));
		printk("nautilus_init_pci: %ldk freed\n",
			(memtop - alpha_mv.min_mem_address) >> 10);
	}

	if ((IRONGATE0->dev_vendor >> 16) > 0x7006)	/* Albacore? */
		IRONGATE0->pci_mem = pci_mem;

	pci_bus_assign_resources(bus);
	pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
}

/*
 * The System Vectors
 */

struct alpha_machine_vector nautilus_mv __initmv = {
	.vector_name		= "Nautilus",
	DO_EV6_MMU,
	DO_DEFAULT_RTC,
	DO_IRONGATE_IO,
	.machine_check		= nautilus_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= IRONGATE_DEFAULT_MEM_BASE,

	.nr_irqs		= 16,
	.device_interrupt	= isa_device_interrupt,

	.init_arch		= irongate_init_arch,
	.init_irq		= nautilus_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= nautilus_init_pci,
	.kill_arch		= nautilus_kill_arch,
	.pci_map_irq		= nautilus_map_irq,
	.pci_swizzle		= common_swizzle,
};
ALIAS_MV(nautilus)
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/alpha/kernel/sys_nautilus.c
	3	*
	4	* Copyright (C) 1995 David A Rusling
	5	* Copyright (C) 1998 Richard Henderson
	6	* Copyright (C) 1999 Alpha Processor, Inc.,
	7	* (David Daniel, Stig Telfer, Soohoon Lee)
	8	*
	9	* Code supporting NAUTILUS systems.
	10	*
	11	*
	12	* NAUTILUS has the following I/O features:
	13	*
	14	* a) Driven by AMD 751 aka IRONGATE (northbridge):
	15	* 4 PCI slots
	16	* 1 AGP slot
	17	*
	18	* b) Driven by ALI M1543C (southbridge)
	19	* 2 ISA slots
	20	* 2 IDE connectors
	21	* 1 dual drive capable FDD controller
	22	* 2 serial ports
	23	* 1 ECP/EPP/SP parallel port
	24	* 2 USB ports
	25	*/
	26
	27	#include <linux/kernel.h>
	28	#include <linux/types.h>
	29	#include <linux/mm.h>
	30	#include <linux/sched.h>
	31	#include <linux/pci.h>
	32	#include <linux/init.h>
	33	#include <linux/reboot.h>
	34	#include <linux/bootmem.h>
	35	#include <linux/bitops.h>
	36
	37	#include <asm/ptrace.h>
	38	#include <asm/system.h>
	39	#include <asm/dma.h>
	40	#include <asm/irq.h>
	41	#include <asm/mmu_context.h>
	42	#include <asm/io.h>
	43	#include <asm/pci.h>
	44	#include <asm/pgtable.h>
	45	#include <asm/core_irongate.h>
	46	#include <asm/hwrpb.h>
	47	#include <asm/tlbflush.h>
	48
	49	#include "proto.h"
	50	#include "err_impl.h"
	51	#include "irq_impl.h"
	52	#include "pci_impl.h"
	53	#include "machvec_impl.h"
	54
	55
	56	static void __init
	57	nautilus_init_irq(void)
	58	{
	59	if (alpha_using_srm) {
	60	alpha_mv.device_interrupt = srm_device_interrupt;
	61	}
	62
	63	init_i8259a_irqs();
	64	common_init_isa_dma();
65	}
66
67	static int __init
68	nautilus_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
69	{
70	/* Preserve the IRQ set up by the console. */
71
72	u8 irq;
73	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
74	return irq;
75	}
76
77	void
78	nautilus_kill_arch(int mode)
79	{
80	struct pci_bus *bus = pci_isa_hose->bus;
81	u32 pmuport;
82	int off;
83
84	switch (mode) {
85	case LINUX_REBOOT_CMD_RESTART:
86	if (! alpha_using_srm) {
87	u8 t8;
88	pci_bus_read_config_byte(bus, 0x38, 0x43, &t8);
89	pci_bus_write_config_byte(bus, 0x38, 0x43, t8 \| 0x80);
90	outb(1, 0x92);
91	outb(0, 0x92);
92	/* NOTREACHED */
93	}
94	break;
95
96	case LINUX_REBOOT_CMD_POWER_OFF:
97	/* Assume M1543C */
98	off = 0x2000; /* SLP_TYPE = 0, SLP_EN = 1 */
99	pci_bus_read_config_dword(bus, 0x88, 0x10, &pmuport);
100	if (!pmuport) {
101	/* M1535D/D+ */
102	off = 0x3400; /* SLP_TYPE = 5, SLP_EN = 1 */
103	pci_bus_read_config_dword(bus, 0x88, 0xe0, &pmuport);
104	}
105	pmuport &= 0xfffe;
106	outw(0xffff, pmuport); /* Clear pending events. */
107	outw(off, pmuport + 4);
108	/* NOTREACHED */
109	break;
110	}
111	}
112
113	/* Perform analysis of a machine check that arrived from the system (NMI) */
114
115	static void
116	naut_sys_machine_check(unsigned long vector, unsigned long la_ptr,
117	struct pt_regs *regs)
118	{
119	printk("PC %lx RA %lx\n", regs->pc, regs->r26);
120	irongate_pci_clr_err();
121	}
122
123	/* Machine checks can come from two sources - those on the CPU and those
124	in the system. They are analysed separately but all starts here. */
125
126	void
4fa1970a	127	nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
1da177e4 LT	128	{
	129	char *mchk_class;
	130
	131	/* Now for some analysis. Machine checks fall into two classes --
	132	those picked up by the system, and those picked up by the CPU.
	133	Add to that the two levels of severity - correctable or not. */
	134
	135	if (vector == SCB_Q_SYSMCHK
	136	&& ((IRONGATE0->dramms & 0x300) == 0x300)) {
	137	unsigned long nmi_ctl;
	138
	139	/* Clear ALI NMI */
	140	nmi_ctl = inb(0x61);
	141	nmi_ctl \|= 0x0c;
	142	outb(nmi_ctl, 0x61);
	143	nmi_ctl &= ~0x0c;
	144	outb(nmi_ctl, 0x61);
	145
	146	/* Write again clears error bits. */
	147	IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100;
	148	mb();
	149	IRONGATE0->stat_cmd;
	150
	151	/* Write again clears error bits. */
	152	IRONGATE0->dramms = IRONGATE0->dramms;
	153	mb();
	154	IRONGATE0->dramms;
	155
	156	draina();
	157	wrmces(0x7);
	158	mb();
	159	return;
	160	}
	161
	162	if (vector == SCB_Q_SYSERR)
	163	mchk_class = "Correctable";
	164	else if (vector == SCB_Q_SYSMCHK)
	165	mchk_class = "Fatal";
	166	else {
4fa1970a	167	ev6_machine_check(vector, la_ptr);
1da177e4 LT	168	return;
	169	}
	170
	171	printk(KERN_CRIT "NAUTILUS Machine check 0x%lx "
	172	"[%s System Machine Check (NMI)]\n",
	173	vector, mchk_class);
	174
4fa1970a	175	naut_sys_machine_check(vector, la_ptr, get_irq_regs());
1da177e4 LT	176
	177	/* Tell the PALcode to clear the machine check */
	178	draina();
	179	wrmces(0x7);
	180	mb();
	181	}
	182
	183	extern void free_reserved_mem(void , void );
	184
	185	static struct resource irongate_mem = {
	186	.name = "Irongate PCI MEM",
	187	.flags = IORESOURCE_MEM,
	188	};
	189
	190	void __init
	191	nautilus_init_pci(void)
	192	{
	193	struct pci_controller *hose = hose_head;
	194	struct pci_bus *bus;
	195	struct pci_dev *irongate;
	196	unsigned long bus_align, bus_size, pci_mem;
	197	unsigned long memtop = max_low_pfn << PAGE_SHIFT;
	198
	199	/* Scan our single hose. */
	200	bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
	201	hose->bus = bus;
	202
	203	irongate = pci_find_slot(0, 0);
	204	bus->self = irongate;
	205	bus->resource[1] = &irongate_mem;
	206
	207	pci_bus_size_bridges(bus);
	208
	209	/* IO port range. */
	210	bus->resource[0]->start = 0;
	211	bus->resource[0]->end = 0xffff;
	212
	213	/* Set up PCI memory range - limit is hardwired to 0xffffffff,
	214	base must be at aligned to 16Mb. */
	215	bus_align = bus->resource[1]->start;
	216	bus_size = bus->resource[1]->end + 1 - bus_align;
	217	if (bus_align < 0x1000000UL)
	218	bus_align = 0x1000000UL;
	219
	220	pci_mem = (0x100000000UL - bus_size) & -bus_align;
	221
	222	bus->resource[1]->start = pci_mem;
	223	bus->resource[1]->end = 0xffffffffUL;
	224	if (request_resource(&iomem_resource, bus->resource[1]) < 0)
	225	printk(KERN_ERR "Failed to request MEM on hose 0\n");
	226
	227	if (pci_mem < memtop)
	228	memtop = pci_mem;
	229	if (memtop > alpha_mv.min_mem_address) {
	230	free_reserved_mem(__va(alpha_mv.min_mem_address),
	231	__va(memtop));
	232	printk("nautilus_init_pci: %ldk freed\n",
	233	(memtop - alpha_mv.min_mem_address) >> 10);
	234	}
	235
	236	if ((IRONGATE0->dev_vendor >> 16) > 0x7006) /* Albacore? */
	237	IRONGATE0->pci_mem = pci_mem;
	238
	239	pci_bus_assign_resources(bus);
240	pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
241	}
242
243	/*
244	* The System Vectors
245	*/
246
247	struct alpha_machine_vector nautilus_mv __initmv = {
248	.vector_name = "Nautilus",
249	DO_EV6_MMU,
250	DO_DEFAULT_RTC,
251	DO_IRONGATE_IO,
252	.machine_check = nautilus_machine_check,
253	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
254	.min_io_address = DEFAULT_IO_BASE,
255	.min_mem_address = IRONGATE_DEFAULT_MEM_BASE,
256
257	.nr_irqs = 16,
258	.device_interrupt = isa_device_interrupt,
259
260	.init_arch = irongate_init_arch,
261	.init_irq = nautilus_init_irq,
262	.init_rtc = common_init_rtc,
263	.init_pci = nautilus_init_pci,
264	.kill_arch = nautilus_kill_arch,
265	.pci_map_irq = nautilus_map_irq,
266	.pci_swizzle = common_swizzle,
267	};
268	ALIAS_MV(nautilus)