[mirror_ubuntu-bionic-kernel.git] / arch / alpha / kernel / sys_titan.c

// SPDX-License-Identifier: GPL-2.0
/*
 *	linux/arch/alpha/kernel/sys_titan.c
 *
 *	Copyright (C) 1995 David A Rusling
 *	Copyright (C) 1996, 1999 Jay A Estabrook
 *	Copyright (C) 1998, 1999 Richard Henderson
 *      Copyright (C) 1999, 2000 Jeff Wiedemeier
 *
 * Code supporting TITAN systems (EV6+TITAN), currently:
 *      Privateer
 *	Falcon
 *	Granite
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/bitops.h>

#include <asm/ptrace.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/core_titan.h>
#include <asm/hwrpb.h>
#include <asm/tlbflush.h>

#include "proto.h"
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
#include "err_impl.h"

\f
/*
 * Titan generic
 */

/*
 * Titan supports up to 4 CPUs
 */
static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL };

/*
 * Mask is set (1) if enabled
 */
static unsigned long titan_cached_irq_mask;

/*
 * Need SMP-safe access to interrupt CSRs
 */
DEFINE_SPINLOCK(titan_irq_lock);

static void
titan_update_irq_hw(unsigned long mask)
{
	register titan_cchip *cchip = TITAN_cchip;
	unsigned long isa_enable = 1UL << 55;
	register int bcpu = boot_cpuid;

#ifdef CONFIG_SMP
	cpumask_t cpm;
	volatile unsigned long *dim0, *dim1, *dim2, *dim3;
	unsigned long mask0, mask1, mask2, mask3, dummy;

	cpumask_copy(&cpm, cpu_present_mask);
	mask &= ~isa_enable;
	mask0 = mask & titan_cpu_irq_affinity[0];
	mask1 = mask & titan_cpu_irq_affinity[1];
	mask2 = mask & titan_cpu_irq_affinity[2];
	mask3 = mask & titan_cpu_irq_affinity[3];

	if (bcpu == 0) mask0 |= isa_enable;
	else if (bcpu == 1) mask1 |= isa_enable;
	else if (bcpu == 2) mask2 |= isa_enable;
	else mask3 |= isa_enable;

	dim0 = &cchip->dim0.csr;
	dim1 = &cchip->dim1.csr;
	dim2 = &cchip->dim2.csr;
	dim3 = &cchip->dim3.csr;
	if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy;
	if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy;
	if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy;
	if (!cpumask_test_cpu(3, &cpm)) dim3 = &dummy;

	*dim0 = mask0;
	*dim1 = mask1;
	*dim2 = mask2;
	*dim3 = mask3;
	mb();
	*dim0;
	*dim1;
	*dim2;
	*dim3;
#else
	volatile unsigned long *dimB;
	dimB = &cchip->dim0.csr;
	if (bcpu == 1) dimB = &cchip->dim1.csr;
	else if (bcpu == 2) dimB = &cchip->dim2.csr;
	else if (bcpu == 3) dimB = &cchip->dim3.csr;

	*dimB = mask | isa_enable;
	mb();
	*dimB;
#endif
}

static inline void
titan_enable_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;
	spin_lock(&titan_irq_lock);
	titan_cached_irq_mask |= 1UL << (irq - 16);
	titan_update_irq_hw(titan_cached_irq_mask);
	spin_unlock(&titan_irq_lock);
}

static inline void
titan_disable_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;
	spin_lock(&titan_irq_lock);
	titan_cached_irq_mask &= ~(1UL << (irq - 16));
	titan_update_irq_hw(titan_cached_irq_mask);
	spin_unlock(&titan_irq_lock);
}

static void
titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
{
	int cpu;

	for (cpu = 0; cpu < 4; cpu++) {
		if (cpumask_test_cpu(cpu, &affinity))
			titan_cpu_irq_affinity[cpu] |= 1UL << irq;
		else
			titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
	}

}

static int
titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
		       bool force)
{ 
	unsigned int irq = d->irq;
	spin_lock(&titan_irq_lock);
	titan_cpu_set_irq_affinity(irq - 16, *affinity);
	titan_update_irq_hw(titan_cached_irq_mask);
	spin_unlock(&titan_irq_lock);

	return 0;
}

static void
titan_device_interrupt(unsigned long vector)
{
	printk("titan_device_interrupt: NOT IMPLEMENTED YET!!\n");
}

static void 
titan_srm_device_interrupt(unsigned long vector)
{
	int irq;

	irq = (vector - 0x800) >> 4;
	handle_irq(irq);
}


static void __init
init_titan_irqs(struct irq_chip * ops, int imin, int imax)
{
	long i;
	for (i = imin; i <= imax; ++i) {
		irq_set_chip_and_handler(i, ops, handle_level_irq);
		irq_set_status_flags(i, IRQ_LEVEL);
	}
}

static struct irq_chip titan_irq_type = {
       .name			= "TITAN",
       .irq_unmask		= titan_enable_irq,
       .irq_mask		= titan_disable_irq,
       .irq_mask_ack		= titan_disable_irq,
       .irq_set_affinity	= titan_set_irq_affinity,
};

static irqreturn_t
titan_intr_nop(int irq, void *dev_id)
{
      /*
       * This is a NOP interrupt handler for the purposes of
       * event counting -- just return.
       */                                                                     
       return IRQ_HANDLED;
}

static void __init
titan_init_irq(void)
{
	if (alpha_using_srm && !alpha_mv.device_interrupt)
		alpha_mv.device_interrupt = titan_srm_device_interrupt;
	if (!alpha_mv.device_interrupt)
		alpha_mv.device_interrupt = titan_device_interrupt;

	titan_update_irq_hw(0);

	init_titan_irqs(&titan_irq_type, 16, 63 + 16);
}
  
static void __init
titan_legacy_init_irq(void)
{
	/* init the legacy dma controller */
	outb(0, DMA1_RESET_REG);
	outb(0, DMA2_RESET_REG);
	outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
	outb(0, DMA2_MASK_REG);

	/* init the legacy irq controller */
	init_i8259a_irqs();

	/* init the titan irqs */
	titan_init_irq();
}

void
titan_dispatch_irqs(u64 mask)
{
	unsigned long vector;

	/*
	 * Mask down to those interrupts which are enable on this processor
	 */
	mask &= titan_cpu_irq_affinity[smp_processor_id()];

	/*
	 * Dispatch all requested interrupts 
	 */
	while (mask) {
		/* convert to SRM vector... priority is <63> -> <0> */
		vector = 63 - __kernel_ctlz(mask);
		mask &= ~(1UL << vector);	/* clear it out 	 */
		vector = 0x900 + (vector << 4);	/* convert to SRM vector */
		
		/* dispatch it */
		alpha_mv.device_interrupt(vector);
	}
}
  
\f
/*
 * Titan Family
 */
static void __init
titan_request_irq(unsigned int irq, irq_handler_t handler,
		  unsigned long irqflags, const char *devname,
		  void *dev_id)
{
	int err;
	err = request_irq(irq, handler, irqflags, devname, dev_id);
	if (err) {
		printk("titan_request_irq for IRQ %d returned %d; ignoring\n",
		       irq, err);
	}
}

static void __init
titan_late_init(void)
{
	/*
	 * Enable the system error interrupts. These interrupts are 
	 * all reported to the kernel as machine checks, so the handler
	 * is a nop so it can be called to count the individual events.
	 */
	titan_request_irq(63+16, titan_intr_nop, 0,
		    "CChip Error", NULL);
	titan_request_irq(62+16, titan_intr_nop, 0,
		    "PChip 0 H_Error", NULL);
	titan_request_irq(61+16, titan_intr_nop, 0,
		    "PChip 1 H_Error", NULL);
	titan_request_irq(60+16, titan_intr_nop, 0,
		    "PChip 0 C_Error", NULL);
	titan_request_irq(59+16, titan_intr_nop, 0,
		    "PChip 1 C_Error", NULL);

	/* 
	 * Register our error handlers.
	 */
	titan_register_error_handlers();

	/*
	 * Check if the console left us any error logs.
	 */
	cdl_check_console_data_log();

}

static int
titan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	u8 intline;
	int irq;

 	/* Get the current intline.  */
	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
	irq = intline;

 	/* Is it explicitly routed through ISA?  */
 	if ((irq & 0xF0) == 0xE0)
 		return irq;
 
 	/* Offset by 16 to make room for ISA interrupts 0 - 15.  */
 	return irq + 16;
}

static void __init
titan_init_pci(void)
{
 	/*
 	 * This isn't really the right place, but there's some init
 	 * that needs to be done after everything is basically up.
 	 */
 	titan_late_init();
 
	/* Indicate that we trust the console to configure things properly */
	pci_set_flags(PCI_PROBE_ONLY);
	common_init_pci();
	SMC669_Init(0);
	locate_and_init_vga(NULL);
}

\f
/*
 * Privateer
 */
static void __init
privateer_init_pci(void)
{
	/*
	 * Hook a couple of extra err interrupts that the
	 * common titan code won't.
	 */
	titan_request_irq(53+16, titan_intr_nop, 0,
		    "NMI", NULL);
	titan_request_irq(50+16, titan_intr_nop, 0,
		    "Temperature Warning", NULL);

	/*
	 * Finish with the common version.
	 */
	return titan_init_pci();
}

\f
/*
 * The System Vectors.
 */
struct alpha_machine_vector titan_mv __initmv = {
	.vector_name		= "TITAN",
	DO_EV6_MMU,
	DO_DEFAULT_RTC,
	DO_TITAN_IO,
	.machine_check		= titan_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,
	.pci_dac_offset		= TITAN_DAC_OFFSET,

	.nr_irqs		= 80,	/* 64 + 16 */
	/* device_interrupt will be filled in by titan_init_irq */

	.agp_info		= titan_agp_info,

	.init_arch		= titan_init_arch,
	.init_irq		= titan_legacy_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= titan_init_pci,

	.kill_arch		= titan_kill_arch,
	.pci_map_irq		= titan_map_irq,
	.pci_swizzle		= common_swizzle,
};
ALIAS_MV(titan)

struct alpha_machine_vector privateer_mv __initmv = {
	.vector_name		= "PRIVATEER",
	DO_EV6_MMU,
	DO_DEFAULT_RTC,
	DO_TITAN_IO,
	.machine_check		= privateer_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,
	.pci_dac_offset		= TITAN_DAC_OFFSET,

	.nr_irqs		= 80,	/* 64 + 16 */
	/* device_interrupt will be filled in by titan_init_irq */

	.agp_info		= titan_agp_info,

	.init_arch		= titan_init_arch,
	.init_irq		= titan_legacy_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= privateer_init_pci,

	.kill_arch		= titan_kill_arch,
	.pci_map_irq		= titan_map_irq,
	.pci_swizzle		= common_swizzle,
};
/* No alpha_mv alias for privateer since we compile it 
   in unconditionally with titan; setup_arch knows how to cope. */
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* linux/arch/alpha/kernel/sys_titan.c
	4	*
	5	* Copyright (C) 1995 David A Rusling
	6	* Copyright (C) 1996, 1999 Jay A Estabrook
	7	* Copyright (C) 1998, 1999 Richard Henderson
	8	* Copyright (C) 1999, 2000 Jeff Wiedemeier
	9	*
	10	* Code supporting TITAN systems (EV6+TITAN), currently:
	11	* Privateer
	12	* Falcon
	13	* Granite
	14	*/
	15
1da177e4 LT	16	#include <linux/kernel.h>
	17	#include <linux/types.h>
	18	#include <linux/mm.h>
	19	#include <linux/sched.h>
	20	#include <linux/pci.h>
	21	#include <linux/init.h>
	22	#include <linux/bitops.h>
	23
	24	#include <asm/ptrace.h>
1da177e4 LT	25	#include <asm/dma.h>
	26	#include <asm/irq.h>
	27	#include <asm/mmu_context.h>
	28	#include <asm/io.h>
	29	#include <asm/pgtable.h>
	30	#include <asm/core_titan.h>
	31	#include <asm/hwrpb.h>
	32	#include <asm/tlbflush.h>
	33
	34	#include "proto.h"
	35	#include "irq_impl.h"
	36	#include "pci_impl.h"
	37	#include "machvec_impl.h"
	38	#include "err_impl.h"
	39
	40	\f
	41	/*
	42	* Titan generic
	43	*/
	44
	45	/*
	46	* Titan supports up to 4 CPUs
	47	*/
	48	static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL };
	49
	50	/*
	51	* Mask is set (1) if enabled
	52	*/
	53	static unsigned long titan_cached_irq_mask;
	54
	55	/*
	56	* Need SMP-safe access to interrupt CSRs
	57	*/
	58	DEFINE_SPINLOCK(titan_irq_lock);
	59
	60	static void
	61	titan_update_irq_hw(unsigned long mask)
	62	{
	63	register titan_cchip *cchip = TITAN_cchip;
	64	unsigned long isa_enable = 1UL << 55;
	65	register int bcpu = boot_cpuid;
	66
	67	#ifdef CONFIG_SMP
81740fc6	68	cpumask_t cpm;
1da177e4 LT	69	volatile unsigned long dim0, dim1, dim2, dim3;
	70	unsigned long mask0, mask1, mask2, mask3, dummy;
	71
81740fc6	72	cpumask_copy(&cpm, cpu_present_mask);
1da177e4 LT	73	mask &= ~isa_enable;
	74	mask0 = mask & titan_cpu_irq_affinity[0];
	75	mask1 = mask & titan_cpu_irq_affinity[1];
	76	mask2 = mask & titan_cpu_irq_affinity[2];
	77	mask3 = mask & titan_cpu_irq_affinity[3];
	78
	79	if (bcpu == 0) mask0 \|= isa_enable;
	80	else if (bcpu == 1) mask1 \|= isa_enable;
	81	else if (bcpu == 2) mask2 \|= isa_enable;
	82	else mask3 \|= isa_enable;
	83
	84	dim0 = &cchip->dim0.csr;
	85	dim1 = &cchip->dim1.csr;
	86	dim2 = &cchip->dim2.csr;
	87	dim3 = &cchip->dim3.csr;
81740fc6 KM	88	if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy;
	89	if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy;
	90	if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy;
	91	if (!cpumask_test_cpu(3, &cpm)) dim3 = &dummy;
1da177e4 LT	92
	93	*dim0 = mask0;
	94	*dim1 = mask1;
	95	*dim2 = mask2;
	96	*dim3 = mask3;
	97	mb();
	98	*dim0;
	99	*dim1;
	100	*dim2;
	101	*dim3;
	102	#else
	103	volatile unsigned long *dimB;
	104	dimB = &cchip->dim0.csr;
	105	if (bcpu == 1) dimB = &cchip->dim1.csr;
	106	else if (bcpu == 2) dimB = &cchip->dim2.csr;
	107	else if (bcpu == 3) dimB = &cchip->dim3.csr;
	108
	109	*dimB = mask \| isa_enable;
	110	mb();
	111	*dimB;
	112	#endif
	113	}
	114
	115	static inline void
628150ca	116	titan_enable_irq(struct irq_data *d)
1da177e4	117	{
628150ca	118	unsigned int irq = d->irq;
1da177e4 LT	119	spin_lock(&titan_irq_lock);
	120	titan_cached_irq_mask \|= 1UL << (irq - 16);
	121	titan_update_irq_hw(titan_cached_irq_mask);
	122	spin_unlock(&titan_irq_lock);
	123	}
	124
	125	static inline void
628150ca	126	titan_disable_irq(struct irq_data *d)
1da177e4	127	{
628150ca	128	unsigned int irq = d->irq;
1da177e4 LT	129	spin_lock(&titan_irq_lock);
	130	titan_cached_irq_mask &= ~(1UL << (irq - 16));
	131	titan_update_irq_hw(titan_cached_irq_mask);
	132	spin_unlock(&titan_irq_lock);
	133	}
	134
1da177e4 LT	135	static void
	136	titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
	137	{
	138	int cpu;
	139
	140	for (cpu = 0; cpu < 4; cpu++) {
81740fc6	141	if (cpumask_test_cpu(cpu, &affinity))
1da177e4 LT	142	titan_cpu_irq_affinity[cpu] \|= 1UL << irq;
	143	else
	144	titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
	145	}
	146
	147	}
	148
d5dedd45	149	static int
628150ca TG	150	titan_set_irq_affinity(struct irq_data d, const struct cpumask affinity,
628150ca TG	151	bool force)
1da177e4	152	{
fbf855d7	153	unsigned int irq = d->irq;
1da177e4	154	spin_lock(&titan_irq_lock);
0de26520	155	titan_cpu_set_irq_affinity(irq - 16, *affinity);
1da177e4 LT	156	titan_update_irq_hw(titan_cached_irq_mask);
1da177e4 LT	157	spin_unlock(&titan_irq_lock);
d5dedd45 YL	158
d5dedd45 YL	159	return 0;
1da177e4 LT	160	}
	161
	162	static void
7ca56053	163	titan_device_interrupt(unsigned long vector)
1da177e4	164	{
7f2d889c	165	printk("titan_device_interrupt: NOT IMPLEMENTED YET!!\n");
1da177e4 LT	166	}
	167
	168	static void
7ca56053	169	titan_srm_device_interrupt(unsigned long vector)
1da177e4 LT	170	{
	171	int irq;
	172
	173	irq = (vector - 0x800) >> 4;
3dbb8c62	174	handle_irq(irq);
1da177e4 LT	175	}
	176
	177
	178	static void __init
44377f62	179	init_titan_irqs(struct irq_chip * ops, int imin, int imax)
1da177e4 LT	180	{
	181	long i;
	182	for (i = imin; i <= imax; ++i) {
a9eb076b	183	irq_set_chip_and_handler(i, ops, handle_level_irq);
628150ca	184	irq_set_status_flags(i, IRQ_LEVEL);
1da177e4 LT	185	}
	186	}
	187
44377f62	188	static struct irq_chip titan_irq_type = {
628150ca TG	189	.name = "TITAN",
	190	.irq_unmask = titan_enable_irq,
	191	.irq_mask = titan_disable_irq,
	192	.irq_mask_ack = titan_disable_irq,
	193	.irq_set_affinity = titan_set_irq_affinity,
1da177e4 LT	194	};
	195
	196	static irqreturn_t
041a6bae	197	titan_intr_nop(int irq, void *dev_id)
1da177e4 LT	198	{
	199	/*
	200	* This is a NOP interrupt handler for the purposes of
	201	* event counting -- just return.
	202	*/
	203	return IRQ_HANDLED;
	204	}
	205
	206	static void __init
	207	titan_init_irq(void)
	208	{
	209	if (alpha_using_srm && !alpha_mv.device_interrupt)
	210	alpha_mv.device_interrupt = titan_srm_device_interrupt;
	211	if (!alpha_mv.device_interrupt)
	212	alpha_mv.device_interrupt = titan_device_interrupt;
	213
	214	titan_update_irq_hw(0);
	215
	216	init_titan_irqs(&titan_irq_type, 16, 63 + 16);
	217	}
	218
	219	static void __init
	220	titan_legacy_init_irq(void)
	221	{
	222	/* init the legacy dma controller */
	223	outb(0, DMA1_RESET_REG);
	224	outb(0, DMA2_RESET_REG);
	225	outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
	226	outb(0, DMA2_MASK_REG);
	227
	228	/* init the legacy irq controller */
	229	init_i8259a_irqs();
	230
	231	/* init the titan irqs */
	232	titan_init_irq();
	233	}
	234
	235	void
2f116cbf	236	titan_dispatch_irqs(u64 mask)
1da177e4 LT	237	{
	238	unsigned long vector;
	239
	240	/*
	241	* Mask down to those interrupts which are enable on this processor
	242	*/
	243	mask &= titan_cpu_irq_affinity[smp_processor_id()];
	244
	245	/*
	246	* Dispatch all requested interrupts
	247	*/
	248	while (mask) {
	249	/* convert to SRM vector... priority is <63> -> <0> */
88ed39b0	250	vector = 63 - __kernel_ctlz(mask);
1da177e4 LT	251	mask &= ~(1UL << vector); /* clear it out */
	252	vector = 0x900 + (vector << 4); /* convert to SRM vector */
	253
	254	/* dispatch it */
7ca56053	255	alpha_mv.device_interrupt(vector);
1da177e4 LT	256	}
	257	}
	258
	259	\f
	260	/*
	261	* Titan Family
	262	*/
f6901e63 JE	263	static void __init
	264	titan_request_irq(unsigned int irq, irq_handler_t handler,
	265	unsigned long irqflags, const char *devname,
	266	void *dev_id)
	267	{
	268	int err;
	269	err = request_irq(irq, handler, irqflags, devname, dev_id);
	270	if (err) {
	271	printk("titan_request_irq for IRQ %d returned %d; ignoring\n",
	272	irq, err);
	273	}
	274	}
	275
1da177e4 LT	276	static void __init
	277	titan_late_init(void)
	278	{
	279	/*
	280	* Enable the system error interrupts. These interrupts are
	281	* all reported to the kernel as machine checks, so the handler
	282	* is a nop so it can be called to count the individual events.
	283	*/
e74e2592	284	titan_request_irq(63+16, titan_intr_nop, 0,
1da177e4	285	"CChip Error", NULL);
e74e2592	286	titan_request_irq(62+16, titan_intr_nop, 0,
1da177e4	287	"PChip 0 H_Error", NULL);
e74e2592	288	titan_request_irq(61+16, titan_intr_nop, 0,
1da177e4	289	"PChip 1 H_Error", NULL);
e74e2592	290	titan_request_irq(60+16, titan_intr_nop, 0,
1da177e4	291	"PChip 0 C_Error", NULL);
e74e2592	292	titan_request_irq(59+16, titan_intr_nop, 0,
1da177e4 LT	293	"PChip 1 C_Error", NULL);
	294
	295	/*
	296	* Register our error handlers.
	297	*/
	298	titan_register_error_handlers();
	299
	300	/*
	301	* Check if the console left us any error logs.
	302	*/
	303	cdl_check_console_data_log();
	304
	305	}
	306
f8d6c8d9	307	static int
d5341942	308	titan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1da177e4 LT	309	{
	310	u8 intline;
	311	int irq;
	312
	313	/* Get the current intline. */
	314	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
	315	irq = intline;
	316
	317	/* Is it explicitly routed through ISA? */
	318	if ((irq & 0xF0) == 0xE0)
	319	return irq;
	320
	321	/* Offset by 16 to make room for ISA interrupts 0 - 15. */
	322	return irq + 16;
	323	}
	324
	325	static void __init
	326	titan_init_pci(void)
	327	{
	328	/*
	329	* This isn't really the right place, but there's some init
	330	* that needs to be done after everything is basically up.
	331	*/
	332	titan_late_init();
	333
151d16d5 BH	334	/* Indicate that we trust the console to configure things properly */
151d16d5 BH	335	pci_set_flags(PCI_PROBE_ONLY);
1da177e4 LT	336	common_init_pci();
1da177e4 LT	337	SMC669_Init(0);
1da177e4	338	locate_and_init_vga(NULL);
1da177e4 LT	339	}
	340
	341	\f
	342	/*
	343	* Privateer
	344	*/
	345	static void __init
	346	privateer_init_pci(void)
	347	{
	348	/*
	349	* Hook a couple of extra err interrupts that the
	350	* common titan code won't.
	351	*/
e74e2592	352	titan_request_irq(53+16, titan_intr_nop, 0,
1da177e4	353	"NMI", NULL);
e74e2592	354	titan_request_irq(50+16, titan_intr_nop, 0,
1da177e4 LT	355	"Temperature Warning", NULL);
	356
	357	/*
	358	* Finish with the common version.
	359	*/
	360	return titan_init_pci();
	361	}
	362
	363	\f
	364	/*
	365	* The System Vectors.
	366	*/
	367	struct alpha_machine_vector titan_mv __initmv = {
	368	.vector_name = "TITAN",
	369	DO_EV6_MMU,
	370	DO_DEFAULT_RTC,
	371	DO_TITAN_IO,
	372	.machine_check = titan_machine_check,
	373	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
	374	.min_io_address = DEFAULT_IO_BASE,
	375	.min_mem_address = DEFAULT_MEM_BASE,
	376	.pci_dac_offset = TITAN_DAC_OFFSET,
	377
	378	.nr_irqs = 80, /* 64 + 16 */
	379	/* device_interrupt will be filled in by titan_init_irq */
	380
	381	.agp_info = titan_agp_info,
	382
	383	.init_arch = titan_init_arch,
	384	.init_irq = titan_legacy_init_irq,
	385	.init_rtc = common_init_rtc,
	386	.init_pci = titan_init_pci,
	387
	388	.kill_arch = titan_kill_arch,
	389	.pci_map_irq = titan_map_irq,
	390	.pci_swizzle = common_swizzle,
	391	};
	392	ALIAS_MV(titan)
	393
	394	struct alpha_machine_vector privateer_mv __initmv = {
	395	.vector_name = "PRIVATEER",
	396	DO_EV6_MMU,
	397	DO_DEFAULT_RTC,
	398	DO_TITAN_IO,
	399	.machine_check = privateer_machine_check,
	400	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
	401	.min_io_address = DEFAULT_IO_BASE,
	402	.min_mem_address = DEFAULT_MEM_BASE,
	403	.pci_dac_offset = TITAN_DAC_OFFSET,
	404
	405	.nr_irqs = 80, /* 64 + 16 */
	406	/* device_interrupt will be filled in by titan_init_irq */
	407
	408	.agp_info = titan_agp_info,
	409
	410	.init_arch = titan_init_arch,
	411	.init_irq = titan_legacy_init_irq,
	412	.init_rtc = common_init_rtc,
	413	.init_pci = privateer_init_pci,
	414
	415	.kill_arch = titan_kill_arch,
	416	.pci_map_irq = titan_map_irq,
	417	.pci_swizzle = common_swizzle,
	418	};
419	/* No alpha_mv alias for privateer since we compile it
420	in unconditionally with titan; setup_arch knows how to cope. */