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Commit | Line | Data |
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cfdbc2e1 VG |
1 | # |
2 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | # | |
4 | # This program is free software; you can redistribute it and/or modify | |
5 | # it under the terms of the GNU General Public License version 2 as | |
6 | # published by the Free Software Foundation. | |
7 | # | |
8 | ||
9 | config ARC | |
10 | def_bool y | |
2a440168 | 11 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
f06d19e4 | 12 | select BUILDTIME_EXTABLE_SORT |
d7f8a085 | 13 | select COMMON_CLK |
4adeefe1 | 14 | select CLONE_BACKWARDS |
cfdbc2e1 VG |
15 | select GENERIC_ATOMIC64 |
16 | select GENERIC_CLOCKEVENTS | |
17 | select GENERIC_FIND_FIRST_BIT | |
18 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
19 | select GENERIC_IRQ_SHOW | |
c1678ffc | 20 | select GENERIC_PCI_IOMAP |
cfdbc2e1 VG |
21 | select GENERIC_PENDING_IRQ if SMP |
22 | select GENERIC_SMP_IDLE_THREAD | |
f46121bd | 23 | select HAVE_ARCH_KGDB |
547f1125 | 24 | select HAVE_ARCH_TRACEHOOK |
5e057429 | 25 | select HAVE_FUTEX_CMPXCHG |
4368902b | 26 | select HAVE_IOREMAP_PROT |
4d86dfbb VG |
27 | select HAVE_KPROBES |
28 | select HAVE_KRETPROBES | |
c121c506 | 29 | select HAVE_MEMBLOCK |
854a0d95 | 30 | select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND |
769bc1fd | 31 | select HAVE_OPROFILE |
9c57564e | 32 | select HAVE_PERF_EVENTS |
999159a5 | 33 | select IRQ_DOMAIN |
cfdbc2e1 | 34 | select MODULES_USE_ELF_RELA |
c121c506 | 35 | select NO_BOOTMEM |
999159a5 VG |
36 | select OF |
37 | select OF_EARLY_FLATTREE | |
1b10cb21 | 38 | select OF_RESERVED_MEM |
9c57564e | 39 | select PERF_USE_VMALLOC |
d1a1dc0b | 40 | select HAVE_DEBUG_STACKOVERFLOW |
32ed9a0e | 41 | select HAVE_GENERIC_DMA_COHERENT |
cfdbc2e1 | 42 | |
c1678ffc JP |
43 | config MIGHT_HAVE_PCI |
44 | bool | |
45 | ||
0dafafc3 VG |
46 | config TRACE_IRQFLAGS_SUPPORT |
47 | def_bool y | |
48 | ||
49 | config LOCKDEP_SUPPORT | |
50 | def_bool y | |
51 | ||
cfdbc2e1 VG |
52 | config SCHED_OMIT_FRAME_POINTER |
53 | def_bool y | |
54 | ||
55 | config GENERIC_CSUM | |
56 | def_bool y | |
57 | ||
58 | config RWSEM_GENERIC_SPINLOCK | |
59 | def_bool y | |
60 | ||
26f9d5fd VG |
61 | config ARCH_DISCONTIGMEM_ENABLE |
62 | def_bool y | |
63 | ||
cfdbc2e1 VG |
64 | config ARCH_FLATMEM_ENABLE |
65 | def_bool y | |
66 | ||
67 | config MMU | |
68 | def_bool y | |
69 | ||
ce816fa8 | 70 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
71 | def_bool y |
72 | ||
73 | config GENERIC_CALIBRATE_DELAY | |
74 | def_bool y | |
75 | ||
76 | config GENERIC_HWEIGHT | |
77 | def_bool y | |
78 | ||
44c8bb91 VG |
79 | config STACKTRACE_SUPPORT |
80 | def_bool y | |
81 | select STACKTRACE | |
82 | ||
fe6c1b86 VG |
83 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
84 | def_bool y | |
85 | depends on ARC_MMU_V4 | |
86 | ||
cfdbc2e1 VG |
87 | source "init/Kconfig" |
88 | source "kernel/Kconfig.freezer" | |
89 | ||
90 | menu "ARC Architecture Configuration" | |
91 | ||
93ad700d | 92 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 93 | |
fd155792 | 94 | source "arch/arc/plat-sim/Kconfig" |
072eb693 | 95 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 96 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 97 | #New platform adds here |
93ad700d | 98 | |
53d98958 | 99 | endmenu |
cfdbc2e1 | 100 | |
1f6ccfff VG |
101 | choice |
102 | prompt "ARC Instruction Set" | |
103 | default ISA_ARCOMPACT | |
104 | ||
105 | config ISA_ARCOMPACT | |
106 | bool "ARCompact ISA" | |
107 | help | |
108 | The original ARC ISA of ARC600/700 cores | |
109 | ||
65bfbcdf VG |
110 | config ISA_ARCV2 |
111 | bool "ARC ISA v2" | |
112 | help | |
113 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
114 | |
115 | endchoice | |
116 | ||
cfdbc2e1 VG |
117 | menu "ARC CPU Configuration" |
118 | ||
119 | choice | |
120 | prompt "ARC Core" | |
1f6ccfff VG |
121 | default ARC_CPU_770 if ISA_ARCOMPACT |
122 | default ARC_CPU_HS if ISA_ARCV2 | |
123 | ||
124 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
125 | |
126 | config ARC_CPU_750D | |
127 | bool "ARC750D" | |
14a0abfc | 128 | select ARC_CANT_LLSC |
cfdbc2e1 VG |
129 | help |
130 | Support for ARC750 core | |
131 | ||
132 | config ARC_CPU_770 | |
133 | bool "ARC770" | |
742f8af6 | 134 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
135 | help |
136 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
137 | This core has a bunch of cool new features: | |
138 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
139 | Shared Address Spaces (for sharing TLB entires in MMU) | |
140 | -Caches: New Prog Model, Region Flush | |
141 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
142 | ||
1f6ccfff VG |
143 | endif #ISA_ARCOMPACT |
144 | ||
145 | config ARC_CPU_HS | |
146 | bool "ARC-HS" | |
147 | depends on ISA_ARCV2 | |
148 | help | |
149 | Support for ARC HS38x Cores based on ARCv2 ISA | |
150 | The notable features are: | |
151 | - SMP configurations of upto 4 core with coherency | |
152 | - Optional L2 Cache and IO-Coherency | |
153 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
154 | auto stack switch, auto regfile save/restore) | |
155 | - MMUv4 (PIPT dcache, Huge Pages) | |
156 | - Instructions for | |
157 | * 64bit load/store: LDD, STD | |
158 | * Hardware assisted divide/remainder: DIV, REM | |
159 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
160 | * IRQ enable/disable: CLRI, SETI | |
161 | * pop count: FFS, FLS | |
162 | * SETcc, BMSKN, XBFU... | |
163 | ||
cfdbc2e1 VG |
164 | endchoice |
165 | ||
166 | config CPU_BIG_ENDIAN | |
167 | bool "Enable Big Endian Mode" | |
168 | default n | |
169 | help | |
170 | Build kernel for Big Endian Mode of ARC CPU | |
171 | ||
41195d23 | 172 | config SMP |
82fea5a1 | 173 | bool "Symmetric Multi-Processing" |
41195d23 | 174 | default n |
82fea5a1 VG |
175 | select ARC_HAS_COH_CACHES if ISA_ARCV2 |
176 | select ARC_MCIP if ISA_ARCV2 | |
41195d23 | 177 | help |
82fea5a1 | 178 | This enables support for systems with more than one CPU. |
41195d23 VG |
179 | |
180 | if SMP | |
181 | ||
182 | config ARC_HAS_COH_CACHES | |
183 | def_bool n | |
184 | ||
41195d23 VG |
185 | config ARC_HAS_REENTRANT_IRQ_LV2 |
186 | def_bool n | |
187 | ||
82fea5a1 VG |
188 | config ARC_MCIP |
189 | bool "ARConnect Multicore IP (MCIP) Support " | |
190 | depends on ISA_ARCV2 | |
191 | help | |
192 | This IP block enables SMP in ARC-HS38 cores. | |
193 | It provides for cross-core interrupts, multi-core debug | |
194 | hardware semaphores, shared memory,.... | |
41195d23 VG |
195 | |
196 | config NR_CPUS | |
3aa4f80e NC |
197 | int "Maximum number of CPUs (2-4096)" |
198 | range 2 4096 | |
82fea5a1 VG |
199 | default "4" |
200 | ||
3971cdc2 VG |
201 | config ARC_SMP_HALT_ON_RESET |
202 | bool "Enable Halt-on-reset boot mode" | |
203 | default y if ARC_UBOOT_SUPPORT | |
204 | help | |
205 | In SMP configuration cores can be configured as Halt-on-reset | |
206 | or they could all start at same time. For Halt-on-reset, non | |
207 | masters are parked until Master kicks them so they can start of | |
208 | at designated entry point. For other case, all jump to common | |
209 | entry point and spin wait for Master's signal. | |
210 | ||
82fea5a1 | 211 | endif #SMP |
41195d23 | 212 | |
cfdbc2e1 VG |
213 | menuconfig ARC_CACHE |
214 | bool "Enable Cache Support" | |
215 | default y | |
41195d23 VG |
216 | # if SMP, cache enabled ONLY if ARC implementation has cache coherency |
217 | depends on !SMP || ARC_HAS_COH_CACHES | |
cfdbc2e1 VG |
218 | |
219 | if ARC_CACHE | |
220 | ||
221 | config ARC_CACHE_LINE_SHIFT | |
222 | int "Cache Line Length (as power of 2)" | |
223 | range 5 7 | |
224 | default "6" | |
225 | help | |
226 | Starting with ARC700 4.9, Cache line length is configurable, | |
227 | This option specifies "N", with Line-len = 2 power N | |
228 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
229 | Linux only supports same line lengths for I and D caches. | |
230 | ||
231 | config ARC_HAS_ICACHE | |
232 | bool "Use Instruction Cache" | |
233 | default y | |
234 | ||
235 | config ARC_HAS_DCACHE | |
236 | bool "Use Data Cache" | |
237 | default y | |
238 | ||
239 | config ARC_CACHE_PAGES | |
240 | bool "Per Page Cache Control" | |
241 | default y | |
242 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
243 | help | |
244 | This can be used to over-ride the global I/D Cache Enable on a | |
245 | per-page basis (but only for pages accessed via MMU such as | |
246 | Kernel Virtual address or User Virtual Address) | |
247 | TLB entries have a per-page Cache Enable Bit. | |
248 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
249 | Global DISABLE + Per Page ENABLE won't work | |
250 | ||
4102b533 VG |
251 | config ARC_CACHE_VIPT_ALIASING |
252 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 253 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 VG |
254 | default n |
255 | ||
cfdbc2e1 VG |
256 | endif #ARC_CACHE |
257 | ||
8b5850f8 VG |
258 | config ARC_HAS_ICCM |
259 | bool "Use ICCM" | |
260 | help | |
261 | Single Cycle RAMS to store Fast Path Code | |
262 | default n | |
263 | ||
264 | config ARC_ICCM_SZ | |
265 | int "ICCM Size in KB" | |
266 | default "64" | |
267 | depends on ARC_HAS_ICCM | |
268 | ||
269 | config ARC_HAS_DCCM | |
270 | bool "Use DCCM" | |
271 | help | |
272 | Single Cycle RAMS to store Fast Path Data | |
273 | default n | |
274 | ||
275 | config ARC_DCCM_SZ | |
276 | int "DCCM Size in KB" | |
277 | default "64" | |
278 | depends on ARC_HAS_DCCM | |
279 | ||
280 | config ARC_DCCM_BASE | |
281 | hex "DCCM map address" | |
282 | default "0xA0000000" | |
283 | depends on ARC_HAS_DCCM | |
284 | ||
cfdbc2e1 | 285 | choice |
1f6ccfff | 286 | prompt "MMU Version" |
cfdbc2e1 VG |
287 | default ARC_MMU_V3 if ARC_CPU_770 |
288 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 289 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 | 290 | |
c583ee4f VG |
291 | if ISA_ARCOMPACT |
292 | ||
cfdbc2e1 VG |
293 | config ARC_MMU_V1 |
294 | bool "MMU v1" | |
295 | help | |
296 | Orig ARC700 MMU | |
297 | ||
298 | config ARC_MMU_V2 | |
299 | bool "MMU v2" | |
300 | help | |
301 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio | |
302 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. | |
303 | ||
304 | config ARC_MMU_V3 | |
305 | bool "MMU v3" | |
306 | depends on ARC_CPU_770 | |
307 | help | |
308 | Introduced with ARC700 4.10: New Features | |
309 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
310 | Shared Address Spaces (SASID) | |
311 | ||
c583ee4f VG |
312 | endif |
313 | ||
d7a512bf VG |
314 | config ARC_MMU_V4 |
315 | bool "MMU v4" | |
316 | depends on ISA_ARCV2 | |
317 | ||
cfdbc2e1 VG |
318 | endchoice |
319 | ||
320 | ||
321 | choice | |
322 | prompt "MMU Page Size" | |
323 | default ARC_PAGE_SIZE_8K | |
324 | ||
325 | config ARC_PAGE_SIZE_8K | |
326 | bool "8KB" | |
327 | help | |
328 | Choose between 8k vs 16k | |
329 | ||
330 | config ARC_PAGE_SIZE_16K | |
331 | bool "16KB" | |
450ed0db | 332 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
333 | |
334 | config ARC_PAGE_SIZE_4K | |
335 | bool "4KB" | |
450ed0db | 336 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
337 | |
338 | endchoice | |
339 | ||
37eda9df VG |
340 | choice |
341 | prompt "MMU Super Page Size" | |
342 | depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE | |
343 | default ARC_HUGEPAGE_2M | |
344 | ||
345 | config ARC_HUGEPAGE_2M | |
346 | bool "2MB" | |
347 | ||
348 | config ARC_HUGEPAGE_16M | |
349 | bool "16MB" | |
350 | ||
351 | endchoice | |
352 | ||
26f9d5fd VG |
353 | config NODES_SHIFT |
354 | int "Maximum NUMA Nodes (as a power of 2)" | |
355 | default "1" if !DISCONTIGMEM | |
356 | default "2" if DISCONTIGMEM | |
357 | depends on NEED_MULTIPLE_NODES | |
358 | ---help--- | |
359 | Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory | |
360 | zones. | |
361 | ||
1f6ccfff VG |
362 | if ISA_ARCOMPACT |
363 | ||
4788a594 VG |
364 | config ARC_COMPACT_IRQ_LEVELS |
365 | bool "ARCompact IRQ Priorities: High(2)/Low(1)" | |
366 | default n | |
367 | # Timer HAS to be high priority, for any other high priority config | |
368 | select ARC_IRQ3_LV2 | |
41195d23 VG |
369 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
370 | depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 | |
4788a594 VG |
371 | |
372 | if ARC_COMPACT_IRQ_LEVELS | |
373 | ||
374 | config ARC_IRQ3_LV2 | |
375 | bool | |
376 | ||
377 | config ARC_IRQ5_LV2 | |
378 | bool | |
379 | ||
380 | config ARC_IRQ6_LV2 | |
381 | bool | |
382 | ||
1f6ccfff | 383 | endif #ARC_COMPACT_IRQ_LEVELS |
4788a594 | 384 | |
cfdbc2e1 VG |
385 | config ARC_FPU_SAVE_RESTORE |
386 | bool "Enable FPU state persistence across context switch" | |
387 | default n | |
388 | help | |
389 | Double Precision Floating Point unit had dedictaed regs which | |
390 | need to be saved/restored across context-switch. | |
391 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
392 | hardware pieces to allow software to conditionally save/restore, | |
393 | based on actual usage of FPU by a task. Thus our implemn does | |
394 | this for all tasks in system. | |
395 | ||
1f6ccfff VG |
396 | endif #ISA_ARCOMPACT |
397 | ||
fbf8e13d VG |
398 | config ARC_CANT_LLSC |
399 | def_bool n | |
400 | ||
cfdbc2e1 VG |
401 | config ARC_HAS_LLSC |
402 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
403 | default y | |
14a0abfc | 404 | depends on !ARC_CANT_LLSC |
cfdbc2e1 | 405 | |
e78fdfef VG |
406 | config ARC_STAR_9000923308 |
407 | bool "Workaround for llock/scond livelock" | |
b31ac426 | 408 | default n |
e78fdfef VG |
409 | depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC |
410 | ||
cfdbc2e1 VG |
411 | config ARC_HAS_SWAPE |
412 | bool "Insn: SWAPE (endian-swap)" | |
413 | default y | |
cfdbc2e1 | 414 | |
1f6ccfff VG |
415 | if ISA_ARCV2 |
416 | ||
417 | config ARC_HAS_LL64 | |
418 | bool "Insn: 64bit LDD/STD" | |
419 | help | |
420 | Enable gcc to generate 64-bit load/store instructions | |
421 | ISA mandates even/odd registers to allow encoding of two | |
422 | dest operands with 2 possible source operands. | |
423 | default y | |
424 | ||
d05a76ab AB |
425 | config ARC_HAS_DIV_REM |
426 | bool "Insn: div, divu, rem, remu" | |
427 | default y | |
428 | ||
aa93e8ef VG |
429 | config ARC_HAS_RTC |
430 | bool "Local 64-bit r/o cycle counter" | |
431 | default n | |
432 | depends on !SMP | |
433 | ||
d584f0fb | 434 | config ARC_HAS_GFRC |
72d72880 VG |
435 | bool "SMP synchronized 64-bit cycle counter" |
436 | default y | |
437 | depends on SMP | |
438 | ||
1f6ccfff VG |
439 | config ARC_NUMBER_OF_INTERRUPTS |
440 | int "Number of interrupts" | |
441 | range 8 240 | |
442 | default 32 | |
443 | help | |
444 | This defines the number of interrupts on the ARCv2HS core. | |
445 | It affects the size of vector table. | |
446 | The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable | |
447 | in hardware, it keep things simple for Linux to assume they are always | |
448 | present. | |
449 | ||
450 | endif # ISA_ARCV2 | |
451 | ||
cfdbc2e1 VG |
452 | endmenu # "ARC CPU Configuration" |
453 | ||
cfdbc2e1 VG |
454 | config LINUX_LINK_BASE |
455 | hex "Linux Link Address" | |
456 | default "0x80000000" | |
457 | help | |
458 | ARC700 divides the 32 bit phy address space into two equal halves | |
459 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
460 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
461 | Typically Linux kernel is linked at the start of untransalted addr, | |
462 | hence the default value of 0x8zs. | |
463 | However some customers have peripherals mapped at this addr, so | |
464 | Linux needs to be scooted a bit. | |
465 | If you don't know what the above means, leave this setting alone. | |
ff1c0b6a | 466 | This needs to match memory start address specified in Device Tree |
cfdbc2e1 | 467 | |
45890f6d VG |
468 | config HIGHMEM |
469 | bool "High Memory Support" | |
26f9d5fd | 470 | select DISCONTIGMEM |
45890f6d VG |
471 | help |
472 | With ARC 2G:2G address split, only upper 2G is directly addressable by | |
473 | kernel. Enable this to potentially allow access to rest of 2G and PAE | |
474 | in future | |
475 | ||
5a364c2a VG |
476 | config ARC_HAS_PAE40 |
477 | bool "Support for the 40-bit Physical Address Extension" | |
478 | default n | |
479 | depends on ISA_ARCV2 | |
5a364c2a VG |
480 | help |
481 | Enable access to physical memory beyond 4G, only supported on | |
482 | ARC cores with 40 bit Physical Addressing support | |
483 | ||
484 | config ARCH_PHYS_ADDR_T_64BIT | |
485 | def_bool ARC_HAS_PAE40 | |
486 | ||
487 | config ARCH_DMA_ADDR_T_64BIT | |
488 | bool | |
489 | ||
f2e3d553 VG |
490 | config ARC_PLAT_NEEDS_PHYS_TO_DMA |
491 | bool | |
492 | ||
080c3747 VG |
493 | config ARC_CURR_IN_REG |
494 | bool "Dedicate Register r25 for current_task pointer" | |
495 | default y | |
496 | help | |
497 | This reserved Register R25 to point to Current Task in | |
498 | kernel mode. This saves memory access for each such access | |
499 | ||
2e651ea1 | 500 | |
1736a56f | 501 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 502 | bool "Emulate unaligned memory access (userspace only)" |
1f6ccfff | 503 | default N |
2e651ea1 VG |
504 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
505 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 506 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
507 | help |
508 | This enables misaligned 16 & 32 bit memory access from user space. | |
509 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
510 | potential bugs in code | |
511 | ||
cfdbc2e1 VG |
512 | config HZ |
513 | int "Timer Frequency" | |
514 | default 100 | |
515 | ||
cbe056f7 VG |
516 | config ARC_METAWARE_HLINK |
517 | bool "Support for Metaware debugger assisted Host access" | |
518 | default n | |
519 | help | |
520 | This options allows a Linux userland apps to directly access | |
521 | host file system (open/creat/read/write etc) with help from | |
522 | Metaware Debugger. This can come in handy for Linux-host communication | |
523 | when there is no real usable peripheral such as EMAC. | |
524 | ||
cfdbc2e1 VG |
525 | menuconfig ARC_DBG |
526 | bool "ARC debugging" | |
527 | default y | |
528 | ||
aa6083ed VG |
529 | if ARC_DBG |
530 | ||
854a0d95 VG |
531 | config ARC_DW2_UNWIND |
532 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
533 | default y |
534 | select KALLSYMS | |
535 | help | |
536 | Compiles the kernel with DWARF unwind information and can be used | |
537 | to get stack backtraces. | |
538 | ||
539 | If you say Y here the resulting kernel image will be slightly larger | |
540 | but not slower, and it will give very useful debugging information. | |
541 | If you don't debug the kernel, you can say N, but we may not be able | |
542 | to solve problems without frame unwind information | |
543 | ||
cfdbc2e1 VG |
544 | config ARC_DBG_TLB_PARANOIA |
545 | bool "Paranoia Checks in Low Level TLB Handlers" | |
cfdbc2e1 VG |
546 | default n |
547 | ||
548 | config ARC_DBG_TLB_MISS_COUNT | |
549 | bool "Profile TLB Misses" | |
550 | default n | |
551 | select DEBUG_FS | |
cfdbc2e1 VG |
552 | help |
553 | Counts number of I and D TLB Misses and exports them via Debugfs | |
554 | The counters can be cleared via Debugfs as well | |
555 | ||
aa6083ed VG |
556 | endif |
557 | ||
036b2c56 VG |
558 | config ARC_UBOOT_SUPPORT |
559 | bool "Support uboot arg Handling" | |
560 | default n | |
561 | help | |
562 | ARC Linux by default checks for uboot provided args as pointers to | |
563 | external cmdline or DTB. This however breaks in absence of uboot, | |
564 | when booting from Metaware debugger directly, as the registers are | |
565 | not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus | |
566 | registers look like uboot args to kernel which then chokes. | |
567 | So only enable the uboot arg checking/processing if users are sure | |
568 | of uboot being in play. | |
569 | ||
999159a5 VG |
570 | config ARC_BUILTIN_DTB_NAME |
571 | string "Built in DTB" | |
572 | help | |
573 | Set the name of the DTB to embed in the vmlinux binary | |
574 | Leaving it blank selects the minimal "skeleton" dtb | |
575 | ||
cfdbc2e1 VG |
576 | source "kernel/Kconfig.preempt" |
577 | ||
5628832f VG |
578 | menu "Executable file formats" |
579 | source "fs/Kconfig.binfmt" | |
580 | endmenu | |
581 | ||
cfdbc2e1 VG |
582 | endmenu # "ARC Architecture Configuration" |
583 | ||
584 | source "mm/Kconfig" | |
37eda9df VG |
585 | |
586 | config FORCE_MAX_ZONEORDER | |
587 | int "Maximum zone order" | |
588 | default "12" if ARC_HUGEPAGE_16M | |
589 | default "11" | |
590 | ||
cfdbc2e1 VG |
591 | source "net/Kconfig" |
592 | source "drivers/Kconfig" | |
c1678ffc JP |
593 | |
594 | menu "Bus Support" | |
595 | ||
596 | config PCI | |
597 | bool "PCI support" if MIGHT_HAVE_PCI | |
598 | help | |
599 | PCI is the name of a bus system, i.e., the way the CPU talks to | |
600 | the other stuff inside your box. Find out if your board/platform | |
601 | has PCI. | |
602 | ||
603 | Note: PCIe support for Synopsys Device will be available only | |
604 | when HAPS DX is configured with PCIe RC bitmap. If you have PCI, | |
605 | say Y, otherwise N. | |
606 | ||
607 | config PCI_SYSCALL | |
608 | def_bool PCI | |
609 | ||
610 | source "drivers/pci/Kconfig" | |
c1678ffc JP |
611 | |
612 | endmenu | |
613 | ||
cfdbc2e1 VG |
614 | source "fs/Kconfig" |
615 | source "arch/arc/Kconfig.debug" | |
616 | source "security/Kconfig" | |
617 | source "crypto/Kconfig" | |
618 | source "lib/Kconfig" | |
996bad6c | 619 | source "kernel/power/Kconfig" |