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Commit | Line | Data |
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cfdbc2e1 VG |
1 | # |
2 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | # | |
4 | # This program is free software; you can redistribute it and/or modify | |
5 | # it under the terms of the GNU General Public License version 2 as | |
6 | # published by the Free Software Foundation. | |
7 | # | |
8 | ||
9 | config ARC | |
10 | def_bool y | |
c4c9a040 | 11 | select ARC_TIMERS |
2a440168 | 12 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
f06d19e4 | 13 | select BUILDTIME_EXTABLE_SORT |
4adeefe1 | 14 | select CLONE_BACKWARDS |
69fbd098 | 15 | select COMMON_CLK |
ce636527 | 16 | select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) |
cfdbc2e1 VG |
17 | select GENERIC_CLOCKEVENTS |
18 | select GENERIC_FIND_FIRST_BIT | |
19 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
20 | select GENERIC_IRQ_SHOW | |
c1678ffc | 21 | select GENERIC_PCI_IOMAP |
cfdbc2e1 VG |
22 | select GENERIC_PENDING_IRQ if SMP |
23 | select GENERIC_SMP_IDLE_THREAD | |
f46121bd | 24 | select HAVE_ARCH_KGDB |
547f1125 | 25 | select HAVE_ARCH_TRACEHOOK |
5e057429 | 26 | select HAVE_FUTEX_CMPXCHG |
4368902b | 27 | select HAVE_IOREMAP_PROT |
4d86dfbb VG |
28 | select HAVE_KPROBES |
29 | select HAVE_KRETPROBES | |
c121c506 | 30 | select HAVE_MEMBLOCK |
854a0d95 | 31 | select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND |
769bc1fd | 32 | select HAVE_OPROFILE |
9c57564e | 33 | select HAVE_PERF_EVENTS |
1b0ccb8a | 34 | select HANDLE_DOMAIN_IRQ |
999159a5 | 35 | select IRQ_DOMAIN |
cfdbc2e1 | 36 | select MODULES_USE_ELF_RELA |
c121c506 | 37 | select NO_BOOTMEM |
999159a5 VG |
38 | select OF |
39 | select OF_EARLY_FLATTREE | |
1b10cb21 | 40 | select OF_RESERVED_MEM |
9c57564e | 41 | select PERF_USE_VMALLOC |
d1a1dc0b | 42 | select HAVE_DEBUG_STACKOVERFLOW |
32ed9a0e | 43 | select HAVE_GENERIC_DMA_COHERENT |
27f3d2a3 DM |
44 | select HAVE_KERNEL_GZIP |
45 | select HAVE_KERNEL_LZMA | |
cfdbc2e1 | 46 | |
c1678ffc JP |
47 | config MIGHT_HAVE_PCI |
48 | bool | |
49 | ||
0dafafc3 VG |
50 | config TRACE_IRQFLAGS_SUPPORT |
51 | def_bool y | |
52 | ||
53 | config LOCKDEP_SUPPORT | |
54 | def_bool y | |
55 | ||
cfdbc2e1 VG |
56 | config SCHED_OMIT_FRAME_POINTER |
57 | def_bool y | |
58 | ||
59 | config GENERIC_CSUM | |
60 | def_bool y | |
61 | ||
62 | config RWSEM_GENERIC_SPINLOCK | |
63 | def_bool y | |
64 | ||
26f9d5fd | 65 | config ARCH_DISCONTIGMEM_ENABLE |
d140b9bf | 66 | def_bool n |
26f9d5fd | 67 | |
cfdbc2e1 VG |
68 | config ARCH_FLATMEM_ENABLE |
69 | def_bool y | |
70 | ||
71 | config MMU | |
72 | def_bool y | |
73 | ||
ce816fa8 | 74 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
75 | def_bool y |
76 | ||
77 | config GENERIC_CALIBRATE_DELAY | |
78 | def_bool y | |
79 | ||
80 | config GENERIC_HWEIGHT | |
81 | def_bool y | |
82 | ||
44c8bb91 VG |
83 | config STACKTRACE_SUPPORT |
84 | def_bool y | |
85 | select STACKTRACE | |
86 | ||
fe6c1b86 VG |
87 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
88 | def_bool y | |
89 | depends on ARC_MMU_V4 | |
90 | ||
cfdbc2e1 VG |
91 | source "init/Kconfig" |
92 | source "kernel/Kconfig.freezer" | |
93 | ||
94 | menu "ARC Architecture Configuration" | |
95 | ||
93ad700d | 96 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 97 | |
fd155792 | 98 | source "arch/arc/plat-sim/Kconfig" |
072eb693 | 99 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 100 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 101 | #New platform adds here |
96665789 | 102 | source "arch/arc/plat-eznps/Kconfig" |
93ad700d | 103 | |
53d98958 | 104 | endmenu |
cfdbc2e1 | 105 | |
1f6ccfff VG |
106 | choice |
107 | prompt "ARC Instruction Set" | |
108 | default ISA_ARCOMPACT | |
109 | ||
110 | config ISA_ARCOMPACT | |
111 | bool "ARCompact ISA" | |
fff7fb0b | 112 | select CPU_NO_EFFICIENT_FFS |
1f6ccfff VG |
113 | help |
114 | The original ARC ISA of ARC600/700 cores | |
115 | ||
65bfbcdf VG |
116 | config ISA_ARCV2 |
117 | bool "ARC ISA v2" | |
c4c9a040 | 118 | select ARC_TIMERS_64BIT |
65bfbcdf VG |
119 | help |
120 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
121 | |
122 | endchoice | |
123 | ||
cfdbc2e1 VG |
124 | menu "ARC CPU Configuration" |
125 | ||
126 | choice | |
127 | prompt "ARC Core" | |
1f6ccfff VG |
128 | default ARC_CPU_770 if ISA_ARCOMPACT |
129 | default ARC_CPU_HS if ISA_ARCV2 | |
130 | ||
131 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
132 | |
133 | config ARC_CPU_750D | |
134 | bool "ARC750D" | |
14a0abfc | 135 | select ARC_CANT_LLSC |
cfdbc2e1 VG |
136 | help |
137 | Support for ARC750 core | |
138 | ||
139 | config ARC_CPU_770 | |
140 | bool "ARC770" | |
742f8af6 | 141 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
142 | help |
143 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
144 | This core has a bunch of cool new features: | |
145 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
146 | Shared Address Spaces (for sharing TLB entires in MMU) | |
147 | -Caches: New Prog Model, Region Flush | |
148 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
149 | ||
1f6ccfff VG |
150 | endif #ISA_ARCOMPACT |
151 | ||
152 | config ARC_CPU_HS | |
153 | bool "ARC-HS" | |
154 | depends on ISA_ARCV2 | |
155 | help | |
156 | Support for ARC HS38x Cores based on ARCv2 ISA | |
157 | The notable features are: | |
158 | - SMP configurations of upto 4 core with coherency | |
159 | - Optional L2 Cache and IO-Coherency | |
160 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
161 | auto stack switch, auto regfile save/restore) | |
162 | - MMUv4 (PIPT dcache, Huge Pages) | |
163 | - Instructions for | |
164 | * 64bit load/store: LDD, STD | |
165 | * Hardware assisted divide/remainder: DIV, REM | |
166 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
167 | * IRQ enable/disable: CLRI, SETI | |
168 | * pop count: FFS, FLS | |
169 | * SETcc, BMSKN, XBFU... | |
170 | ||
cfdbc2e1 VG |
171 | endchoice |
172 | ||
173 | config CPU_BIG_ENDIAN | |
174 | bool "Enable Big Endian Mode" | |
175 | default n | |
176 | help | |
177 | Build kernel for Big Endian Mode of ARC CPU | |
178 | ||
41195d23 | 179 | config SMP |
82fea5a1 | 180 | bool "Symmetric Multi-Processing" |
41195d23 | 181 | default n |
82fea5a1 VG |
182 | select ARC_HAS_COH_CACHES if ISA_ARCV2 |
183 | select ARC_MCIP if ISA_ARCV2 | |
41195d23 | 184 | help |
82fea5a1 | 185 | This enables support for systems with more than one CPU. |
41195d23 VG |
186 | |
187 | if SMP | |
188 | ||
189 | config ARC_HAS_COH_CACHES | |
190 | def_bool n | |
191 | ||
41195d23 | 192 | config NR_CPUS |
3aa4f80e NC |
193 | int "Maximum number of CPUs (2-4096)" |
194 | range 2 4096 | |
82fea5a1 VG |
195 | default "4" |
196 | ||
3971cdc2 VG |
197 | config ARC_SMP_HALT_ON_RESET |
198 | bool "Enable Halt-on-reset boot mode" | |
199 | default y if ARC_UBOOT_SUPPORT | |
200 | help | |
201 | In SMP configuration cores can be configured as Halt-on-reset | |
202 | or they could all start at same time. For Halt-on-reset, non | |
203 | masters are parked until Master kicks them so they can start of | |
204 | at designated entry point. For other case, all jump to common | |
205 | entry point and spin wait for Master's signal. | |
206 | ||
82fea5a1 | 207 | endif #SMP |
41195d23 | 208 | |
3ce0fefc VG |
209 | config ARC_MCIP |
210 | bool "ARConnect Multicore IP (MCIP) Support " | |
211 | depends on ISA_ARCV2 | |
212 | default y if SMP | |
213 | help | |
214 | This IP block enables SMP in ARC-HS38 cores. | |
215 | It provides for cross-core interrupts, multi-core debug | |
216 | hardware semaphores, shared memory,.... | |
217 | ||
cfdbc2e1 VG |
218 | menuconfig ARC_CACHE |
219 | bool "Enable Cache Support" | |
220 | default y | |
41195d23 VG |
221 | # if SMP, cache enabled ONLY if ARC implementation has cache coherency |
222 | depends on !SMP || ARC_HAS_COH_CACHES | |
cfdbc2e1 VG |
223 | |
224 | if ARC_CACHE | |
225 | ||
226 | config ARC_CACHE_LINE_SHIFT | |
227 | int "Cache Line Length (as power of 2)" | |
228 | range 5 7 | |
229 | default "6" | |
230 | help | |
231 | Starting with ARC700 4.9, Cache line length is configurable, | |
232 | This option specifies "N", with Line-len = 2 power N | |
233 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
234 | Linux only supports same line lengths for I and D caches. | |
235 | ||
236 | config ARC_HAS_ICACHE | |
237 | bool "Use Instruction Cache" | |
238 | default y | |
239 | ||
240 | config ARC_HAS_DCACHE | |
241 | bool "Use Data Cache" | |
242 | default y | |
243 | ||
244 | config ARC_CACHE_PAGES | |
245 | bool "Per Page Cache Control" | |
246 | default y | |
247 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
248 | help | |
249 | This can be used to over-ride the global I/D Cache Enable on a | |
250 | per-page basis (but only for pages accessed via MMU such as | |
251 | Kernel Virtual address or User Virtual Address) | |
252 | TLB entries have a per-page Cache Enable Bit. | |
253 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
254 | Global DISABLE + Per Page ENABLE won't work | |
255 | ||
4102b533 VG |
256 | config ARC_CACHE_VIPT_ALIASING |
257 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 258 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 VG |
259 | default n |
260 | ||
cfdbc2e1 VG |
261 | endif #ARC_CACHE |
262 | ||
8b5850f8 VG |
263 | config ARC_HAS_ICCM |
264 | bool "Use ICCM" | |
265 | help | |
266 | Single Cycle RAMS to store Fast Path Code | |
267 | default n | |
268 | ||
269 | config ARC_ICCM_SZ | |
270 | int "ICCM Size in KB" | |
271 | default "64" | |
272 | depends on ARC_HAS_ICCM | |
273 | ||
274 | config ARC_HAS_DCCM | |
275 | bool "Use DCCM" | |
276 | help | |
277 | Single Cycle RAMS to store Fast Path Data | |
278 | default n | |
279 | ||
280 | config ARC_DCCM_SZ | |
281 | int "DCCM Size in KB" | |
282 | default "64" | |
283 | depends on ARC_HAS_DCCM | |
284 | ||
285 | config ARC_DCCM_BASE | |
286 | hex "DCCM map address" | |
287 | default "0xA0000000" | |
288 | depends on ARC_HAS_DCCM | |
289 | ||
cfdbc2e1 | 290 | choice |
1f6ccfff | 291 | prompt "MMU Version" |
cfdbc2e1 VG |
292 | default ARC_MMU_V3 if ARC_CPU_770 |
293 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 294 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 | 295 | |
c583ee4f VG |
296 | if ISA_ARCOMPACT |
297 | ||
cfdbc2e1 VG |
298 | config ARC_MMU_V1 |
299 | bool "MMU v1" | |
300 | help | |
301 | Orig ARC700 MMU | |
302 | ||
303 | config ARC_MMU_V2 | |
304 | bool "MMU v2" | |
305 | help | |
306 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio | |
307 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. | |
308 | ||
309 | config ARC_MMU_V3 | |
310 | bool "MMU v3" | |
311 | depends on ARC_CPU_770 | |
312 | help | |
313 | Introduced with ARC700 4.10: New Features | |
314 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
315 | Shared Address Spaces (SASID) | |
316 | ||
c583ee4f VG |
317 | endif |
318 | ||
d7a512bf VG |
319 | config ARC_MMU_V4 |
320 | bool "MMU v4" | |
321 | depends on ISA_ARCV2 | |
322 | ||
cfdbc2e1 VG |
323 | endchoice |
324 | ||
325 | ||
326 | choice | |
327 | prompt "MMU Page Size" | |
328 | default ARC_PAGE_SIZE_8K | |
329 | ||
330 | config ARC_PAGE_SIZE_8K | |
331 | bool "8KB" | |
332 | help | |
333 | Choose between 8k vs 16k | |
334 | ||
335 | config ARC_PAGE_SIZE_16K | |
336 | bool "16KB" | |
450ed0db | 337 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
338 | |
339 | config ARC_PAGE_SIZE_4K | |
340 | bool "4KB" | |
450ed0db | 341 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
342 | |
343 | endchoice | |
344 | ||
37eda9df VG |
345 | choice |
346 | prompt "MMU Super Page Size" | |
347 | depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE | |
348 | default ARC_HUGEPAGE_2M | |
349 | ||
350 | config ARC_HUGEPAGE_2M | |
351 | bool "2MB" | |
352 | ||
353 | config ARC_HUGEPAGE_16M | |
354 | bool "16MB" | |
355 | ||
356 | endchoice | |
357 | ||
26f9d5fd VG |
358 | config NODES_SHIFT |
359 | int "Maximum NUMA Nodes (as a power of 2)" | |
3528f84f NC |
360 | default "0" if !DISCONTIGMEM |
361 | default "1" if DISCONTIGMEM | |
26f9d5fd VG |
362 | depends on NEED_MULTIPLE_NODES |
363 | ---help--- | |
364 | Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory | |
365 | zones. | |
366 | ||
1f6ccfff VG |
367 | if ISA_ARCOMPACT |
368 | ||
4788a594 | 369 | config ARC_COMPACT_IRQ_LEVELS |
60f2b4b8 | 370 | bool "Setup Timer IRQ as high Priority" |
4788a594 | 371 | default n |
41195d23 | 372 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
60f2b4b8 | 373 | depends on !SMP |
4788a594 | 374 | |
cfdbc2e1 VG |
375 | config ARC_FPU_SAVE_RESTORE |
376 | bool "Enable FPU state persistence across context switch" | |
377 | default n | |
378 | help | |
379 | Double Precision Floating Point unit had dedictaed regs which | |
380 | need to be saved/restored across context-switch. | |
381 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
382 | hardware pieces to allow software to conditionally save/restore, | |
383 | based on actual usage of FPU by a task. Thus our implemn does | |
384 | this for all tasks in system. | |
385 | ||
1f6ccfff VG |
386 | endif #ISA_ARCOMPACT |
387 | ||
fbf8e13d VG |
388 | config ARC_CANT_LLSC |
389 | def_bool n | |
390 | ||
cfdbc2e1 VG |
391 | config ARC_HAS_LLSC |
392 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
393 | default y | |
14a0abfc | 394 | depends on !ARC_CANT_LLSC |
cfdbc2e1 VG |
395 | |
396 | config ARC_HAS_SWAPE | |
397 | bool "Insn: SWAPE (endian-swap)" | |
398 | default y | |
cfdbc2e1 | 399 | |
1f6ccfff VG |
400 | if ISA_ARCV2 |
401 | ||
402 | config ARC_HAS_LL64 | |
403 | bool "Insn: 64bit LDD/STD" | |
404 | help | |
405 | Enable gcc to generate 64-bit load/store instructions | |
406 | ISA mandates even/odd registers to allow encoding of two | |
407 | dest operands with 2 possible source operands. | |
408 | default y | |
409 | ||
d05a76ab AB |
410 | config ARC_HAS_DIV_REM |
411 | bool "Insn: div, divu, rem, remu" | |
412 | default y | |
413 | ||
1f6ccfff VG |
414 | config ARC_NUMBER_OF_INTERRUPTS |
415 | int "Number of interrupts" | |
416 | range 8 240 | |
417 | default 32 | |
418 | help | |
419 | This defines the number of interrupts on the ARCv2HS core. | |
420 | It affects the size of vector table. | |
421 | The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable | |
422 | in hardware, it keep things simple for Linux to assume they are always | |
423 | present. | |
424 | ||
425 | endif # ISA_ARCV2 | |
426 | ||
cfdbc2e1 VG |
427 | endmenu # "ARC CPU Configuration" |
428 | ||
cfdbc2e1 VG |
429 | config LINUX_LINK_BASE |
430 | hex "Linux Link Address" | |
431 | default "0x80000000" | |
432 | help | |
433 | ARC700 divides the 32 bit phy address space into two equal halves | |
434 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
435 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
436 | Typically Linux kernel is linked at the start of untransalted addr, | |
437 | hence the default value of 0x8zs. | |
438 | However some customers have peripherals mapped at this addr, so | |
439 | Linux needs to be scooted a bit. | |
440 | If you don't know what the above means, leave this setting alone. | |
ff1c0b6a | 441 | This needs to match memory start address specified in Device Tree |
cfdbc2e1 | 442 | |
45890f6d VG |
443 | config HIGHMEM |
444 | bool "High Memory Support" | |
d140b9bf | 445 | select ARCH_DISCONTIGMEM_ENABLE |
45890f6d VG |
446 | help |
447 | With ARC 2G:2G address split, only upper 2G is directly addressable by | |
448 | kernel. Enable this to potentially allow access to rest of 2G and PAE | |
449 | in future | |
450 | ||
5a364c2a VG |
451 | config ARC_HAS_PAE40 |
452 | bool "Support for the 40-bit Physical Address Extension" | |
453 | default n | |
454 | depends on ISA_ARCV2 | |
5a364c2a VG |
455 | help |
456 | Enable access to physical memory beyond 4G, only supported on | |
457 | ARC cores with 40 bit Physical Addressing support | |
458 | ||
459 | config ARCH_PHYS_ADDR_T_64BIT | |
460 | def_bool ARC_HAS_PAE40 | |
461 | ||
462 | config ARCH_DMA_ADDR_T_64BIT | |
463 | bool | |
464 | ||
f2e3d553 VG |
465 | config ARC_PLAT_NEEDS_PHYS_TO_DMA |
466 | bool | |
467 | ||
15ca68a9 NC |
468 | config ARC_KVADDR_SIZE |
469 | int "Kernel Virtaul Address Space size (MB)" | |
470 | range 0 512 | |
471 | default "256" | |
472 | help | |
473 | The kernel address space is carved out of 256MB of translated address | |
474 | space for catering to vmalloc, modules, pkmap, fixmap. This however may | |
475 | not suffice vmalloc requirements of a 4K CPU EZChip system. So allow | |
476 | this to be stretched to 512 MB (by extending into the reserved | |
477 | kernel-user gutter) | |
478 | ||
080c3747 VG |
479 | config ARC_CURR_IN_REG |
480 | bool "Dedicate Register r25 for current_task pointer" | |
481 | default y | |
482 | help | |
483 | This reserved Register R25 to point to Current Task in | |
484 | kernel mode. This saves memory access for each such access | |
485 | ||
2e651ea1 | 486 | |
1736a56f | 487 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 488 | bool "Emulate unaligned memory access (userspace only)" |
1f6ccfff | 489 | default N |
2e651ea1 VG |
490 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
491 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 492 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
493 | help |
494 | This enables misaligned 16 & 32 bit memory access from user space. | |
495 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
496 | potential bugs in code | |
497 | ||
cfdbc2e1 VG |
498 | config HZ |
499 | int "Timer Frequency" | |
500 | default 100 | |
501 | ||
cbe056f7 VG |
502 | config ARC_METAWARE_HLINK |
503 | bool "Support for Metaware debugger assisted Host access" | |
504 | default n | |
505 | help | |
506 | This options allows a Linux userland apps to directly access | |
507 | host file system (open/creat/read/write etc) with help from | |
508 | Metaware Debugger. This can come in handy for Linux-host communication | |
509 | when there is no real usable peripheral such as EMAC. | |
510 | ||
cfdbc2e1 VG |
511 | menuconfig ARC_DBG |
512 | bool "ARC debugging" | |
513 | default y | |
514 | ||
aa6083ed VG |
515 | if ARC_DBG |
516 | ||
854a0d95 VG |
517 | config ARC_DW2_UNWIND |
518 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
519 | default y |
520 | select KALLSYMS | |
521 | help | |
522 | Compiles the kernel with DWARF unwind information and can be used | |
523 | to get stack backtraces. | |
524 | ||
525 | If you say Y here the resulting kernel image will be slightly larger | |
526 | but not slower, and it will give very useful debugging information. | |
527 | If you don't debug the kernel, you can say N, but we may not be able | |
528 | to solve problems without frame unwind information | |
529 | ||
cfdbc2e1 VG |
530 | config ARC_DBG_TLB_PARANOIA |
531 | bool "Paranoia Checks in Low Level TLB Handlers" | |
cfdbc2e1 VG |
532 | default n |
533 | ||
aa6083ed VG |
534 | endif |
535 | ||
036b2c56 VG |
536 | config ARC_UBOOT_SUPPORT |
537 | bool "Support uboot arg Handling" | |
538 | default n | |
539 | help | |
540 | ARC Linux by default checks for uboot provided args as pointers to | |
541 | external cmdline or DTB. This however breaks in absence of uboot, | |
542 | when booting from Metaware debugger directly, as the registers are | |
543 | not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus | |
544 | registers look like uboot args to kernel which then chokes. | |
545 | So only enable the uboot arg checking/processing if users are sure | |
546 | of uboot being in play. | |
547 | ||
999159a5 VG |
548 | config ARC_BUILTIN_DTB_NAME |
549 | string "Built in DTB" | |
550 | help | |
551 | Set the name of the DTB to embed in the vmlinux binary | |
552 | Leaving it blank selects the minimal "skeleton" dtb | |
553 | ||
cfdbc2e1 VG |
554 | source "kernel/Kconfig.preempt" |
555 | ||
5628832f VG |
556 | menu "Executable file formats" |
557 | source "fs/Kconfig.binfmt" | |
558 | endmenu | |
559 | ||
cfdbc2e1 VG |
560 | endmenu # "ARC Architecture Configuration" |
561 | ||
562 | source "mm/Kconfig" | |
37eda9df VG |
563 | |
564 | config FORCE_MAX_ZONEORDER | |
565 | int "Maximum zone order" | |
566 | default "12" if ARC_HUGEPAGE_16M | |
567 | default "11" | |
568 | ||
cfdbc2e1 VG |
569 | source "net/Kconfig" |
570 | source "drivers/Kconfig" | |
c1678ffc JP |
571 | |
572 | menu "Bus Support" | |
573 | ||
574 | config PCI | |
575 | bool "PCI support" if MIGHT_HAVE_PCI | |
576 | help | |
577 | PCI is the name of a bus system, i.e., the way the CPU talks to | |
578 | the other stuff inside your box. Find out if your board/platform | |
579 | has PCI. | |
580 | ||
581 | Note: PCIe support for Synopsys Device will be available only | |
582 | when HAPS DX is configured with PCIe RC bitmap. If you have PCI, | |
583 | say Y, otherwise N. | |
584 | ||
585 | config PCI_SYSCALL | |
586 | def_bool PCI | |
587 | ||
588 | source "drivers/pci/Kconfig" | |
c1678ffc JP |
589 | |
590 | endmenu | |
591 | ||
cfdbc2e1 VG |
592 | source "fs/Kconfig" |
593 | source "arch/arc/Kconfig.debug" | |
594 | source "security/Kconfig" | |
595 | source "crypto/Kconfig" | |
596 | source "lib/Kconfig" | |
996bad6c | 597 | source "kernel/power/Kconfig" |