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cfdbc2e1 VG |
1 | # |
2 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | # | |
4 | # This program is free software; you can redistribute it and/or modify | |
5 | # it under the terms of the GNU General Public License version 2 as | |
6 | # published by the Free Software Foundation. | |
7 | # | |
8 | ||
9 | config ARC | |
10 | def_bool y | |
f06d19e4 | 11 | select BUILDTIME_EXTABLE_SORT |
d7f8a085 | 12 | select COMMON_CLK |
4adeefe1 | 13 | select CLONE_BACKWARDS |
cfdbc2e1 VG |
14 | # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev |
15 | select DEVTMPFS if !INITRAMFS_SOURCE="" | |
16 | select GENERIC_ATOMIC64 | |
17 | select GENERIC_CLOCKEVENTS | |
18 | select GENERIC_FIND_FIRST_BIT | |
19 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
20 | select GENERIC_IRQ_SHOW | |
21 | select GENERIC_PENDING_IRQ if SMP | |
22 | select GENERIC_SMP_IDLE_THREAD | |
f46121bd | 23 | select HAVE_ARCH_KGDB |
547f1125 | 24 | select HAVE_ARCH_TRACEHOOK |
4368902b | 25 | select HAVE_IOREMAP_PROT |
4d86dfbb VG |
26 | select HAVE_KPROBES |
27 | select HAVE_KRETPROBES | |
c121c506 | 28 | select HAVE_MEMBLOCK |
854a0d95 | 29 | select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND |
769bc1fd | 30 | select HAVE_OPROFILE |
9c57564e | 31 | select HAVE_PERF_EVENTS |
999159a5 | 32 | select IRQ_DOMAIN |
cfdbc2e1 | 33 | select MODULES_USE_ELF_RELA |
c121c506 | 34 | select NO_BOOTMEM |
999159a5 VG |
35 | select OF |
36 | select OF_EARLY_FLATTREE | |
9c57564e | 37 | select PERF_USE_VMALLOC |
d1a1dc0b | 38 | select HAVE_DEBUG_STACKOVERFLOW |
cfdbc2e1 | 39 | |
0dafafc3 VG |
40 | config TRACE_IRQFLAGS_SUPPORT |
41 | def_bool y | |
42 | ||
43 | config LOCKDEP_SUPPORT | |
44 | def_bool y | |
45 | ||
cfdbc2e1 VG |
46 | config SCHED_OMIT_FRAME_POINTER |
47 | def_bool y | |
48 | ||
49 | config GENERIC_CSUM | |
50 | def_bool y | |
51 | ||
52 | config RWSEM_GENERIC_SPINLOCK | |
53 | def_bool y | |
54 | ||
55 | config ARCH_FLATMEM_ENABLE | |
56 | def_bool y | |
57 | ||
58 | config MMU | |
59 | def_bool y | |
60 | ||
ce816fa8 | 61 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
62 | def_bool y |
63 | ||
64 | config GENERIC_CALIBRATE_DELAY | |
65 | def_bool y | |
66 | ||
67 | config GENERIC_HWEIGHT | |
68 | def_bool y | |
69 | ||
44c8bb91 VG |
70 | config STACKTRACE_SUPPORT |
71 | def_bool y | |
72 | select STACKTRACE | |
73 | ||
cfdbc2e1 VG |
74 | config HAVE_LATENCYTOP_SUPPORT |
75 | def_bool y | |
76 | ||
cfdbc2e1 VG |
77 | source "init/Kconfig" |
78 | source "kernel/Kconfig.freezer" | |
79 | ||
80 | menu "ARC Architecture Configuration" | |
81 | ||
93ad700d | 82 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 83 | |
fd155792 | 84 | source "arch/arc/plat-sim/Kconfig" |
072eb693 | 85 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 86 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 87 | #New platform adds here |
93ad700d | 88 | |
53d98958 | 89 | endmenu |
cfdbc2e1 | 90 | |
1f6ccfff VG |
91 | choice |
92 | prompt "ARC Instruction Set" | |
93 | default ISA_ARCOMPACT | |
94 | ||
95 | config ISA_ARCOMPACT | |
96 | bool "ARCompact ISA" | |
97 | help | |
98 | The original ARC ISA of ARC600/700 cores | |
99 | ||
65bfbcdf VG |
100 | config ISA_ARCV2 |
101 | bool "ARC ISA v2" | |
102 | help | |
103 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
104 | |
105 | endchoice | |
106 | ||
cfdbc2e1 VG |
107 | menu "ARC CPU Configuration" |
108 | ||
109 | choice | |
110 | prompt "ARC Core" | |
1f6ccfff VG |
111 | default ARC_CPU_770 if ISA_ARCOMPACT |
112 | default ARC_CPU_HS if ISA_ARCV2 | |
113 | ||
114 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
115 | |
116 | config ARC_CPU_750D | |
117 | bool "ARC750D" | |
118 | help | |
119 | Support for ARC750 core | |
120 | ||
121 | config ARC_CPU_770 | |
122 | bool "ARC770" | |
742f8af6 | 123 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
124 | help |
125 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
126 | This core has a bunch of cool new features: | |
127 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
128 | Shared Address Spaces (for sharing TLB entires in MMU) | |
129 | -Caches: New Prog Model, Region Flush | |
130 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
131 | ||
1f6ccfff VG |
132 | endif #ISA_ARCOMPACT |
133 | ||
134 | config ARC_CPU_HS | |
135 | bool "ARC-HS" | |
136 | depends on ISA_ARCV2 | |
137 | help | |
138 | Support for ARC HS38x Cores based on ARCv2 ISA | |
139 | The notable features are: | |
140 | - SMP configurations of upto 4 core with coherency | |
141 | - Optional L2 Cache and IO-Coherency | |
142 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
143 | auto stack switch, auto regfile save/restore) | |
144 | - MMUv4 (PIPT dcache, Huge Pages) | |
145 | - Instructions for | |
146 | * 64bit load/store: LDD, STD | |
147 | * Hardware assisted divide/remainder: DIV, REM | |
148 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
149 | * IRQ enable/disable: CLRI, SETI | |
150 | * pop count: FFS, FLS | |
151 | * SETcc, BMSKN, XBFU... | |
152 | ||
cfdbc2e1 VG |
153 | endchoice |
154 | ||
155 | config CPU_BIG_ENDIAN | |
156 | bool "Enable Big Endian Mode" | |
157 | default n | |
158 | help | |
159 | Build kernel for Big Endian Mode of ARC CPU | |
160 | ||
41195d23 | 161 | config SMP |
82fea5a1 | 162 | bool "Symmetric Multi-Processing" |
41195d23 | 163 | default n |
82fea5a1 VG |
164 | select ARC_HAS_COH_CACHES if ISA_ARCV2 |
165 | select ARC_MCIP if ISA_ARCV2 | |
41195d23 | 166 | help |
82fea5a1 | 167 | This enables support for systems with more than one CPU. |
41195d23 VG |
168 | |
169 | if SMP | |
170 | ||
171 | config ARC_HAS_COH_CACHES | |
172 | def_bool n | |
173 | ||
41195d23 VG |
174 | config ARC_HAS_REENTRANT_IRQ_LV2 |
175 | def_bool n | |
176 | ||
82fea5a1 VG |
177 | config ARC_MCIP |
178 | bool "ARConnect Multicore IP (MCIP) Support " | |
179 | depends on ISA_ARCV2 | |
180 | help | |
181 | This IP block enables SMP in ARC-HS38 cores. | |
182 | It provides for cross-core interrupts, multi-core debug | |
183 | hardware semaphores, shared memory,.... | |
41195d23 VG |
184 | |
185 | config NR_CPUS | |
3aa4f80e NC |
186 | int "Maximum number of CPUs (2-4096)" |
187 | range 2 4096 | |
82fea5a1 VG |
188 | default "4" |
189 | ||
190 | endif #SMP | |
41195d23 | 191 | |
cfdbc2e1 VG |
192 | menuconfig ARC_CACHE |
193 | bool "Enable Cache Support" | |
194 | default y | |
41195d23 VG |
195 | # if SMP, cache enabled ONLY if ARC implementation has cache coherency |
196 | depends on !SMP || ARC_HAS_COH_CACHES | |
cfdbc2e1 VG |
197 | |
198 | if ARC_CACHE | |
199 | ||
200 | config ARC_CACHE_LINE_SHIFT | |
201 | int "Cache Line Length (as power of 2)" | |
202 | range 5 7 | |
203 | default "6" | |
204 | help | |
205 | Starting with ARC700 4.9, Cache line length is configurable, | |
206 | This option specifies "N", with Line-len = 2 power N | |
207 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
208 | Linux only supports same line lengths for I and D caches. | |
209 | ||
210 | config ARC_HAS_ICACHE | |
211 | bool "Use Instruction Cache" | |
212 | default y | |
213 | ||
214 | config ARC_HAS_DCACHE | |
215 | bool "Use Data Cache" | |
216 | default y | |
217 | ||
218 | config ARC_CACHE_PAGES | |
219 | bool "Per Page Cache Control" | |
220 | default y | |
221 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
222 | help | |
223 | This can be used to over-ride the global I/D Cache Enable on a | |
224 | per-page basis (but only for pages accessed via MMU such as | |
225 | Kernel Virtual address or User Virtual Address) | |
226 | TLB entries have a per-page Cache Enable Bit. | |
227 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
228 | Global DISABLE + Per Page ENABLE won't work | |
229 | ||
4102b533 VG |
230 | config ARC_CACHE_VIPT_ALIASING |
231 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 232 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 VG |
233 | default n |
234 | ||
cfdbc2e1 VG |
235 | endif #ARC_CACHE |
236 | ||
8b5850f8 VG |
237 | config ARC_HAS_ICCM |
238 | bool "Use ICCM" | |
239 | help | |
240 | Single Cycle RAMS to store Fast Path Code | |
241 | default n | |
242 | ||
243 | config ARC_ICCM_SZ | |
244 | int "ICCM Size in KB" | |
245 | default "64" | |
246 | depends on ARC_HAS_ICCM | |
247 | ||
248 | config ARC_HAS_DCCM | |
249 | bool "Use DCCM" | |
250 | help | |
251 | Single Cycle RAMS to store Fast Path Data | |
252 | default n | |
253 | ||
254 | config ARC_DCCM_SZ | |
255 | int "DCCM Size in KB" | |
256 | default "64" | |
257 | depends on ARC_HAS_DCCM | |
258 | ||
259 | config ARC_DCCM_BASE | |
260 | hex "DCCM map address" | |
261 | default "0xA0000000" | |
262 | depends on ARC_HAS_DCCM | |
263 | ||
cfdbc2e1 VG |
264 | config ARC_HAS_HW_MPY |
265 | bool "Use Hardware Multiplier (Normal or Faster XMAC)" | |
266 | default y | |
267 | help | |
268 | Influences how gcc generates code for MPY operations. | |
269 | If enabled, MPYxx insns are generated, provided by Standard/XMAC | |
270 | Multipler. Otherwise software multipy lib is used | |
271 | ||
272 | choice | |
1f6ccfff | 273 | prompt "MMU Version" |
cfdbc2e1 VG |
274 | default ARC_MMU_V3 if ARC_CPU_770 |
275 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 276 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 VG |
277 | |
278 | config ARC_MMU_V1 | |
279 | bool "MMU v1" | |
280 | help | |
281 | Orig ARC700 MMU | |
282 | ||
283 | config ARC_MMU_V2 | |
284 | bool "MMU v2" | |
285 | help | |
286 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio | |
287 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. | |
288 | ||
289 | config ARC_MMU_V3 | |
290 | bool "MMU v3" | |
291 | depends on ARC_CPU_770 | |
292 | help | |
293 | Introduced with ARC700 4.10: New Features | |
294 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
295 | Shared Address Spaces (SASID) | |
296 | ||
d7a512bf VG |
297 | config ARC_MMU_V4 |
298 | bool "MMU v4" | |
299 | depends on ISA_ARCV2 | |
300 | ||
cfdbc2e1 VG |
301 | endchoice |
302 | ||
303 | ||
304 | choice | |
305 | prompt "MMU Page Size" | |
306 | default ARC_PAGE_SIZE_8K | |
307 | ||
308 | config ARC_PAGE_SIZE_8K | |
309 | bool "8KB" | |
310 | help | |
311 | Choose between 8k vs 16k | |
312 | ||
313 | config ARC_PAGE_SIZE_16K | |
314 | bool "16KB" | |
315 | depends on ARC_MMU_V3 | |
316 | ||
317 | config ARC_PAGE_SIZE_4K | |
318 | bool "4KB" | |
319 | depends on ARC_MMU_V3 | |
320 | ||
321 | endchoice | |
322 | ||
1f6ccfff VG |
323 | if ISA_ARCOMPACT |
324 | ||
4788a594 VG |
325 | config ARC_COMPACT_IRQ_LEVELS |
326 | bool "ARCompact IRQ Priorities: High(2)/Low(1)" | |
327 | default n | |
328 | # Timer HAS to be high priority, for any other high priority config | |
329 | select ARC_IRQ3_LV2 | |
41195d23 VG |
330 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
331 | depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 | |
4788a594 VG |
332 | |
333 | if ARC_COMPACT_IRQ_LEVELS | |
334 | ||
335 | config ARC_IRQ3_LV2 | |
336 | bool | |
337 | ||
338 | config ARC_IRQ5_LV2 | |
339 | bool | |
340 | ||
341 | config ARC_IRQ6_LV2 | |
342 | bool | |
343 | ||
1f6ccfff | 344 | endif #ARC_COMPACT_IRQ_LEVELS |
4788a594 | 345 | |
cfdbc2e1 VG |
346 | config ARC_FPU_SAVE_RESTORE |
347 | bool "Enable FPU state persistence across context switch" | |
348 | default n | |
349 | help | |
350 | Double Precision Floating Point unit had dedictaed regs which | |
351 | need to be saved/restored across context-switch. | |
352 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
353 | hardware pieces to allow software to conditionally save/restore, | |
354 | based on actual usage of FPU by a task. Thus our implemn does | |
355 | this for all tasks in system. | |
356 | ||
1f6ccfff VG |
357 | endif #ISA_ARCOMPACT |
358 | ||
fbf8e13d VG |
359 | config ARC_CANT_LLSC |
360 | def_bool n | |
361 | ||
cfdbc2e1 VG |
362 | config ARC_HAS_LLSC |
363 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
364 | default y | |
1f6ccfff | 365 | depends on !ARC_CPU_750D && !ARC_CANT_LLSC |
cfdbc2e1 VG |
366 | |
367 | config ARC_HAS_SWAPE | |
368 | bool "Insn: SWAPE (endian-swap)" | |
369 | default y | |
cfdbc2e1 | 370 | |
1f6ccfff VG |
371 | if ISA_ARCV2 |
372 | ||
373 | config ARC_HAS_LL64 | |
374 | bool "Insn: 64bit LDD/STD" | |
375 | help | |
376 | Enable gcc to generate 64-bit load/store instructions | |
377 | ISA mandates even/odd registers to allow encoding of two | |
378 | dest operands with 2 possible source operands. | |
379 | default y | |
380 | ||
aa93e8ef VG |
381 | config ARC_HAS_RTC |
382 | bool "Local 64-bit r/o cycle counter" | |
383 | default n | |
384 | depends on !SMP | |
385 | ||
72d72880 VG |
386 | config ARC_HAS_GRTC |
387 | bool "SMP synchronized 64-bit cycle counter" | |
388 | default y | |
389 | depends on SMP | |
390 | ||
1f6ccfff VG |
391 | config ARC_NUMBER_OF_INTERRUPTS |
392 | int "Number of interrupts" | |
393 | range 8 240 | |
394 | default 32 | |
395 | help | |
396 | This defines the number of interrupts on the ARCv2HS core. | |
397 | It affects the size of vector table. | |
398 | The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable | |
399 | in hardware, it keep things simple for Linux to assume they are always | |
400 | present. | |
401 | ||
402 | endif # ISA_ARCV2 | |
403 | ||
cfdbc2e1 VG |
404 | endmenu # "ARC CPU Configuration" |
405 | ||
cfdbc2e1 VG |
406 | config LINUX_LINK_BASE |
407 | hex "Linux Link Address" | |
408 | default "0x80000000" | |
409 | help | |
410 | ARC700 divides the 32 bit phy address space into two equal halves | |
411 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
412 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
413 | Typically Linux kernel is linked at the start of untransalted addr, | |
414 | hence the default value of 0x8zs. | |
415 | However some customers have peripherals mapped at this addr, so | |
416 | Linux needs to be scooted a bit. | |
417 | If you don't know what the above means, leave this setting alone. | |
418 | ||
080c3747 VG |
419 | config ARC_CURR_IN_REG |
420 | bool "Dedicate Register r25 for current_task pointer" | |
421 | default y | |
422 | help | |
423 | This reserved Register R25 to point to Current Task in | |
424 | kernel mode. This saves memory access for each such access | |
425 | ||
2e651ea1 | 426 | |
1736a56f | 427 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 428 | bool "Emulate unaligned memory access (userspace only)" |
1f6ccfff | 429 | default N |
2e651ea1 VG |
430 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
431 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 432 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
433 | help |
434 | This enables misaligned 16 & 32 bit memory access from user space. | |
435 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
436 | potential bugs in code | |
437 | ||
cfdbc2e1 VG |
438 | config HZ |
439 | int "Timer Frequency" | |
440 | default 100 | |
441 | ||
cbe056f7 VG |
442 | config ARC_METAWARE_HLINK |
443 | bool "Support for Metaware debugger assisted Host access" | |
444 | default n | |
445 | help | |
446 | This options allows a Linux userland apps to directly access | |
447 | host file system (open/creat/read/write etc) with help from | |
448 | Metaware Debugger. This can come in handy for Linux-host communication | |
449 | when there is no real usable peripheral such as EMAC. | |
450 | ||
cfdbc2e1 VG |
451 | menuconfig ARC_DBG |
452 | bool "ARC debugging" | |
453 | default y | |
454 | ||
aa6083ed VG |
455 | if ARC_DBG |
456 | ||
854a0d95 VG |
457 | config ARC_DW2_UNWIND |
458 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
459 | default y |
460 | select KALLSYMS | |
461 | help | |
462 | Compiles the kernel with DWARF unwind information and can be used | |
463 | to get stack backtraces. | |
464 | ||
465 | If you say Y here the resulting kernel image will be slightly larger | |
466 | but not slower, and it will give very useful debugging information. | |
467 | If you don't debug the kernel, you can say N, but we may not be able | |
468 | to solve problems without frame unwind information | |
469 | ||
cfdbc2e1 VG |
470 | config ARC_DBG_TLB_PARANOIA |
471 | bool "Paranoia Checks in Low Level TLB Handlers" | |
cfdbc2e1 VG |
472 | default n |
473 | ||
474 | config ARC_DBG_TLB_MISS_COUNT | |
475 | bool "Profile TLB Misses" | |
476 | default n | |
477 | select DEBUG_FS | |
cfdbc2e1 VG |
478 | help |
479 | Counts number of I and D TLB Misses and exports them via Debugfs | |
480 | The counters can be cleared via Debugfs as well | |
481 | ||
aa6083ed VG |
482 | if SMP |
483 | ||
484 | config ARC_IPI_DBG | |
485 | bool "Debug Inter Core interrupts" | |
486 | default n | |
487 | ||
488 | endif | |
489 | ||
490 | endif | |
491 | ||
036b2c56 VG |
492 | config ARC_UBOOT_SUPPORT |
493 | bool "Support uboot arg Handling" | |
494 | default n | |
495 | help | |
496 | ARC Linux by default checks for uboot provided args as pointers to | |
497 | external cmdline or DTB. This however breaks in absence of uboot, | |
498 | when booting from Metaware debugger directly, as the registers are | |
499 | not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus | |
500 | registers look like uboot args to kernel which then chokes. | |
501 | So only enable the uboot arg checking/processing if users are sure | |
502 | of uboot being in play. | |
503 | ||
999159a5 VG |
504 | config ARC_BUILTIN_DTB_NAME |
505 | string "Built in DTB" | |
506 | help | |
507 | Set the name of the DTB to embed in the vmlinux binary | |
508 | Leaving it blank selects the minimal "skeleton" dtb | |
509 | ||
cfdbc2e1 VG |
510 | source "kernel/Kconfig.preempt" |
511 | ||
5628832f VG |
512 | menu "Executable file formats" |
513 | source "fs/Kconfig.binfmt" | |
514 | endmenu | |
515 | ||
cfdbc2e1 VG |
516 | endmenu # "ARC Architecture Configuration" |
517 | ||
518 | source "mm/Kconfig" | |
519 | source "net/Kconfig" | |
520 | source "drivers/Kconfig" | |
521 | source "fs/Kconfig" | |
522 | source "arch/arc/Kconfig.debug" | |
523 | source "security/Kconfig" | |
524 | source "crypto/Kconfig" | |
525 | source "lib/Kconfig" | |
996bad6c | 526 | source "kernel/power/Kconfig" |