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cfdbc2e1 VG |
1 | # |
2 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | # | |
4 | # This program is free software; you can redistribute it and/or modify | |
5 | # it under the terms of the GNU General Public License version 2 as | |
6 | # published by the Free Software Foundation. | |
7 | # | |
8 | ||
9 | config ARC | |
10 | def_bool y | |
11 | select ARCH_NO_VIRT_TO_BUS | |
4adeefe1 | 12 | select CLONE_BACKWARDS |
cfdbc2e1 VG |
13 | # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev |
14 | select DEVTMPFS if !INITRAMFS_SOURCE="" | |
15 | select GENERIC_ATOMIC64 | |
16 | select GENERIC_CLOCKEVENTS | |
17 | select GENERIC_FIND_FIRST_BIT | |
18 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
19 | select GENERIC_IRQ_SHOW | |
bf90e1ea VG |
20 | select GENERIC_KERNEL_EXECVE |
21 | select GENERIC_KERNEL_THREAD | |
cfdbc2e1 | 22 | select GENERIC_PENDING_IRQ if SMP |
c3581039 | 23 | select GENERIC_SIGALTSTACK |
cfdbc2e1 | 24 | select GENERIC_SMP_IDLE_THREAD |
f46121bd | 25 | select HAVE_ARCH_KGDB |
547f1125 | 26 | select HAVE_ARCH_TRACEHOOK |
cfdbc2e1 | 27 | select HAVE_GENERIC_HARDIRQS |
4368902b | 28 | select HAVE_IOREMAP_PROT |
9c57564e | 29 | select HAVE_IRQ_WORK |
4d86dfbb VG |
30 | select HAVE_KPROBES |
31 | select HAVE_KRETPROBES | |
c121c506 | 32 | select HAVE_MEMBLOCK |
854a0d95 | 33 | select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND |
769bc1fd | 34 | select HAVE_OPROFILE |
9c57564e | 35 | select HAVE_PERF_EVENTS |
999159a5 | 36 | select IRQ_DOMAIN |
cfdbc2e1 | 37 | select MODULES_USE_ELF_RELA |
c121c506 | 38 | select NO_BOOTMEM |
999159a5 VG |
39 | select OF |
40 | select OF_EARLY_FLATTREE | |
9c57564e | 41 | select PERF_USE_VMALLOC |
cfdbc2e1 VG |
42 | |
43 | config SCHED_OMIT_FRAME_POINTER | |
44 | def_bool y | |
45 | ||
46 | config GENERIC_CSUM | |
47 | def_bool y | |
48 | ||
49 | config RWSEM_GENERIC_SPINLOCK | |
50 | def_bool y | |
51 | ||
52 | config ARCH_FLATMEM_ENABLE | |
53 | def_bool y | |
54 | ||
55 | config MMU | |
56 | def_bool y | |
57 | ||
58 | config NO_IOPORT | |
59 | def_bool y | |
60 | ||
61 | config GENERIC_CALIBRATE_DELAY | |
62 | def_bool y | |
63 | ||
64 | config GENERIC_HWEIGHT | |
65 | def_bool y | |
66 | ||
67 | config BINFMT_ELF | |
68 | def_bool y | |
69 | ||
44c8bb91 VG |
70 | config STACKTRACE_SUPPORT |
71 | def_bool y | |
72 | select STACKTRACE | |
73 | ||
cfdbc2e1 VG |
74 | config HAVE_LATENCYTOP_SUPPORT |
75 | def_bool y | |
76 | ||
77 | config NO_DMA | |
78 | def_bool n | |
79 | ||
80 | source "init/Kconfig" | |
81 | source "kernel/Kconfig.freezer" | |
82 | ||
83 | menu "ARC Architecture Configuration" | |
84 | ||
85 | choice | |
86 | prompt "ARC Platform" | |
87 | default ARC_PLAT_FPGA_LEGACY | |
88 | ||
89 | config ARC_PLAT_FPGA_LEGACY | |
90 | bool "\"Legacy\" ARC FPGA dev platform" | |
91 | help | |
92 | Support for ARC development platforms, provided by Synopsys. | |
93 | These are based on FPGA or ISS. e.g. | |
94 | - ARCAngel4 | |
95 | - ML509 | |
96 | - MetaWare ISS | |
97 | ||
98 | #New platform adds here | |
99 | endchoice | |
100 | ||
101 | menu "ARC CPU Configuration" | |
102 | ||
103 | choice | |
104 | prompt "ARC Core" | |
105 | default ARC_CPU_770 | |
106 | ||
107 | config ARC_CPU_750D | |
108 | bool "ARC750D" | |
109 | help | |
110 | Support for ARC750 core | |
111 | ||
112 | config ARC_CPU_770 | |
113 | bool "ARC770" | |
114 | select ARC_CPU_REL_4_10 | |
115 | help | |
116 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
117 | This core has a bunch of cool new features: | |
118 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
119 | Shared Address Spaces (for sharing TLB entires in MMU) | |
120 | -Caches: New Prog Model, Region Flush | |
121 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
122 | ||
123 | endchoice | |
124 | ||
125 | config CPU_BIG_ENDIAN | |
126 | bool "Enable Big Endian Mode" | |
127 | default n | |
128 | help | |
129 | Build kernel for Big Endian Mode of ARC CPU | |
130 | ||
41195d23 VG |
131 | config SMP |
132 | bool "Symmetric Multi-Processing (Incomplete)" | |
133 | default n | |
134 | select USE_GENERIC_SMP_HELPERS | |
135 | help | |
136 | This enables support for systems with more than one CPU. If you have | |
137 | a system with only one CPU, like most personal computers, say N. If | |
138 | you have a system with more than one CPU, say Y. | |
139 | ||
140 | if SMP | |
141 | ||
142 | config ARC_HAS_COH_CACHES | |
143 | def_bool n | |
144 | ||
145 | config ARC_HAS_COH_LLSC | |
146 | def_bool n | |
147 | ||
148 | config ARC_HAS_COH_RTSC | |
149 | def_bool n | |
150 | ||
151 | config ARC_HAS_REENTRANT_IRQ_LV2 | |
152 | def_bool n | |
153 | ||
154 | endif | |
155 | ||
156 | config NR_CPUS | |
157 | int "Maximum number of CPUs (2-32)" | |
158 | range 2 32 | |
159 | depends on SMP | |
160 | default "2" | |
161 | ||
cfdbc2e1 VG |
162 | menuconfig ARC_CACHE |
163 | bool "Enable Cache Support" | |
164 | default y | |
41195d23 VG |
165 | # if SMP, cache enabled ONLY if ARC implementation has cache coherency |
166 | depends on !SMP || ARC_HAS_COH_CACHES | |
cfdbc2e1 VG |
167 | |
168 | if ARC_CACHE | |
169 | ||
170 | config ARC_CACHE_LINE_SHIFT | |
171 | int "Cache Line Length (as power of 2)" | |
172 | range 5 7 | |
173 | default "6" | |
174 | help | |
175 | Starting with ARC700 4.9, Cache line length is configurable, | |
176 | This option specifies "N", with Line-len = 2 power N | |
177 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
178 | Linux only supports same line lengths for I and D caches. | |
179 | ||
180 | config ARC_HAS_ICACHE | |
181 | bool "Use Instruction Cache" | |
182 | default y | |
183 | ||
184 | config ARC_HAS_DCACHE | |
185 | bool "Use Data Cache" | |
186 | default y | |
187 | ||
188 | config ARC_CACHE_PAGES | |
189 | bool "Per Page Cache Control" | |
190 | default y | |
191 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
192 | help | |
193 | This can be used to over-ride the global I/D Cache Enable on a | |
194 | per-page basis (but only for pages accessed via MMU such as | |
195 | Kernel Virtual address or User Virtual Address) | |
196 | TLB entries have a per-page Cache Enable Bit. | |
197 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
198 | Global DISABLE + Per Page ENABLE won't work | |
199 | ||
200 | endif #ARC_CACHE | |
201 | ||
8b5850f8 VG |
202 | config ARC_HAS_ICCM |
203 | bool "Use ICCM" | |
204 | help | |
205 | Single Cycle RAMS to store Fast Path Code | |
206 | default n | |
207 | ||
208 | config ARC_ICCM_SZ | |
209 | int "ICCM Size in KB" | |
210 | default "64" | |
211 | depends on ARC_HAS_ICCM | |
212 | ||
213 | config ARC_HAS_DCCM | |
214 | bool "Use DCCM" | |
215 | help | |
216 | Single Cycle RAMS to store Fast Path Data | |
217 | default n | |
218 | ||
219 | config ARC_DCCM_SZ | |
220 | int "DCCM Size in KB" | |
221 | default "64" | |
222 | depends on ARC_HAS_DCCM | |
223 | ||
224 | config ARC_DCCM_BASE | |
225 | hex "DCCM map address" | |
226 | default "0xA0000000" | |
227 | depends on ARC_HAS_DCCM | |
228 | ||
cfdbc2e1 VG |
229 | config ARC_HAS_HW_MPY |
230 | bool "Use Hardware Multiplier (Normal or Faster XMAC)" | |
231 | default y | |
232 | help | |
233 | Influences how gcc generates code for MPY operations. | |
234 | If enabled, MPYxx insns are generated, provided by Standard/XMAC | |
235 | Multipler. Otherwise software multipy lib is used | |
236 | ||
237 | choice | |
238 | prompt "ARC700 MMU Version" | |
239 | default ARC_MMU_V3 if ARC_CPU_770 | |
240 | default ARC_MMU_V2 if ARC_CPU_750D | |
241 | ||
242 | config ARC_MMU_V1 | |
243 | bool "MMU v1" | |
244 | help | |
245 | Orig ARC700 MMU | |
246 | ||
247 | config ARC_MMU_V2 | |
248 | bool "MMU v2" | |
249 | help | |
250 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio | |
251 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. | |
252 | ||
253 | config ARC_MMU_V3 | |
254 | bool "MMU v3" | |
255 | depends on ARC_CPU_770 | |
256 | help | |
257 | Introduced with ARC700 4.10: New Features | |
258 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
259 | Shared Address Spaces (SASID) | |
260 | ||
261 | endchoice | |
262 | ||
263 | ||
264 | choice | |
265 | prompt "MMU Page Size" | |
266 | default ARC_PAGE_SIZE_8K | |
267 | ||
268 | config ARC_PAGE_SIZE_8K | |
269 | bool "8KB" | |
270 | help | |
271 | Choose between 8k vs 16k | |
272 | ||
273 | config ARC_PAGE_SIZE_16K | |
274 | bool "16KB" | |
275 | depends on ARC_MMU_V3 | |
276 | ||
277 | config ARC_PAGE_SIZE_4K | |
278 | bool "4KB" | |
279 | depends on ARC_MMU_V3 | |
280 | ||
281 | endchoice | |
282 | ||
4788a594 VG |
283 | config ARC_COMPACT_IRQ_LEVELS |
284 | bool "ARCompact IRQ Priorities: High(2)/Low(1)" | |
285 | default n | |
286 | # Timer HAS to be high priority, for any other high priority config | |
287 | select ARC_IRQ3_LV2 | |
41195d23 VG |
288 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
289 | depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 | |
4788a594 VG |
290 | |
291 | if ARC_COMPACT_IRQ_LEVELS | |
292 | ||
293 | config ARC_IRQ3_LV2 | |
294 | bool | |
295 | ||
296 | config ARC_IRQ5_LV2 | |
297 | bool | |
298 | ||
299 | config ARC_IRQ6_LV2 | |
300 | bool | |
301 | ||
302 | endif | |
303 | ||
cfdbc2e1 VG |
304 | config ARC_FPU_SAVE_RESTORE |
305 | bool "Enable FPU state persistence across context switch" | |
306 | default n | |
307 | help | |
308 | Double Precision Floating Point unit had dedictaed regs which | |
309 | need to be saved/restored across context-switch. | |
310 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
311 | hardware pieces to allow software to conditionally save/restore, | |
312 | based on actual usage of FPU by a task. Thus our implemn does | |
313 | this for all tasks in system. | |
314 | ||
315 | menuconfig ARC_CPU_REL_4_10 | |
316 | bool "Enable support for Rel 4.10 features" | |
317 | default n | |
318 | help | |
319 | -ARC770 (and dependent features) enabled | |
320 | -ARC750 also shares some of the new features with 770 | |
321 | ||
322 | config ARC_HAS_LLSC | |
323 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
324 | default y | |
325 | depends on ARC_CPU_770 | |
326 | # if SMP, enable LLSC ONLY if ARC implementation has coherent atomics | |
327 | depends on !SMP || ARC_HAS_COH_LLSC | |
328 | ||
329 | config ARC_HAS_SWAPE | |
330 | bool "Insn: SWAPE (endian-swap)" | |
331 | default y | |
332 | depends on ARC_CPU_REL_4_10 | |
333 | ||
334 | config ARC_HAS_RTSC | |
335 | bool "Insn: RTSC (64-bit r/o cycle counter)" | |
336 | default y | |
337 | depends on ARC_CPU_REL_4_10 | |
41195d23 VG |
338 | # if SMP, enable RTSC only if counter is coherent across cores |
339 | depends on !SMP || ARC_HAS_COH_RTSC | |
cfdbc2e1 VG |
340 | |
341 | endmenu # "ARC CPU Configuration" | |
342 | ||
343 | menu "Platform Board Configuration" | |
344 | ||
345 | source "arch/arc/plat-arcfpga/Kconfig" | |
346 | ||
347 | #New platform adds here | |
348 | ||
cfdbc2e1 VG |
349 | config LINUX_LINK_BASE |
350 | hex "Linux Link Address" | |
351 | default "0x80000000" | |
352 | help | |
353 | ARC700 divides the 32 bit phy address space into two equal halves | |
354 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
355 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
356 | Typically Linux kernel is linked at the start of untransalted addr, | |
357 | hence the default value of 0x8zs. | |
358 | However some customers have peripherals mapped at this addr, so | |
359 | Linux needs to be scooted a bit. | |
360 | If you don't know what the above means, leave this setting alone. | |
361 | ||
cfdbc2e1 VG |
362 | endmenu # "Platform Board Configuration" |
363 | ||
080c3747 VG |
364 | config ARC_CURR_IN_REG |
365 | bool "Dedicate Register r25 for current_task pointer" | |
366 | default y | |
367 | help | |
368 | This reserved Register R25 to point to Current Task in | |
369 | kernel mode. This saves memory access for each such access | |
370 | ||
2e651ea1 VG |
371 | |
372 | config ARC_MISALIGN_ACCESS | |
373 | bool "Emulate unaligned memory access (userspace only)" | |
374 | default N | |
375 | select SYSCTL_ARCH_UNALIGN_NO_WARN | |
376 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
377 | help | |
378 | This enables misaligned 16 & 32 bit memory access from user space. | |
379 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
380 | potential bugs in code | |
381 | ||
cfdbc2e1 VG |
382 | config ARC_STACK_NONEXEC |
383 | bool "Make stack non-executable" | |
384 | default n | |
385 | help | |
386 | To disable the execute permissions of stack/heap of processes | |
387 | which are enabled by default. | |
388 | ||
389 | config HZ | |
390 | int "Timer Frequency" | |
391 | default 100 | |
392 | ||
cbe056f7 VG |
393 | config ARC_METAWARE_HLINK |
394 | bool "Support for Metaware debugger assisted Host access" | |
395 | default n | |
396 | help | |
397 | This options allows a Linux userland apps to directly access | |
398 | host file system (open/creat/read/write etc) with help from | |
399 | Metaware Debugger. This can come in handy for Linux-host communication | |
400 | when there is no real usable peripheral such as EMAC. | |
401 | ||
cfdbc2e1 VG |
402 | menuconfig ARC_DBG |
403 | bool "ARC debugging" | |
404 | default y | |
405 | ||
854a0d95 VG |
406 | config ARC_DW2_UNWIND |
407 | bool "Enable DWARF specific kernel stack unwind" | |
408 | depends on ARC_DBG | |
409 | default y | |
410 | select KALLSYMS | |
411 | help | |
412 | Compiles the kernel with DWARF unwind information and can be used | |
413 | to get stack backtraces. | |
414 | ||
415 | If you say Y here the resulting kernel image will be slightly larger | |
416 | but not slower, and it will give very useful debugging information. | |
417 | If you don't debug the kernel, you can say N, but we may not be able | |
418 | to solve problems without frame unwind information | |
419 | ||
cfdbc2e1 VG |
420 | config ARC_DBG_TLB_PARANOIA |
421 | bool "Paranoia Checks in Low Level TLB Handlers" | |
f46121bd | 422 | depends on ARC_DBG |
cfdbc2e1 VG |
423 | default n |
424 | ||
425 | config ARC_DBG_TLB_MISS_COUNT | |
426 | bool "Profile TLB Misses" | |
427 | default n | |
428 | select DEBUG_FS | |
429 | depends on ARC_DBG | |
430 | help | |
431 | Counts number of I and D TLB Misses and exports them via Debugfs | |
432 | The counters can be cleared via Debugfs as well | |
433 | ||
434 | config CMDLINE | |
435 | string "Kernel command line to built-in" | |
436 | default "print-fatal-signals=1" | |
437 | help | |
438 | The default command line which will be appended to the optional | |
439 | u-boot provided command line (see below) | |
440 | ||
441 | config CMDLINE_UBOOT | |
442 | bool "Support U-boot kernel command line passing" | |
443 | default n | |
444 | help | |
445 | If you are using U-boot (www.denx.de) and wish to pass the kernel | |
446 | command line from the U-boot environment to the Linux kernel then | |
447 | switch this option on. | |
448 | ARC U-boot will setup the cmdline in RAM/flash and set r2 to point | |
449 | to it. kernel startup code will copy the string into cmdline buffer | |
450 | and also append CONFIG_CMDLINE. | |
451 | ||
999159a5 VG |
452 | config ARC_BUILTIN_DTB_NAME |
453 | string "Built in DTB" | |
454 | help | |
455 | Set the name of the DTB to embed in the vmlinux binary | |
456 | Leaving it blank selects the minimal "skeleton" dtb | |
457 | ||
cfdbc2e1 VG |
458 | source "kernel/Kconfig.preempt" |
459 | ||
460 | endmenu # "ARC Architecture Configuration" | |
461 | ||
462 | source "mm/Kconfig" | |
463 | source "net/Kconfig" | |
464 | source "drivers/Kconfig" | |
465 | source "fs/Kconfig" | |
466 | source "arch/arc/Kconfig.debug" | |
467 | source "security/Kconfig" | |
468 | source "crypto/Kconfig" | |
469 | source "lib/Kconfig" |