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1#
2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License version 2 as
6# published by the Free Software Foundation.
7#
8
9config ARC
10 def_bool y
2a440168 11 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
f06d19e4 12 select BUILDTIME_EXTABLE_SORT
d7f8a085 13 select COMMON_CLK
4adeefe1 14 select CLONE_BACKWARDS
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15 select GENERIC_ATOMIC64
16 select GENERIC_CLOCKEVENTS
17 select GENERIC_FIND_FIRST_BIT
18 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PENDING_IRQ if SMP
21 select GENERIC_SMP_IDLE_THREAD
f46121bd 22 select HAVE_ARCH_KGDB
547f1125 23 select HAVE_ARCH_TRACEHOOK
5e057429 24 select HAVE_FUTEX_CMPXCHG
4368902b 25 select HAVE_IOREMAP_PROT
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26 select HAVE_KPROBES
27 select HAVE_KRETPROBES
c121c506 28 select HAVE_MEMBLOCK
854a0d95 29 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
769bc1fd 30 select HAVE_OPROFILE
9c57564e 31 select HAVE_PERF_EVENTS
999159a5 32 select IRQ_DOMAIN
cfdbc2e1 33 select MODULES_USE_ELF_RELA
c121c506 34 select NO_BOOTMEM
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35 select OF
36 select OF_EARLY_FLATTREE
9c57564e 37 select PERF_USE_VMALLOC
d1a1dc0b 38 select HAVE_DEBUG_STACKOVERFLOW
cfdbc2e1 39
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40config TRACE_IRQFLAGS_SUPPORT
41 def_bool y
42
43config LOCKDEP_SUPPORT
44 def_bool y
45
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46config SCHED_OMIT_FRAME_POINTER
47 def_bool y
48
49config GENERIC_CSUM
50 def_bool y
51
52config RWSEM_GENERIC_SPINLOCK
53 def_bool y
54
55config ARCH_FLATMEM_ENABLE
56 def_bool y
57
58config MMU
59 def_bool y
60
ce816fa8 61config NO_IOPORT_MAP
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62 def_bool y
63
64config GENERIC_CALIBRATE_DELAY
65 def_bool y
66
67config GENERIC_HWEIGHT
68 def_bool y
69
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70config STACKTRACE_SUPPORT
71 def_bool y
72 select STACKTRACE
73
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74config HAVE_ARCH_TRANSPARENT_HUGEPAGE
75 def_bool y
76 depends on ARC_MMU_V4
77
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78source "init/Kconfig"
79source "kernel/Kconfig.freezer"
80
81menu "ARC Architecture Configuration"
82
93ad700d 83menu "ARC Platform/SoC/Board"
cfdbc2e1 84
fd155792 85source "arch/arc/plat-sim/Kconfig"
072eb693 86source "arch/arc/plat-tb10x/Kconfig"
556cc1c5 87source "arch/arc/plat-axs10x/Kconfig"
cfdbc2e1 88#New platform adds here
93ad700d 89
53d98958 90endmenu
cfdbc2e1 91
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92choice
93 prompt "ARC Instruction Set"
94 default ISA_ARCOMPACT
95
96config ISA_ARCOMPACT
97 bool "ARCompact ISA"
98 help
99 The original ARC ISA of ARC600/700 cores
100
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101config ISA_ARCV2
102 bool "ARC ISA v2"
103 help
104 ISA for the Next Generation ARC-HS cores
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105
106endchoice
107
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108menu "ARC CPU Configuration"
109
110choice
111 prompt "ARC Core"
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112 default ARC_CPU_770 if ISA_ARCOMPACT
113 default ARC_CPU_HS if ISA_ARCV2
114
115if ISA_ARCOMPACT
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116
117config ARC_CPU_750D
118 bool "ARC750D"
14a0abfc 119 select ARC_CANT_LLSC
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120 help
121 Support for ARC750 core
122
123config ARC_CPU_770
124 bool "ARC770"
742f8af6 125 select ARC_HAS_SWAPE
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126 help
127 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
128 This core has a bunch of cool new features:
129 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
130 Shared Address Spaces (for sharing TLB entires in MMU)
131 -Caches: New Prog Model, Region Flush
132 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
133
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134endif #ISA_ARCOMPACT
135
136config ARC_CPU_HS
137 bool "ARC-HS"
138 depends on ISA_ARCV2
139 help
140 Support for ARC HS38x Cores based on ARCv2 ISA
141 The notable features are:
142 - SMP configurations of upto 4 core with coherency
143 - Optional L2 Cache and IO-Coherency
144 - Revised Interrupt Architecture (multiple priorites, reg banks,
145 auto stack switch, auto regfile save/restore)
146 - MMUv4 (PIPT dcache, Huge Pages)
147 - Instructions for
148 * 64bit load/store: LDD, STD
149 * Hardware assisted divide/remainder: DIV, REM
150 * Function prologue/epilogue: ENTER_S, LEAVE_S
151 * IRQ enable/disable: CLRI, SETI
152 * pop count: FFS, FLS
153 * SETcc, BMSKN, XBFU...
154
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155endchoice
156
157config CPU_BIG_ENDIAN
158 bool "Enable Big Endian Mode"
159 default n
160 help
161 Build kernel for Big Endian Mode of ARC CPU
162
41195d23 163config SMP
82fea5a1 164 bool "Symmetric Multi-Processing"
41195d23 165 default n
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166 select ARC_HAS_COH_CACHES if ISA_ARCV2
167 select ARC_MCIP if ISA_ARCV2
41195d23 168 help
82fea5a1 169 This enables support for systems with more than one CPU.
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170
171if SMP
172
173config ARC_HAS_COH_CACHES
174 def_bool n
175
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176config ARC_HAS_REENTRANT_IRQ_LV2
177 def_bool n
178
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179config ARC_MCIP
180 bool "ARConnect Multicore IP (MCIP) Support "
181 depends on ISA_ARCV2
182 help
183 This IP block enables SMP in ARC-HS38 cores.
184 It provides for cross-core interrupts, multi-core debug
185 hardware semaphores, shared memory,....
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186
187config NR_CPUS
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188 int "Maximum number of CPUs (2-4096)"
189 range 2 4096
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190 default "4"
191
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192config ARC_SMP_HALT_ON_RESET
193 bool "Enable Halt-on-reset boot mode"
194 default y if ARC_UBOOT_SUPPORT
195 help
196 In SMP configuration cores can be configured as Halt-on-reset
197 or they could all start at same time. For Halt-on-reset, non
198 masters are parked until Master kicks them so they can start of
199 at designated entry point. For other case, all jump to common
200 entry point and spin wait for Master's signal.
201
82fea5a1 202endif #SMP
41195d23 203
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204menuconfig ARC_CACHE
205 bool "Enable Cache Support"
206 default y
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207 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
208 depends on !SMP || ARC_HAS_COH_CACHES
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209
210if ARC_CACHE
211
212config ARC_CACHE_LINE_SHIFT
213 int "Cache Line Length (as power of 2)"
214 range 5 7
215 default "6"
216 help
217 Starting with ARC700 4.9, Cache line length is configurable,
218 This option specifies "N", with Line-len = 2 power N
219 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
220 Linux only supports same line lengths for I and D caches.
221
222config ARC_HAS_ICACHE
223 bool "Use Instruction Cache"
224 default y
225
226config ARC_HAS_DCACHE
227 bool "Use Data Cache"
228 default y
229
230config ARC_CACHE_PAGES
231 bool "Per Page Cache Control"
232 default y
233 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
234 help
235 This can be used to over-ride the global I/D Cache Enable on a
236 per-page basis (but only for pages accessed via MMU such as
237 Kernel Virtual address or User Virtual Address)
238 TLB entries have a per-page Cache Enable Bit.
239 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
240 Global DISABLE + Per Page ENABLE won't work
241
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242config ARC_CACHE_VIPT_ALIASING
243 bool "Support VIPT Aliasing D$"
d1f317d8 244 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
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245 default n
246
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247endif #ARC_CACHE
248
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249config ARC_HAS_ICCM
250 bool "Use ICCM"
251 help
252 Single Cycle RAMS to store Fast Path Code
253 default n
254
255config ARC_ICCM_SZ
256 int "ICCM Size in KB"
257 default "64"
258 depends on ARC_HAS_ICCM
259
260config ARC_HAS_DCCM
261 bool "Use DCCM"
262 help
263 Single Cycle RAMS to store Fast Path Data
264 default n
265
266config ARC_DCCM_SZ
267 int "DCCM Size in KB"
268 default "64"
269 depends on ARC_HAS_DCCM
270
271config ARC_DCCM_BASE
272 hex "DCCM map address"
273 default "0xA0000000"
274 depends on ARC_HAS_DCCM
275
cfdbc2e1 276choice
1f6ccfff 277 prompt "MMU Version"
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278 default ARC_MMU_V3 if ARC_CPU_770
279 default ARC_MMU_V2 if ARC_CPU_750D
d7a512bf 280 default ARC_MMU_V4 if ARC_CPU_HS
cfdbc2e1 281
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282if ISA_ARCOMPACT
283
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284config ARC_MMU_V1
285 bool "MMU v1"
286 help
287 Orig ARC700 MMU
288
289config ARC_MMU_V2
290 bool "MMU v2"
291 help
292 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
293 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
294
295config ARC_MMU_V3
296 bool "MMU v3"
297 depends on ARC_CPU_770
298 help
299 Introduced with ARC700 4.10: New Features
300 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
301 Shared Address Spaces (SASID)
302
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303endif
304
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305config ARC_MMU_V4
306 bool "MMU v4"
307 depends on ISA_ARCV2
308
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309endchoice
310
311
312choice
313 prompt "MMU Page Size"
314 default ARC_PAGE_SIZE_8K
315
316config ARC_PAGE_SIZE_8K
317 bool "8KB"
318 help
319 Choose between 8k vs 16k
320
321config ARC_PAGE_SIZE_16K
322 bool "16KB"
450ed0db 323 depends on ARC_MMU_V3 || ARC_MMU_V4
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324
325config ARC_PAGE_SIZE_4K
326 bool "4KB"
450ed0db 327 depends on ARC_MMU_V3 || ARC_MMU_V4
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328
329endchoice
330
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331choice
332 prompt "MMU Super Page Size"
333 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
334 default ARC_HUGEPAGE_2M
335
336config ARC_HUGEPAGE_2M
337 bool "2MB"
338
339config ARC_HUGEPAGE_16M
340 bool "16MB"
341
342endchoice
343
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344if ISA_ARCOMPACT
345
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346config ARC_COMPACT_IRQ_LEVELS
347 bool "ARCompact IRQ Priorities: High(2)/Low(1)"
348 default n
349 # Timer HAS to be high priority, for any other high priority config
350 select ARC_IRQ3_LV2
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351 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
352 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
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353
354if ARC_COMPACT_IRQ_LEVELS
355
356config ARC_IRQ3_LV2
357 bool
358
359config ARC_IRQ5_LV2
360 bool
361
362config ARC_IRQ6_LV2
363 bool
364
1f6ccfff 365endif #ARC_COMPACT_IRQ_LEVELS
4788a594 366
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367config ARC_FPU_SAVE_RESTORE
368 bool "Enable FPU state persistence across context switch"
369 default n
370 help
371 Double Precision Floating Point unit had dedictaed regs which
372 need to be saved/restored across context-switch.
373 Note that ARC FPU is overly simplistic, unlike say x86, which has
374 hardware pieces to allow software to conditionally save/restore,
375 based on actual usage of FPU by a task. Thus our implemn does
376 this for all tasks in system.
377
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378endif #ISA_ARCOMPACT
379
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380config ARC_CANT_LLSC
381 def_bool n
382
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383config ARC_HAS_LLSC
384 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
385 default y
14a0abfc 386 depends on !ARC_CANT_LLSC
cfdbc2e1 387
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388config ARC_STAR_9000923308
389 bool "Workaround for llock/scond livelock"
390 default y
391 depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
392
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393config ARC_HAS_SWAPE
394 bool "Insn: SWAPE (endian-swap)"
395 default y
cfdbc2e1 396
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397if ISA_ARCV2
398
399config ARC_HAS_LL64
400 bool "Insn: 64bit LDD/STD"
401 help
402 Enable gcc to generate 64-bit load/store instructions
403 ISA mandates even/odd registers to allow encoding of two
404 dest operands with 2 possible source operands.
405 default y
406
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407config ARC_HAS_DIV_REM
408 bool "Insn: div, divu, rem, remu"
409 default y
410
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411config ARC_HAS_RTC
412 bool "Local 64-bit r/o cycle counter"
413 default n
414 depends on !SMP
415
d584f0fb 416config ARC_HAS_GFRC
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417 bool "SMP synchronized 64-bit cycle counter"
418 default y
419 depends on SMP
420
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421config ARC_NUMBER_OF_INTERRUPTS
422 int "Number of interrupts"
423 range 8 240
424 default 32
425 help
426 This defines the number of interrupts on the ARCv2HS core.
427 It affects the size of vector table.
428 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
429 in hardware, it keep things simple for Linux to assume they are always
430 present.
431
432endif # ISA_ARCV2
433
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434endmenu # "ARC CPU Configuration"
435
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436config LINUX_LINK_BASE
437 hex "Linux Link Address"
438 default "0x80000000"
439 help
440 ARC700 divides the 32 bit phy address space into two equal halves
441 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
442 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
443 Typically Linux kernel is linked at the start of untransalted addr,
444 hence the default value of 0x8zs.
445 However some customers have peripherals mapped at this addr, so
446 Linux needs to be scooted a bit.
447 If you don't know what the above means, leave this setting alone.
ff1c0b6a 448 This needs to match memory start address specified in Device Tree
cfdbc2e1 449
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450config HIGHMEM
451 bool "High Memory Support"
452 help
453 With ARC 2G:2G address split, only upper 2G is directly addressable by
454 kernel. Enable this to potentially allow access to rest of 2G and PAE
455 in future
456
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457config ARC_HAS_PAE40
458 bool "Support for the 40-bit Physical Address Extension"
459 default n
460 depends on ISA_ARCV2
461 select HIGHMEM
462 help
463 Enable access to physical memory beyond 4G, only supported on
464 ARC cores with 40 bit Physical Addressing support
465
466config ARCH_PHYS_ADDR_T_64BIT
467 def_bool ARC_HAS_PAE40
468
469config ARCH_DMA_ADDR_T_64BIT
470 bool
471
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472config ARC_CURR_IN_REG
473 bool "Dedicate Register r25 for current_task pointer"
474 default y
475 help
476 This reserved Register R25 to point to Current Task in
477 kernel mode. This saves memory access for each such access
478
2e651ea1 479
1736a56f 480config ARC_EMUL_UNALIGNED
2e651ea1 481 bool "Emulate unaligned memory access (userspace only)"
1f6ccfff 482 default N
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483 select SYSCTL_ARCH_UNALIGN_NO_WARN
484 select SYSCTL_ARCH_UNALIGN_ALLOW
1f6ccfff 485 depends on ISA_ARCOMPACT
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486 help
487 This enables misaligned 16 & 32 bit memory access from user space.
488 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
489 potential bugs in code
490
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491config HZ
492 int "Timer Frequency"
493 default 100
494
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495config ARC_METAWARE_HLINK
496 bool "Support for Metaware debugger assisted Host access"
497 default n
498 help
499 This options allows a Linux userland apps to directly access
500 host file system (open/creat/read/write etc) with help from
501 Metaware Debugger. This can come in handy for Linux-host communication
502 when there is no real usable peripheral such as EMAC.
503
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504menuconfig ARC_DBG
505 bool "ARC debugging"
506 default y
507
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508if ARC_DBG
509
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510config ARC_DW2_UNWIND
511 bool "Enable DWARF specific kernel stack unwind"
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512 default y
513 select KALLSYMS
514 help
515 Compiles the kernel with DWARF unwind information and can be used
516 to get stack backtraces.
517
518 If you say Y here the resulting kernel image will be slightly larger
519 but not slower, and it will give very useful debugging information.
520 If you don't debug the kernel, you can say N, but we may not be able
521 to solve problems without frame unwind information
522
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523config ARC_DBG_TLB_PARANOIA
524 bool "Paranoia Checks in Low Level TLB Handlers"
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525 default n
526
527config ARC_DBG_TLB_MISS_COUNT
528 bool "Profile TLB Misses"
529 default n
530 select DEBUG_FS
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531 help
532 Counts number of I and D TLB Misses and exports them via Debugfs
533 The counters can be cleared via Debugfs as well
534
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535endif
536
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537config ARC_UBOOT_SUPPORT
538 bool "Support uboot arg Handling"
539 default n
540 help
541 ARC Linux by default checks for uboot provided args as pointers to
542 external cmdline or DTB. This however breaks in absence of uboot,
543 when booting from Metaware debugger directly, as the registers are
544 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
545 registers look like uboot args to kernel which then chokes.
546 So only enable the uboot arg checking/processing if users are sure
547 of uboot being in play.
548
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549config ARC_BUILTIN_DTB_NAME
550 string "Built in DTB"
551 help
552 Set the name of the DTB to embed in the vmlinux binary
553 Leaving it blank selects the minimal "skeleton" dtb
554
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555source "kernel/Kconfig.preempt"
556
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557menu "Executable file formats"
558source "fs/Kconfig.binfmt"
559endmenu
560
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561endmenu # "ARC Architecture Configuration"
562
563source "mm/Kconfig"
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564
565config FORCE_MAX_ZONEORDER
566 int "Maximum zone order"
567 default "12" if ARC_HUGEPAGE_16M
568 default "11"
569
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570source "net/Kconfig"
571source "drivers/Kconfig"
572source "fs/Kconfig"
573source "arch/arc/Kconfig.debug"
574source "security/Kconfig"
575source "crypto/Kconfig"
576source "lib/Kconfig"
996bad6c 577source "kernel/power/Kconfig"