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cfdbc2e1 VG |
1 | # |
2 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | # | |
4 | # This program is free software; you can redistribute it and/or modify | |
5 | # it under the terms of the GNU General Public License version 2 as | |
6 | # published by the Free Software Foundation. | |
7 | # | |
8 | ||
9 | config ARC | |
10 | def_bool y | |
2a440168 | 11 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
f06d19e4 | 12 | select BUILDTIME_EXTABLE_SORT |
d7f8a085 | 13 | select COMMON_CLK |
4adeefe1 | 14 | select CLONE_BACKWARDS |
cfdbc2e1 VG |
15 | # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev |
16 | select DEVTMPFS if !INITRAMFS_SOURCE="" | |
17 | select GENERIC_ATOMIC64 | |
18 | select GENERIC_CLOCKEVENTS | |
19 | select GENERIC_FIND_FIRST_BIT | |
20 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
21 | select GENERIC_IRQ_SHOW | |
22 | select GENERIC_PENDING_IRQ if SMP | |
23 | select GENERIC_SMP_IDLE_THREAD | |
f46121bd | 24 | select HAVE_ARCH_KGDB |
547f1125 | 25 | select HAVE_ARCH_TRACEHOOK |
5e057429 | 26 | select HAVE_FUTEX_CMPXCHG |
4368902b | 27 | select HAVE_IOREMAP_PROT |
4d86dfbb VG |
28 | select HAVE_KPROBES |
29 | select HAVE_KRETPROBES | |
c121c506 | 30 | select HAVE_MEMBLOCK |
854a0d95 | 31 | select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND |
769bc1fd | 32 | select HAVE_OPROFILE |
9c57564e | 33 | select HAVE_PERF_EVENTS |
999159a5 | 34 | select IRQ_DOMAIN |
cfdbc2e1 | 35 | select MODULES_USE_ELF_RELA |
c121c506 | 36 | select NO_BOOTMEM |
999159a5 VG |
37 | select OF |
38 | select OF_EARLY_FLATTREE | |
9c57564e | 39 | select PERF_USE_VMALLOC |
d1a1dc0b | 40 | select HAVE_DEBUG_STACKOVERFLOW |
cfdbc2e1 | 41 | |
0dafafc3 VG |
42 | config TRACE_IRQFLAGS_SUPPORT |
43 | def_bool y | |
44 | ||
45 | config LOCKDEP_SUPPORT | |
46 | def_bool y | |
47 | ||
cfdbc2e1 VG |
48 | config SCHED_OMIT_FRAME_POINTER |
49 | def_bool y | |
50 | ||
51 | config GENERIC_CSUM | |
52 | def_bool y | |
53 | ||
54 | config RWSEM_GENERIC_SPINLOCK | |
55 | def_bool y | |
56 | ||
57 | config ARCH_FLATMEM_ENABLE | |
58 | def_bool y | |
59 | ||
60 | config MMU | |
61 | def_bool y | |
62 | ||
ce816fa8 | 63 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
64 | def_bool y |
65 | ||
66 | config GENERIC_CALIBRATE_DELAY | |
67 | def_bool y | |
68 | ||
69 | config GENERIC_HWEIGHT | |
70 | def_bool y | |
71 | ||
44c8bb91 VG |
72 | config STACKTRACE_SUPPORT |
73 | def_bool y | |
74 | select STACKTRACE | |
75 | ||
fe6c1b86 VG |
76 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
77 | def_bool y | |
78 | depends on ARC_MMU_V4 | |
79 | ||
cfdbc2e1 VG |
80 | source "init/Kconfig" |
81 | source "kernel/Kconfig.freezer" | |
82 | ||
83 | menu "ARC Architecture Configuration" | |
84 | ||
93ad700d | 85 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 86 | |
fd155792 | 87 | source "arch/arc/plat-sim/Kconfig" |
072eb693 | 88 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 89 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 90 | #New platform adds here |
93ad700d | 91 | |
53d98958 | 92 | endmenu |
cfdbc2e1 | 93 | |
1f6ccfff VG |
94 | choice |
95 | prompt "ARC Instruction Set" | |
96 | default ISA_ARCOMPACT | |
97 | ||
98 | config ISA_ARCOMPACT | |
99 | bool "ARCompact ISA" | |
100 | help | |
101 | The original ARC ISA of ARC600/700 cores | |
102 | ||
65bfbcdf VG |
103 | config ISA_ARCV2 |
104 | bool "ARC ISA v2" | |
105 | help | |
106 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
107 | |
108 | endchoice | |
109 | ||
cfdbc2e1 VG |
110 | menu "ARC CPU Configuration" |
111 | ||
112 | choice | |
113 | prompt "ARC Core" | |
1f6ccfff VG |
114 | default ARC_CPU_770 if ISA_ARCOMPACT |
115 | default ARC_CPU_HS if ISA_ARCV2 | |
116 | ||
117 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
118 | |
119 | config ARC_CPU_750D | |
120 | bool "ARC750D" | |
14a0abfc | 121 | select ARC_CANT_LLSC |
cfdbc2e1 VG |
122 | help |
123 | Support for ARC750 core | |
124 | ||
125 | config ARC_CPU_770 | |
126 | bool "ARC770" | |
742f8af6 | 127 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
128 | help |
129 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
130 | This core has a bunch of cool new features: | |
131 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
132 | Shared Address Spaces (for sharing TLB entires in MMU) | |
133 | -Caches: New Prog Model, Region Flush | |
134 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
135 | ||
1f6ccfff VG |
136 | endif #ISA_ARCOMPACT |
137 | ||
138 | config ARC_CPU_HS | |
139 | bool "ARC-HS" | |
140 | depends on ISA_ARCV2 | |
141 | help | |
142 | Support for ARC HS38x Cores based on ARCv2 ISA | |
143 | The notable features are: | |
144 | - SMP configurations of upto 4 core with coherency | |
145 | - Optional L2 Cache and IO-Coherency | |
146 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
147 | auto stack switch, auto regfile save/restore) | |
148 | - MMUv4 (PIPT dcache, Huge Pages) | |
149 | - Instructions for | |
150 | * 64bit load/store: LDD, STD | |
151 | * Hardware assisted divide/remainder: DIV, REM | |
152 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
153 | * IRQ enable/disable: CLRI, SETI | |
154 | * pop count: FFS, FLS | |
155 | * SETcc, BMSKN, XBFU... | |
156 | ||
cfdbc2e1 VG |
157 | endchoice |
158 | ||
159 | config CPU_BIG_ENDIAN | |
160 | bool "Enable Big Endian Mode" | |
161 | default n | |
162 | help | |
163 | Build kernel for Big Endian Mode of ARC CPU | |
164 | ||
41195d23 | 165 | config SMP |
82fea5a1 | 166 | bool "Symmetric Multi-Processing" |
41195d23 | 167 | default n |
82fea5a1 VG |
168 | select ARC_HAS_COH_CACHES if ISA_ARCV2 |
169 | select ARC_MCIP if ISA_ARCV2 | |
41195d23 | 170 | help |
82fea5a1 | 171 | This enables support for systems with more than one CPU. |
41195d23 VG |
172 | |
173 | if SMP | |
174 | ||
175 | config ARC_HAS_COH_CACHES | |
176 | def_bool n | |
177 | ||
41195d23 VG |
178 | config ARC_HAS_REENTRANT_IRQ_LV2 |
179 | def_bool n | |
180 | ||
82fea5a1 VG |
181 | config ARC_MCIP |
182 | bool "ARConnect Multicore IP (MCIP) Support " | |
183 | depends on ISA_ARCV2 | |
184 | help | |
185 | This IP block enables SMP in ARC-HS38 cores. | |
186 | It provides for cross-core interrupts, multi-core debug | |
187 | hardware semaphores, shared memory,.... | |
41195d23 VG |
188 | |
189 | config NR_CPUS | |
3aa4f80e NC |
190 | int "Maximum number of CPUs (2-4096)" |
191 | range 2 4096 | |
82fea5a1 VG |
192 | default "4" |
193 | ||
3971cdc2 VG |
194 | config ARC_SMP_HALT_ON_RESET |
195 | bool "Enable Halt-on-reset boot mode" | |
196 | default y if ARC_UBOOT_SUPPORT | |
197 | help | |
198 | In SMP configuration cores can be configured as Halt-on-reset | |
199 | or they could all start at same time. For Halt-on-reset, non | |
200 | masters are parked until Master kicks them so they can start of | |
201 | at designated entry point. For other case, all jump to common | |
202 | entry point and spin wait for Master's signal. | |
203 | ||
82fea5a1 | 204 | endif #SMP |
41195d23 | 205 | |
cfdbc2e1 VG |
206 | menuconfig ARC_CACHE |
207 | bool "Enable Cache Support" | |
208 | default y | |
41195d23 VG |
209 | # if SMP, cache enabled ONLY if ARC implementation has cache coherency |
210 | depends on !SMP || ARC_HAS_COH_CACHES | |
cfdbc2e1 VG |
211 | |
212 | if ARC_CACHE | |
213 | ||
214 | config ARC_CACHE_LINE_SHIFT | |
215 | int "Cache Line Length (as power of 2)" | |
216 | range 5 7 | |
217 | default "6" | |
218 | help | |
219 | Starting with ARC700 4.9, Cache line length is configurable, | |
220 | This option specifies "N", with Line-len = 2 power N | |
221 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
222 | Linux only supports same line lengths for I and D caches. | |
223 | ||
224 | config ARC_HAS_ICACHE | |
225 | bool "Use Instruction Cache" | |
226 | default y | |
227 | ||
228 | config ARC_HAS_DCACHE | |
229 | bool "Use Data Cache" | |
230 | default y | |
231 | ||
232 | config ARC_CACHE_PAGES | |
233 | bool "Per Page Cache Control" | |
234 | default y | |
235 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
236 | help | |
237 | This can be used to over-ride the global I/D Cache Enable on a | |
238 | per-page basis (but only for pages accessed via MMU such as | |
239 | Kernel Virtual address or User Virtual Address) | |
240 | TLB entries have a per-page Cache Enable Bit. | |
241 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
242 | Global DISABLE + Per Page ENABLE won't work | |
243 | ||
4102b533 VG |
244 | config ARC_CACHE_VIPT_ALIASING |
245 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 246 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 VG |
247 | default n |
248 | ||
cfdbc2e1 VG |
249 | endif #ARC_CACHE |
250 | ||
8b5850f8 VG |
251 | config ARC_HAS_ICCM |
252 | bool "Use ICCM" | |
253 | help | |
254 | Single Cycle RAMS to store Fast Path Code | |
255 | default n | |
256 | ||
257 | config ARC_ICCM_SZ | |
258 | int "ICCM Size in KB" | |
259 | default "64" | |
260 | depends on ARC_HAS_ICCM | |
261 | ||
262 | config ARC_HAS_DCCM | |
263 | bool "Use DCCM" | |
264 | help | |
265 | Single Cycle RAMS to store Fast Path Data | |
266 | default n | |
267 | ||
268 | config ARC_DCCM_SZ | |
269 | int "DCCM Size in KB" | |
270 | default "64" | |
271 | depends on ARC_HAS_DCCM | |
272 | ||
273 | config ARC_DCCM_BASE | |
274 | hex "DCCM map address" | |
275 | default "0xA0000000" | |
276 | depends on ARC_HAS_DCCM | |
277 | ||
cfdbc2e1 VG |
278 | config ARC_HAS_HW_MPY |
279 | bool "Use Hardware Multiplier (Normal or Faster XMAC)" | |
280 | default y | |
281 | help | |
282 | Influences how gcc generates code for MPY operations. | |
283 | If enabled, MPYxx insns are generated, provided by Standard/XMAC | |
284 | Multipler. Otherwise software multipy lib is used | |
285 | ||
286 | choice | |
1f6ccfff | 287 | prompt "MMU Version" |
cfdbc2e1 VG |
288 | default ARC_MMU_V3 if ARC_CPU_770 |
289 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 290 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 | 291 | |
c583ee4f VG |
292 | if ISA_ARCOMPACT |
293 | ||
cfdbc2e1 VG |
294 | config ARC_MMU_V1 |
295 | bool "MMU v1" | |
296 | help | |
297 | Orig ARC700 MMU | |
298 | ||
299 | config ARC_MMU_V2 | |
300 | bool "MMU v2" | |
301 | help | |
302 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio | |
303 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. | |
304 | ||
305 | config ARC_MMU_V3 | |
306 | bool "MMU v3" | |
307 | depends on ARC_CPU_770 | |
308 | help | |
309 | Introduced with ARC700 4.10: New Features | |
310 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
311 | Shared Address Spaces (SASID) | |
312 | ||
c583ee4f VG |
313 | endif |
314 | ||
d7a512bf VG |
315 | config ARC_MMU_V4 |
316 | bool "MMU v4" | |
317 | depends on ISA_ARCV2 | |
318 | ||
cfdbc2e1 VG |
319 | endchoice |
320 | ||
321 | ||
322 | choice | |
323 | prompt "MMU Page Size" | |
324 | default ARC_PAGE_SIZE_8K | |
325 | ||
326 | config ARC_PAGE_SIZE_8K | |
327 | bool "8KB" | |
328 | help | |
329 | Choose between 8k vs 16k | |
330 | ||
331 | config ARC_PAGE_SIZE_16K | |
332 | bool "16KB" | |
450ed0db | 333 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
334 | |
335 | config ARC_PAGE_SIZE_4K | |
336 | bool "4KB" | |
450ed0db | 337 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
338 | |
339 | endchoice | |
340 | ||
1f6ccfff VG |
341 | if ISA_ARCOMPACT |
342 | ||
4788a594 VG |
343 | config ARC_COMPACT_IRQ_LEVELS |
344 | bool "ARCompact IRQ Priorities: High(2)/Low(1)" | |
345 | default n | |
346 | # Timer HAS to be high priority, for any other high priority config | |
347 | select ARC_IRQ3_LV2 | |
41195d23 VG |
348 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
349 | depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 | |
4788a594 VG |
350 | |
351 | if ARC_COMPACT_IRQ_LEVELS | |
352 | ||
353 | config ARC_IRQ3_LV2 | |
354 | bool | |
355 | ||
356 | config ARC_IRQ5_LV2 | |
357 | bool | |
358 | ||
359 | config ARC_IRQ6_LV2 | |
360 | bool | |
361 | ||
1f6ccfff | 362 | endif #ARC_COMPACT_IRQ_LEVELS |
4788a594 | 363 | |
cfdbc2e1 VG |
364 | config ARC_FPU_SAVE_RESTORE |
365 | bool "Enable FPU state persistence across context switch" | |
366 | default n | |
367 | help | |
368 | Double Precision Floating Point unit had dedictaed regs which | |
369 | need to be saved/restored across context-switch. | |
370 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
371 | hardware pieces to allow software to conditionally save/restore, | |
372 | based on actual usage of FPU by a task. Thus our implemn does | |
373 | this for all tasks in system. | |
374 | ||
1f6ccfff VG |
375 | endif #ISA_ARCOMPACT |
376 | ||
fbf8e13d VG |
377 | config ARC_CANT_LLSC |
378 | def_bool n | |
379 | ||
cfdbc2e1 VG |
380 | config ARC_HAS_LLSC |
381 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
382 | default y | |
14a0abfc | 383 | depends on !ARC_CANT_LLSC |
cfdbc2e1 | 384 | |
e78fdfef VG |
385 | config ARC_STAR_9000923308 |
386 | bool "Workaround for llock/scond livelock" | |
387 | default y | |
388 | depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC | |
389 | ||
cfdbc2e1 VG |
390 | config ARC_HAS_SWAPE |
391 | bool "Insn: SWAPE (endian-swap)" | |
392 | default y | |
cfdbc2e1 | 393 | |
1f6ccfff VG |
394 | if ISA_ARCV2 |
395 | ||
396 | config ARC_HAS_LL64 | |
397 | bool "Insn: 64bit LDD/STD" | |
398 | help | |
399 | Enable gcc to generate 64-bit load/store instructions | |
400 | ISA mandates even/odd registers to allow encoding of two | |
401 | dest operands with 2 possible source operands. | |
402 | default y | |
403 | ||
d05a76ab AB |
404 | config ARC_HAS_DIV_REM |
405 | bool "Insn: div, divu, rem, remu" | |
406 | default y | |
407 | ||
aa93e8ef VG |
408 | config ARC_HAS_RTC |
409 | bool "Local 64-bit r/o cycle counter" | |
410 | default n | |
411 | depends on !SMP | |
412 | ||
72d72880 VG |
413 | config ARC_HAS_GRTC |
414 | bool "SMP synchronized 64-bit cycle counter" | |
415 | default y | |
416 | depends on SMP | |
417 | ||
1f6ccfff VG |
418 | config ARC_NUMBER_OF_INTERRUPTS |
419 | int "Number of interrupts" | |
420 | range 8 240 | |
421 | default 32 | |
422 | help | |
423 | This defines the number of interrupts on the ARCv2HS core. | |
424 | It affects the size of vector table. | |
425 | The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable | |
426 | in hardware, it keep things simple for Linux to assume they are always | |
427 | present. | |
428 | ||
429 | endif # ISA_ARCV2 | |
430 | ||
cfdbc2e1 VG |
431 | endmenu # "ARC CPU Configuration" |
432 | ||
cfdbc2e1 VG |
433 | config LINUX_LINK_BASE |
434 | hex "Linux Link Address" | |
435 | default "0x80000000" | |
436 | help | |
437 | ARC700 divides the 32 bit phy address space into two equal halves | |
438 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
439 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
440 | Typically Linux kernel is linked at the start of untransalted addr, | |
441 | hence the default value of 0x8zs. | |
442 | However some customers have peripherals mapped at this addr, so | |
443 | Linux needs to be scooted a bit. | |
444 | If you don't know what the above means, leave this setting alone. | |
ff1c0b6a | 445 | This needs to match memory start address specified in Device Tree |
cfdbc2e1 | 446 | |
45890f6d VG |
447 | config HIGHMEM |
448 | bool "High Memory Support" | |
449 | help | |
450 | With ARC 2G:2G address split, only upper 2G is directly addressable by | |
451 | kernel. Enable this to potentially allow access to rest of 2G and PAE | |
452 | in future | |
453 | ||
5a364c2a VG |
454 | config ARC_HAS_PAE40 |
455 | bool "Support for the 40-bit Physical Address Extension" | |
456 | default n | |
457 | depends on ISA_ARCV2 | |
458 | select HIGHMEM | |
459 | help | |
460 | Enable access to physical memory beyond 4G, only supported on | |
461 | ARC cores with 40 bit Physical Addressing support | |
462 | ||
463 | config ARCH_PHYS_ADDR_T_64BIT | |
464 | def_bool ARC_HAS_PAE40 | |
465 | ||
466 | config ARCH_DMA_ADDR_T_64BIT | |
467 | bool | |
468 | ||
080c3747 VG |
469 | config ARC_CURR_IN_REG |
470 | bool "Dedicate Register r25 for current_task pointer" | |
471 | default y | |
472 | help | |
473 | This reserved Register R25 to point to Current Task in | |
474 | kernel mode. This saves memory access for each such access | |
475 | ||
2e651ea1 | 476 | |
1736a56f | 477 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 478 | bool "Emulate unaligned memory access (userspace only)" |
1f6ccfff | 479 | default N |
2e651ea1 VG |
480 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
481 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 482 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
483 | help |
484 | This enables misaligned 16 & 32 bit memory access from user space. | |
485 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
486 | potential bugs in code | |
487 | ||
cfdbc2e1 VG |
488 | config HZ |
489 | int "Timer Frequency" | |
490 | default 100 | |
491 | ||
cbe056f7 VG |
492 | config ARC_METAWARE_HLINK |
493 | bool "Support for Metaware debugger assisted Host access" | |
494 | default n | |
495 | help | |
496 | This options allows a Linux userland apps to directly access | |
497 | host file system (open/creat/read/write etc) with help from | |
498 | Metaware Debugger. This can come in handy for Linux-host communication | |
499 | when there is no real usable peripheral such as EMAC. | |
500 | ||
cfdbc2e1 VG |
501 | menuconfig ARC_DBG |
502 | bool "ARC debugging" | |
503 | default y | |
504 | ||
aa6083ed VG |
505 | if ARC_DBG |
506 | ||
854a0d95 VG |
507 | config ARC_DW2_UNWIND |
508 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
509 | default y |
510 | select KALLSYMS | |
511 | help | |
512 | Compiles the kernel with DWARF unwind information and can be used | |
513 | to get stack backtraces. | |
514 | ||
515 | If you say Y here the resulting kernel image will be slightly larger | |
516 | but not slower, and it will give very useful debugging information. | |
517 | If you don't debug the kernel, you can say N, but we may not be able | |
518 | to solve problems without frame unwind information | |
519 | ||
cfdbc2e1 VG |
520 | config ARC_DBG_TLB_PARANOIA |
521 | bool "Paranoia Checks in Low Level TLB Handlers" | |
cfdbc2e1 VG |
522 | default n |
523 | ||
524 | config ARC_DBG_TLB_MISS_COUNT | |
525 | bool "Profile TLB Misses" | |
526 | default n | |
527 | select DEBUG_FS | |
cfdbc2e1 VG |
528 | help |
529 | Counts number of I and D TLB Misses and exports them via Debugfs | |
530 | The counters can be cleared via Debugfs as well | |
531 | ||
aa6083ed VG |
532 | if SMP |
533 | ||
534 | config ARC_IPI_DBG | |
535 | bool "Debug Inter Core interrupts" | |
536 | default n | |
537 | ||
538 | endif | |
539 | ||
540 | endif | |
541 | ||
036b2c56 VG |
542 | config ARC_UBOOT_SUPPORT |
543 | bool "Support uboot arg Handling" | |
544 | default n | |
545 | help | |
546 | ARC Linux by default checks for uboot provided args as pointers to | |
547 | external cmdline or DTB. This however breaks in absence of uboot, | |
548 | when booting from Metaware debugger directly, as the registers are | |
549 | not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus | |
550 | registers look like uboot args to kernel which then chokes. | |
551 | So only enable the uboot arg checking/processing if users are sure | |
552 | of uboot being in play. | |
553 | ||
999159a5 VG |
554 | config ARC_BUILTIN_DTB_NAME |
555 | string "Built in DTB" | |
556 | help | |
557 | Set the name of the DTB to embed in the vmlinux binary | |
558 | Leaving it blank selects the minimal "skeleton" dtb | |
559 | ||
cfdbc2e1 VG |
560 | source "kernel/Kconfig.preempt" |
561 | ||
5628832f VG |
562 | menu "Executable file formats" |
563 | source "fs/Kconfig.binfmt" | |
564 | endmenu | |
565 | ||
cfdbc2e1 VG |
566 | endmenu # "ARC Architecture Configuration" |
567 | ||
568 | source "mm/Kconfig" | |
569 | source "net/Kconfig" | |
570 | source "drivers/Kconfig" | |
571 | source "fs/Kconfig" | |
572 | source "arch/arc/Kconfig.debug" | |
573 | source "security/Kconfig" | |
574 | source "crypto/Kconfig" | |
575 | source "lib/Kconfig" | |
996bad6c | 576 | source "kernel/power/Kconfig" |