[mirror_ubuntu-artful-kernel.git] / arch / arc / boot / dts / abilis_tb10x.dtsi

/*
 * Abilis Systems TB10X SOC device tree
 *
 * Copyright (C) Abilis Systems 2013
 *
 * Author: Christian Ruppert <christian.ruppert@abilis.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */


/ {
	compatible		= "abilis,arc-tb10x";
	#address-cells		= <1>;
	#size-cells		= <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "snps,arc770d";
			reg = <0>;
		};
	};

	/* TIMER0 with interrupt for clockevent */
	timer0 {
		compatible = "snps,arc-timer";
		interrupts = <3>;
		interrupt-parent = <&intc>;
		clocks = <&cpu_clk>;
	};

	/* TIMER1 for free running clocksource */
	timer1 {
		compatible = "snps,arc-timer";
		clocks = <&cpu_clk>;
	};

	soc100 {
		#address-cells	= <1>;
		#size-cells	= <1>;
		device_type	= "soc";
		ranges		= <0xfe000000 0xfe000000 0x02000000
				0x000F0000 0x000F0000 0x00010000>;
		compatible	= "abilis,tb10x", "simple-bus";

		pll0: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "pll0";
		};
		cpu_clk: clkdiv_cpu {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&pll0>;
			clock-output-names = "cpu_clk";
		};
		ahb_clk: clkdiv_ahb {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&pll0>;
			clock-output-names = "ahb_clk";
		};

		iomux: iomux@FF10601c {
			compatible = "abilis,tb10x-iomux";
			#gpio-range-cells = <3>;
			reg = <0xFF10601c 0x4>;
		};

		intc: interrupt-controller {
			compatible = "snps,arc700-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};
		tb10x_ictl: pic@fe002000 {
			compatible = "abilis,tb10x-ictl";
			reg = <0xFE002000 0x20>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
					20 21 22 23 24 25 26 27 28 29 30 31>;
		};

		uart@FF100000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xFF100000 0x100>;
			clock-frequency = <166666666>;
			interrupts = <25 8>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupt-parent = <&tb10x_ictl>;
		};
		ethernet@FE100000 {
			compatible = "snps,dwmac-3.70a","snps,dwmac";
			reg = <0xFE100000 0x1058>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <6 8>;
			interrupt-names = "macirq";
			clocks = <&ahb_clk>;
			clock-names = "stmmaceth";
		};
		dma@FE000000 {
			compatible = "snps,dma-spear1340";
			reg = <0xFE000000 0x400>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <14 8>;
			dma-channels = <6>;
			dma-requests = <0>;
			dma-masters = <1>;
			#dma-cells = <3>;
			chan_allocation_order = <0>;
			chan_priority = <1>;
			block_size = <0x7ff>;
			data_width = <2>;
			clocks = <&ahb_clk>;
			clock-names = "hclk";
		};

		i2c0: i2c@FF120000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xFF120000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <12 8>;
			clocks = <&ahb_clk>;
		};
		i2c1: i2c@FF121000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xFF121000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <12 8>;
			clocks = <&ahb_clk>;
		};
		i2c2: i2c@FF122000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xFF122000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <12 8>;
			clocks = <&ahb_clk>;
		};
		i2c3: i2c@FF123000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xFF123000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <12 8>;
			clocks = <&ahb_clk>;
		};
		i2c4: i2c@FF124000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xFF124000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <12 8>;
			clocks = <&ahb_clk>;
		};

		spi0: spi@0xFE010000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "abilis,tb100-spi";
			num-cs = <1>;
			reg = <0xFE010000 0x20>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <26 8>;
			clocks = <&ahb_clk>;
		};
		spi1: spi@0xFE011000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "abilis,tb100-spi";
			num-cs = <2>;
			reg = <0xFE011000 0x20>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <10 8>;
			clocks = <&ahb_clk>;
		};

		tb10x_tsm: tb10x-tsm@ff316000 {
			compatible = "abilis,tb100-tsm";
			reg = <0xff316000 0x400>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <17 8>;
			output-clkdiv = <4>;
			global-packet-delay = <0x21>;
			port-packet-delay = <0>;
		};
		tb10x_stream_proc: tb10x-stream-proc {
			compatible = "abilis,tb100-streamproc";
			reg =   <0xfff00000 0x200>,
				<0x000f0000 0x10000>,
				<0xfff00200 0x105>,
				<0xff10600c 0x1>,
				<0xfe001018 0x1>;
			reg-names =     "mbox",
					"sp_iccm",
					"mbox_irq",
					"cpuctrl",
					"a6it_int_force";
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <20 2>, <19 2>;
			interrupt-names = "cmd_irq", "event_irq";
		};
		tb10x_mdsc0: tb10x-mdscr@FF300000 {
			compatible = "abilis,tb100-mdscr";
			reg = <0xFF300000 0x7000>;
			tb100-mdscr-manage-tsin;
		};
		tb10x_mscr0: tb10x-mdscr@FF307000 {
			compatible = "abilis,tb100-mdscr";
			reg = <0xFF307000 0x7000>;
		};
		tb10x_scr0: tb10x-mdscr@ff30e000 {
			compatible = "abilis,tb100-mdscr";
			reg = <0xFF30e000 0x4000>;
			tb100-mdscr-manage-tsin;
		};
		tb10x_scr1: tb10x-mdscr@ff312000 {
			compatible = "abilis,tb100-mdscr";
			reg = <0xFF312000 0x4000>;
			tb100-mdscr-manage-tsin;
		};
		tb10x_wfb: tb10x-wfb@ff319000 {
			compatible = "abilis,tb100-wfb";
			reg = <0xff319000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <16 8>;
		};
	};
};
Commit	Line	Data
2eb9504b CR	1	/*
	2	* Abilis Systems TB10X SOC device tree
	3	*
	4	* Copyright (C) Abilis Systems 2013
	5	*
	6	* Author: Christian Ruppert <christian.ruppert@abilis.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
2eb9504b CR	22
	23	/ {
	24	compatible = "abilis,arc-tb10x";
	25	#address-cells = <1>;
	26	#size-cells = <1>;
	27
	28	cpus {
	29	#address-cells = <1>;
	30	#size-cells = <0>;
	31	cpu@0 {
	32	device_type = "cpu";
	33	compatible = "snps,arc770d";
	34	reg = <0>;
	35	};
	36	};
	37
7ec9f34a VG	38	/* TIMER0 with interrupt for clockevent */
	39	timer0 {
	40	compatible = "snps,arc-timer";
	41	interrupts = <3>;
	42	interrupt-parent = <&intc>;
	43	clocks = <&cpu_clk>;
	44	};
	45
	46	/* TIMER1 for free running clocksource */
	47	timer1 {
	48	compatible = "snps,arc-timer";
	49	clocks = <&cpu_clk>;
	50	};
	51
2eb9504b CR	52	soc100 {
	53	#address-cells = <1>;
	54	#size-cells = <1>;
	55	device_type = "soc";
	56	ranges = <0xfe000000 0xfe000000 0x02000000
	57	0x000F0000 0x000F0000 0x00010000>;
	58	compatible = "abilis,tb10x", "simple-bus";
	59
	60	pll0: oscillator {
	61	compatible = "fixed-clock";
	62	#clock-cells = <0>;
	63	clock-output-names = "pll0";
	64	};
	65	cpu_clk: clkdiv_cpu {
0dfad77d	66	compatible = "fixed-factor-clock";
2eb9504b CR	67	#clock-cells = <0>;
	68	clocks = <&pll0>;
	69	clock-output-names = "cpu_clk";
	70	};
	71	ahb_clk: clkdiv_ahb {
0dfad77d	72	compatible = "fixed-factor-clock";
2eb9504b CR	73	#clock-cells = <0>;
	74	clocks = <&pll0>;
	75	clock-output-names = "ahb_clk";
	76	};
	77
	78	iomux: iomux@FF10601c {
2eb9504b	79	compatible = "abilis,tb10x-iomux";
9c8e612d	80	#gpio-range-cells = <3>;
2eb9504b CR	81	reg = <0xFF10601c 0x4>;
	82	};
	83
	84	intc: interrupt-controller {
	85	compatible = "snps,arc700-intc";
	86	interrupt-controller;
	87	#interrupt-cells = <1>;
	88	};
	89	tb10x_ictl: pic@fe002000 {
723e2b80	90	compatible = "abilis,tb10x-ictl";
2eb9504b CR	91	reg = <0xFE002000 0x20>;
	92	interrupt-controller;
	93	#interrupt-cells = <2>;
	94	interrupt-parent = <&intc>;
	95	interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
	96	20 21 22 23 24 25 26 27 28 29 30 31>;
	97	};
	98
	99	uart@FF100000 {
7d19273c	100	compatible = "snps,dw-apb-uart";
2eb9504b CR	101	reg = <0xFF100000 0x100>;
2eb9504b CR	102	clock-frequency = <166666666>;
723e2b80	103	interrupts = <25 8>;
2eb9504b CR	104	reg-shift = <2>;
	105	reg-io-width = <4>;
	106	interrupt-parent = <&tb10x_ictl>;
	107	};
	108	ethernet@FE100000 {
	109	compatible = "snps,dwmac-3.70a","snps,dwmac";
	110	reg = <0xFE100000 0x1058>;
	111	interrupt-parent = <&tb10x_ictl>;
723e2b80	112	interrupts = <6 8>;
2eb9504b CR	113	interrupt-names = "macirq";
	114	clocks = <&ahb_clk>;
	115	clock-names = "stmmaceth";
	116	};
	117	dma@FE000000 {
	118	compatible = "snps,dma-spear1340";
	119	reg = <0xFE000000 0x400>;
	120	interrupt-parent = <&tb10x_ictl>;
723e2b80	121	interrupts = <14 8>;
2eb9504b CR	122	dma-channels = <6>;
	123	dma-requests = <0>;
	124	dma-masters = <1>;
	125	#dma-cells = <3>;
	126	chan_allocation_order = <0>;
	127	chan_priority = <1>;
	128	block_size = <0x7ff>;
d8ded50f	129	data_width = <2>;
2eb9504b CR	130	clocks = <&ahb_clk>;
	131	clock-names = "hclk";
	132	};
	133
	134	i2c0: i2c@FF120000 {
	135	#address-cells = <1>;
	136	#size-cells = <0>;
	137	compatible = "snps,designware-i2c";
	138	reg = <0xFF120000 0x1000>;
	139	interrupt-parent = <&tb10x_ictl>;
723e2b80	140	interrupts = <12 8>;
2eb9504b CR	141	clocks = <&ahb_clk>;
	142	};
	143	i2c1: i2c@FF121000 {
	144	#address-cells = <1>;
	145	#size-cells = <0>;
	146	compatible = "snps,designware-i2c";
	147	reg = <0xFF121000 0x1000>;
	148	interrupt-parent = <&tb10x_ictl>;
723e2b80	149	interrupts = <12 8>;
2eb9504b CR	150	clocks = <&ahb_clk>;
	151	};
	152	i2c2: i2c@FF122000 {
	153	#address-cells = <1>;
	154	#size-cells = <0>;
	155	compatible = "snps,designware-i2c";
	156	reg = <0xFF122000 0x1000>;
	157	interrupt-parent = <&tb10x_ictl>;
723e2b80	158	interrupts = <12 8>;
2eb9504b CR	159	clocks = <&ahb_clk>;
	160	};
	161	i2c3: i2c@FF123000 {
	162	#address-cells = <1>;
	163	#size-cells = <0>;
	164	compatible = "snps,designware-i2c";
	165	reg = <0xFF123000 0x1000>;
	166	interrupt-parent = <&tb10x_ictl>;
723e2b80	167	interrupts = <12 8>;
2eb9504b CR	168	clocks = <&ahb_clk>;
	169	};
	170	i2c4: i2c@FF124000 {
	171	#address-cells = <1>;
	172	#size-cells = <0>;
	173	compatible = "snps,designware-i2c";
	174	reg = <0xFF124000 0x1000>;
	175	interrupt-parent = <&tb10x_ictl>;
723e2b80	176	interrupts = <12 8>;
2eb9504b CR	177	clocks = <&ahb_clk>;
	178	};
	179
	180	spi0: spi@0xFE010000 {
	181	#address-cells = <1>;
	182	#size-cells = <0>;
	183	cell-index = <0>;
	184	compatible = "abilis,tb100-spi";
	185	num-cs = <1>;
	186	reg = <0xFE010000 0x20>;
	187	interrupt-parent = <&tb10x_ictl>;
723e2b80	188	interrupts = <26 8>;
2eb9504b CR	189	clocks = <&ahb_clk>;
	190	};
	191	spi1: spi@0xFE011000 {
	192	#address-cells = <1>;
	193	#size-cells = <0>;
	194	cell-index = <1>;
7d19273c	195	compatible = "abilis,tb100-spi";
2eb9504b CR	196	num-cs = <2>;
	197	reg = <0xFE011000 0x20>;
	198	interrupt-parent = <&tb10x_ictl>;
723e2b80	199	interrupts = <10 8>;
2eb9504b CR	200	clocks = <&ahb_clk>;
	201	};
	202
	203	tb10x_tsm: tb10x-tsm@ff316000 {
	204	compatible = "abilis,tb100-tsm";
	205	reg = <0xff316000 0x400>;
	206	interrupt-parent = <&tb10x_ictl>;
723e2b80	207	interrupts = <17 8>;
2eb9504b CR	208	output-clkdiv = <4>;
	209	global-packet-delay = <0x21>;
	210	port-packet-delay = <0>;
	211	};
	212	tb10x_stream_proc: tb10x-stream-proc {
	213	compatible = "abilis,tb100-streamproc";
	214	reg = <0xfff00000 0x200>,
	215	<0x000f0000 0x10000>,
	216	<0xfff00200 0x105>,
	217	<0xff10600c 0x1>,
	218	<0xfe001018 0x1>;
	219	reg-names = "mbox",
	220	"sp_iccm",
	221	"mbox_irq",
	222	"cpuctrl",
	223	"a6it_int_force";
	224	interrupt-parent = <&tb10x_ictl>;
723e2b80	225	interrupts = <20 2>, <19 2>;
2eb9504b CR	226	interrupt-names = "cmd_irq", "event_irq";
	227	};
	228	tb10x_mdsc0: tb10x-mdscr@FF300000 {
	229	compatible = "abilis,tb100-mdscr";
	230	reg = <0xFF300000 0x7000>;
	231	tb100-mdscr-manage-tsin;
	232	};
	233	tb10x_mscr0: tb10x-mdscr@FF307000 {
	234	compatible = "abilis,tb100-mdscr";
	235	reg = <0xFF307000 0x7000>;
	236	};
	237	tb10x_scr0: tb10x-mdscr@ff30e000 {
	238	compatible = "abilis,tb100-mdscr";
	239	reg = <0xFF30e000 0x4000>;
	240	tb100-mdscr-manage-tsin;
	241	};
	242	tb10x_scr1: tb10x-mdscr@ff312000 {
	243	compatible = "abilis,tb100-mdscr";
	244	reg = <0xFF312000 0x4000>;
	245	tb100-mdscr-manage-tsin;
	246	};
	247	tb10x_wfb: tb10x-wfb@ff319000 {
	248	compatible = "abilis,tb100-wfb";
	249	reg = <0xff319000 0x1000>;
	250	interrupt-parent = <&tb10x_ictl>;
723e2b80	251	interrupts = <16 8>;
2eb9504b CR	252	};
	253	};
	254	};