]>
Commit | Line | Data |
---|---|---|
5fa2daaa VG |
1 | /* |
2 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * Device tree for AXC003 CPU card: HS38x UP configuration | |
11 | */ | |
12 | ||
13 | / { | |
14 | compatible = "snps,arc"; | |
e2fc61f3 | 15 | clock-frequency = <90000000>; |
5fa2daaa VG |
16 | #address-cells = <1>; |
17 | #size-cells = <1>; | |
18 | ||
19 | cpu_card { | |
20 | compatible = "simple-bus"; | |
21 | #address-cells = <1>; | |
22 | #size-cells = <1>; | |
23 | ||
24 | ranges = <0x00000000 0xf0000000 0x10000000>; | |
25 | ||
26 | cpu_intc: archs-intc@cpu { | |
27 | compatible = "snps,archs-intc"; | |
28 | interrupt-controller; | |
29 | #interrupt-cells = <1>; | |
30 | }; | |
31 | ||
32 | /* | |
33 | * this GPIO block ORs all interrupts on CPU card (creg,..) | |
34 | * to uplink only 1 IRQ to ARC core intc | |
35 | */ | |
36 | dw-apb-gpio@0x2000 { | |
37 | compatible = "snps,dw-apb-gpio"; | |
38 | reg = < 0x2000 0x80 >; | |
39 | #address-cells = <1>; | |
40 | #size-cells = <0>; | |
41 | ||
42 | ictl_intc: gpio-controller@0 { | |
43 | compatible = "snps,dw-apb-gpio-port"; | |
44 | gpio-controller; | |
45 | #gpio-cells = <2>; | |
46 | snps,nr-gpios = <30>; | |
47 | reg = <0>; | |
48 | interrupt-controller; | |
49 | #interrupt-cells = <2>; | |
50 | interrupt-parent = <&cpu_intc>; | |
51 | interrupts = <25>; | |
52 | }; | |
53 | }; | |
54 | ||
55 | debug_uart: dw-apb-uart@0x5000 { | |
56 | compatible = "snps,dw-apb-uart"; | |
57 | reg = <0x5000 0x100>; | |
58 | clock-frequency = <33333000>; | |
59 | interrupt-parent = <&ictl_intc>; | |
60 | interrupts = <2 4>; | |
61 | baud = <115200>; | |
62 | reg-shift = <2>; | |
63 | reg-io-width = <4>; | |
64 | }; | |
65 | ||
66 | arcpct0: pct { | |
67 | compatible = "snps,archs-pct"; | |
68 | #interrupt-cells = <1>; | |
69 | interrupt-parent = <&cpu_intc>; | |
70 | interrupts = <20>; | |
71 | }; | |
72 | }; | |
73 | ||
74 | /* | |
75 | * This INTC is actually connected to DW APB GPIO | |
76 | * which acts as a wire between MB INTC and CPU INTC. | |
77 | * GPIO INTC is configured in platform init code | |
78 | * and here we mimic direct connection from MB INTC to | |
79 | * CPU INTC, thus we set "interrupts = <7>" instead of | |
80 | * "interrupts = <12>" | |
81 | * | |
82 | * This intc actually resides on MB, but we move it here to | |
83 | * avoid duplicating the MB dtsi file given that IRQ from | |
84 | * this intc to cpu intc are different for axs101 and axs103 | |
85 | */ | |
86 | mb_intc: dw-apb-ictl@0xe0012000 { | |
87 | #interrupt-cells = <1>; | |
88 | compatible = "snps,dw-apb-ictl"; | |
89 | reg = < 0xe0012000 0x200 >; | |
90 | interrupt-controller; | |
91 | interrupt-parent = <&cpu_intc>; | |
92 | interrupts = < 24 >; | |
93 | }; | |
94 | ||
95 | memory { | |
96 | #address-cells = <1>; | |
97 | #size-cells = <1>; | |
98 | ranges = <0x00000000 0x80000000 0x40000000>; | |
99 | device_type = "memory"; | |
100 | reg = <0x00000000 0x20000000>; /* 512MiB */ | |
101 | }; | |
102 | }; |