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[mirror_ubuntu-focal-kernel.git] / arch / arc / boot / dts / axc003.dtsi
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1/*
2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device tree for AXC003 CPU card: HS38x UP configuration
11 */
12
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13/include/ "skeleton_hs.dtsi"
14
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15/ {
16 compatible = "snps,arc";
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17 #address-cells = <2>;
18 #size-cells = <2>;
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19
20 cpu_card {
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
24
f862b315 25 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
5fa2daaa 26
f6a09bac 27 input_clk: input-clk {
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28 #clock-cells = <0>;
29 compatible = "fixed-clock";
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30 clock-frequency = <33333333>;
31 };
32
33 core_clk: core-clk@80 {
34 compatible = "snps,axs10x-arc-pll-clock";
35 reg = <0x80 0x10>, <0x100 0x10>;
36 #clock-cells = <0>;
37 clocks = <&input_clk>;
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38
39 /*
40 * Set initial core pll output frequency to 90MHz.
41 * It will be applied at the core pll driver probing
42 * on early boot.
43 */
44 assigned-clocks = <&core_clk>;
45 assigned-clock-rates = <90000000>;
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46 };
47
9ba7648c 48 core_intc: archs-intc@cpu {
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49 compatible = "snps,archs-intc";
50 interrupt-controller;
51 #interrupt-cells = <1>;
52 };
53
54 /*
55 * this GPIO block ORs all interrupts on CPU card (creg,..)
56 * to uplink only 1 IRQ to ARC core intc
57 */
58 dw-apb-gpio@0x2000 {
59 compatible = "snps,dw-apb-gpio";
60 reg = < 0x2000 0x80 >;
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 ictl_intc: gpio-controller@0 {
65 compatible = "snps,dw-apb-gpio-port";
66 gpio-controller;
67 #gpio-cells = <2>;
68 snps,nr-gpios = <30>;
69 reg = <0>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
9ba7648c 72 interrupt-parent = <&core_intc>;
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73 interrupts = <25>;
74 };
75 };
76
77 debug_uart: dw-apb-uart@0x5000 {
78 compatible = "snps,dw-apb-uart";
79 reg = <0x5000 0x100>;
80 clock-frequency = <33333000>;
81 interrupt-parent = <&ictl_intc>;
82 interrupts = <2 4>;
83 baud = <115200>;
84 reg-shift = <2>;
85 reg-io-width = <4>;
86 };
87
88 arcpct0: pct {
89 compatible = "snps,archs-pct";
90 #interrupt-cells = <1>;
9ba7648c 91 interrupt-parent = <&core_intc>;
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92 interrupts = <20>;
93 };
94 };
95
96 /*
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97 * The DW APB ICTL intc on MB is connected to CPU intc via a
98 * DT "invisible" DW APB GPIO block, configured to simply pass thru
99 * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
100 *
101 * So here we mimic a direct connection betwen them, ignoring the
102 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
103 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
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104 *
105 * This intc actually resides on MB, but we move it here to
106 * avoid duplicating the MB dtsi file given that IRQ from
107 * this intc to cpu intc are different for axs101 and axs103
108 */
109 mb_intc: dw-apb-ictl@0xe0012000 {
110 #interrupt-cells = <1>;
111 compatible = "snps,dw-apb-ictl";
f862b315 112 reg = < 0x0 0xe0012000 0x0 0x200 >;
5fa2daaa 113 interrupt-controller;
9ba7648c 114 interrupt-parent = <&core_intc>;
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115 interrupts = < 24 >;
116 };
117
118 memory {
5fa2daaa 119 device_type = "memory";
9ed68785 120 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
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121 reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
122 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
5fa2daaa 123 };
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124
125 reserved-memory {
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126 #address-cells = <2>;
127 #size-cells = <2>;
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128 ranges;
129 /*
130 * Move frame buffer out of IOC aperture (0x8z-0xAz).
131 */
132 frame_buffer: frame_buffer@be000000 {
133 compatible = "shared-dma-pool";
f862b315 134 reg = <0x0 0xbe000000 0x0 0x2000000>;
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135 no-map;
136 };
137 };
5fa2daaa 138};