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1 | /* |
2 | * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc | |
11 | */ | |
12 | ||
2e8cd938 VG |
13 | /include/ "skeleton_hs_idu.dtsi" |
14 | ||
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15 | / { |
16 | compatible = "snps,arc"; | |
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17 | #address-cells = <2>; |
18 | #size-cells = <2>; | |
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19 | |
20 | cpu_card { | |
21 | compatible = "simple-bus"; | |
22 | #address-cells = <1>; | |
23 | #size-cells = <1>; | |
24 | ||
f862b315 | 25 | ranges = <0x00000000 0x0 0xf0000000 0x10000000>; |
5fa2daaa | 26 | |
f6a09bac | 27 | input_clk: input-clk { |
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28 | #clock-cells = <0>; |
29 | compatible = "fixed-clock"; | |
f6a09bac EP |
30 | clock-frequency = <33333333>; |
31 | }; | |
32 | ||
33 | core_clk: core-clk@80 { | |
34 | compatible = "snps,axs10x-arc-pll-clock"; | |
35 | reg = <0x80 0x10>, <0x100 0x10>; | |
36 | #clock-cells = <0>; | |
37 | clocks = <&input_clk>; | |
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38 | |
39 | /* | |
40 | * Set initial core pll output frequency to 100MHz. | |
41 | * It will be applied at the core pll driver probing | |
42 | * on early boot. | |
43 | */ | |
44 | assigned-clocks = <&core_clk>; | |
45 | assigned-clock-rates = <100000000>; | |
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46 | }; |
47 | ||
9ba7648c | 48 | core_intc: archs-intc@cpu { |
5fa2daaa VG |
49 | compatible = "snps,archs-intc"; |
50 | interrupt-controller; | |
51 | #interrupt-cells = <1>; | |
52 | }; | |
53 | ||
54 | idu_intc: idu-interrupt-controller { | |
55 | compatible = "snps,archs-idu-intc"; | |
56 | interrupt-controller; | |
9ba7648c | 57 | interrupt-parent = <&core_intc>; |
ec69b269 | 58 | #interrupt-cells = <1>; |
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59 | }; |
60 | ||
61 | /* | |
62 | * this GPIO block ORs all interrupts on CPU card (creg,..) | |
63 | * to uplink only 1 IRQ to ARC core intc | |
64 | */ | |
65 | dw-apb-gpio@0x2000 { | |
66 | compatible = "snps,dw-apb-gpio"; | |
67 | reg = < 0x2000 0x80 >; | |
68 | #address-cells = <1>; | |
69 | #size-cells = <0>; | |
70 | ||
71 | ictl_intc: gpio-controller@0 { | |
72 | compatible = "snps,dw-apb-gpio-port"; | |
73 | gpio-controller; | |
74 | #gpio-cells = <2>; | |
75 | snps,nr-gpios = <30>; | |
76 | reg = <0>; | |
77 | interrupt-controller; | |
78 | #interrupt-cells = <2>; | |
79 | interrupt-parent = <&idu_intc>; | |
ec69b269 | 80 | interrupts = <1>; |
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81 | }; |
82 | }; | |
83 | ||
84 | debug_uart: dw-apb-uart@0x5000 { | |
85 | compatible = "snps,dw-apb-uart"; | |
86 | reg = <0x5000 0x100>; | |
87 | clock-frequency = <33333000>; | |
88 | interrupt-parent = <&ictl_intc>; | |
89 | interrupts = <2 4>; | |
90 | baud = <115200>; | |
91 | reg-shift = <2>; | |
92 | reg-io-width = <4>; | |
93 | }; | |
94 | ||
95 | arcpct0: pct { | |
96 | compatible = "snps,archs-pct"; | |
97 | #interrupt-cells = <1>; | |
9ba7648c | 98 | interrupt-parent = <&core_intc>; |
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99 | interrupts = <20>; |
100 | }; | |
101 | }; | |
102 | ||
103 | /* | |
104 | * This INTC is actually connected to DW APB GPIO | |
105 | * which acts as a wire between MB INTC and CPU INTC. | |
106 | * GPIO INTC is configured in platform init code | |
107 | * and here we mimic direct connection from MB INTC to | |
108 | * CPU INTC, thus we set "interrupts = <0 1>" instead of | |
109 | * "interrupts = <12>" | |
110 | * | |
111 | * This intc actually resides on MB, but we move it here to | |
112 | * avoid duplicating the MB dtsi file given that IRQ from | |
113 | * this intc to cpu intc are different for axs101 and axs103 | |
114 | */ | |
115 | mb_intc: dw-apb-ictl@0xe0012000 { | |
116 | #interrupt-cells = <1>; | |
117 | compatible = "snps,dw-apb-ictl"; | |
f862b315 | 118 | reg = < 0x0 0xe0012000 0x0 0x200 >; |
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119 | interrupt-controller; |
120 | interrupt-parent = <&idu_intc>; | |
ec69b269 | 121 | interrupts = <0>; |
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122 | }; |
123 | ||
124 | memory { | |
5fa2daaa | 125 | device_type = "memory"; |
9ed68785 | 126 | /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ |
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127 | reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */ |
128 | 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */ | |
5fa2daaa | 129 | }; |
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130 | |
131 | reserved-memory { | |
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132 | #address-cells = <2>; |
133 | #size-cells = <2>; | |
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134 | ranges; |
135 | /* | |
136 | * Move frame buffer out of IOC aperture (0x8z-0xAz). | |
137 | */ | |
138 | frame_buffer: frame_buffer@be000000 { | |
139 | compatible = "shared-dma-pool"; | |
f862b315 | 140 | reg = <0x0 0xbe000000 0x0 0x2000000>; |
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141 | no-map; |
142 | }; | |
143 | }; | |
5fa2daaa | 144 | }; |