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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
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2 | /* |
3 | * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) | |
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4 | */ |
5 | /dts-v1/; | |
6 | ||
7 | /include/ "skeleton_hs_idu.dtsi" | |
8 | ||
9 | / { | |
10 | model = "snps,zebu_hs-smp"; | |
11 | compatible = "snps,zebu_hs"; | |
12 | #address-cells = <1>; | |
13 | #size-cells = <1>; | |
14 | interrupt-parent = <&core_intc>; | |
15 | ||
16 | memory { | |
17 | device_type = "memory"; | |
18 | reg = <0x80000000 0x20000000>; /* 512 */ | |
19 | }; | |
20 | ||
21 | chosen { | |
8ff3afc1 | 22 | bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; |
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23 | }; |
24 | ||
25 | aliases { | |
26 | serial0 = &uart0; | |
27 | }; | |
28 | ||
29 | fpga { | |
30 | compatible = "simple-bus"; | |
31 | #address-cells = <1>; | |
32 | #size-cells = <1>; | |
33 | ||
34 | /* child and parent address space 1:1 mapped */ | |
35 | ranges; | |
36 | ||
37 | core_clk: core_clk { | |
38 | #clock-cells = <0>; | |
39 | compatible = "fixed-clock"; | |
40 | clock-frequency = <50000000>; /* 50 MHZ */ | |
41 | }; | |
42 | ||
43 | core_intc: interrupt-controller { | |
44 | compatible = "snps,archs-intc"; | |
45 | interrupt-controller; | |
46 | #interrupt-cells = <1>; | |
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47 | }; |
48 | ||
49 | idu_intc: idu-interrupt-controller { | |
50 | compatible = "snps,archs-idu-intc"; | |
51 | interrupt-controller; | |
52 | interrupt-parent = <&core_intc>; | |
ec69b269 | 53 | #interrupt-cells = <1>; |
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54 | }; |
55 | ||
56 | uart0: serial@f0000000 { | |
57 | /* compatible = "ns8250"; Doesn't use FIFOs */ | |
58 | compatible = "ns16550a"; | |
59 | reg = <0xf0000000 0x2000>; | |
60 | interrupt-parent = <&idu_intc>; | |
ec69b269 | 61 | interrupts = <0>; |
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62 | clock-frequency = <50000000>; |
63 | baud = <115200>; | |
64 | reg-shift = <2>; | |
65 | reg-io-width = <4>; | |
66 | no-loopback-test = <1>; | |
67 | }; | |
68 | ||
69 | arcpct0: pct { | |
70 | compatible = "snps,archs-pct"; | |
71 | #interrupt-cells = <1>; | |
72 | interrupts = <20>; | |
73 | }; | |
74 | }; | |
75 | }; |