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Merge tag 'ntb-4.13-bugfixes' of git://github.com/jonmason/ntb
[mirror_ubuntu-artful-kernel.git] / arch / arc / include / asm / mmu.h
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1/*
2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _ASM_ARC_MMU_H
10#define _ASM_ARC_MMU_H
11
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12#ifndef __ASSEMBLY__
13#include <linux/threads.h> /* NR_CPUS */
14#endif
15
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16#if defined(CONFIG_ARC_MMU_V1)
17#define CONFIG_ARC_MMU_VER 1
18#elif defined(CONFIG_ARC_MMU_V2)
19#define CONFIG_ARC_MMU_VER 2
20#elif defined(CONFIG_ARC_MMU_V3)
21#define CONFIG_ARC_MMU_VER 3
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22#elif defined(CONFIG_ARC_MMU_V4)
23#define CONFIG_ARC_MMU_VER 4
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24#endif
25
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26/* MMU Management regs */
27#define ARC_REG_MMU_BCR 0x06f
d7a512bf 28#if (CONFIG_ARC_MMU_VER < 4)
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29#define ARC_REG_TLBPD0 0x405
30#define ARC_REG_TLBPD1 0x406
5a364c2a 31#define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */
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32#define ARC_REG_TLBINDEX 0x407
33#define ARC_REG_TLBCOMMAND 0x408
34#define ARC_REG_PID 0x409
35#define ARC_REG_SCRATCH_DATA0 0x418
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36#else
37#define ARC_REG_TLBPD0 0x460
38#define ARC_REG_TLBPD1 0x461
5a364c2a 39#define ARC_REG_TLBPD1HI 0x463
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40#define ARC_REG_TLBINDEX 0x464
41#define ARC_REG_TLBCOMMAND 0x465
42#define ARC_REG_PID 0x468
43#define ARC_REG_SCRATCH_DATA0 0x46c
44#endif
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45
46/* Bits in MMU PID register */
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47#define __TLB_ENABLE (1 << 31)
48#define __PROG_ENABLE (1 << 30)
49#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE)
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50
51/* Error code if probe fails */
52#define TLB_LKUP_ERR 0x80000000
53
d7a512bf 54#if (CONFIG_ARC_MMU_VER < 4)
483e9bcb 55#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001)
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56#else
57#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000)
58#endif
483e9bcb 59
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60/* TLB Commands */
61#define TLBWrite 0x1
62#define TLBRead 0x2
63#define TLBGetIndex 0x3
64#define TLBProbe 0x4
65
66#if (CONFIG_ARC_MMU_VER >= 2)
67#define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */
68#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */
69#endif
70
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71#if (CONFIG_ARC_MMU_VER >= 4)
72#define TLBInsertEntry 0x7
73#define TLBDeleteEntry 0x8
74#endif
75
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76#ifndef __ASSEMBLY__
77
78typedef struct {
63eca94c 79 unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */
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80} mm_context_t;
81
da1677b0 82#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
5bd87adf 83void tlb_paranoid_check(unsigned int mm_asid, unsigned long address);
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84#else
85#define tlb_paranoid_check(a, b)
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86#endif
87
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88void arc_mmu_init(void);
89extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
07b9b651 90void read_decode_mmu_bcr(void);
da1677b0 91
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92static inline int is_pae40_enabled(void)
93{
94 return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
95}
96
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97extern int pae40_exist_but_not_enab(void);
98
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99#endif /* !__ASSEMBLY__ */
100
f1f3347d 101#endif