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820970a5 VG |
1 | /* |
2 | * Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/interrupt.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/irqdomain.h> | |
14 | #include <linux/irqchip.h> | |
820970a5 VG |
15 | #include <asm/irq.h> |
16 | ||
179cf194 VG |
17 | #define NR_EXCEPTIONS 16 |
18 | ||
19 | struct bcr_irq_arcv2 { | |
20 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
21 | unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8; | |
22 | #else | |
23 | unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3; | |
24 | #endif | |
25 | }; | |
fe7b1099 | 26 | |
820970a5 VG |
27 | /* |
28 | * Early Hardware specific Interrupt setup | |
29 | * -Called very early (start_kernel -> setup_arch -> setup_processor) | |
30 | * -Platform Independent (must for any ARC Core) | |
31 | * -Needed for each CPU (hence not foldable into init_IRQ) | |
32 | */ | |
33 | void arc_init_IRQ(void) | |
34 | { | |
be568e78 | 35 | unsigned int tmp, irq_prio, i; |
179cf194 | 36 | struct bcr_irq_arcv2 irq_bcr; |
dec2b284 | 37 | |
820970a5 VG |
38 | struct aux_irq_ctrl { |
39 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
40 | unsigned int res3:18, save_idx_regs:1, res2:1, | |
41 | save_u_to_u:1, save_lp_regs:1, save_blink:1, | |
42 | res:4, save_nr_gpr_pairs:5; | |
43 | #else | |
44 | unsigned int save_nr_gpr_pairs:5, res:4, | |
45 | save_blink:1, save_lp_regs:1, save_u_to_u:1, | |
46 | res2:1, save_idx_regs:1, res3:18; | |
47 | #endif | |
48 | } ictrl; | |
49 | ||
50 | *(unsigned int *)&ictrl = 0; | |
51 | ||
52 | ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */ | |
53 | ictrl.save_blink = 1; | |
54 | ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */ | |
55 | ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */ | |
56 | ictrl.save_idx_regs = 1; /* JLI, LDI, EI */ | |
57 | ||
58 | WRITE_AUX(AUX_IRQ_CTRL, ictrl); | |
59 | ||
820970a5 VG |
60 | /* |
61 | * ARCv2 core intc provides multiple interrupt priorities (upto 16). | |
62 | * Typical builds though have only two levels (0-high, 1-low) | |
63 | * Linux by default uses lower prio 1 for most irqs, reserving 0 for | |
64 | * NMI style interrupts in future (say perf) | |
820970a5 | 65 | */ |
dec2b284 VG |
66 | |
67 | READ_BCR(ARC_REG_IRQ_BCR, irq_bcr); | |
68 | ||
69 | irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */ | |
70 | pr_info("archs-intc\t: %d priority levels (default %d)%s\n", | |
107177b1 | 71 | irq_prio + 1, ARCV2_IRQ_DEF_PRIO, |
dec2b284 VG |
72 | irq_bcr.firq ? " FIRQ (not used)":""); |
73 | ||
be568e78 YK |
74 | /* |
75 | * Set a default priority for all available interrupts to prevent | |
76 | * switching of register banks if Fast IRQ and multiple register banks | |
77 | * are supported by CPU. | |
a8ec3ee8 AB |
78 | * Also disable all IRQ lines so faulty external hardware won't |
79 | * trigger interrupt that kernel is not ready to handle. | |
be568e78 YK |
80 | */ |
81 | for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) { | |
82 | write_aux_reg(AUX_IRQ_SELECT, i); | |
83 | write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); | |
a8ec3ee8 | 84 | write_aux_reg(AUX_IRQ_ENABLE, 0); |
be568e78 YK |
85 | } |
86 | ||
dec2b284 | 87 | /* setup status32, don't enable intr yet as kernel doesn't want */ |
e98a7bf0 | 88 | tmp = read_aux_reg(ARC_REG_STATUS32); |
107177b1 | 89 | tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1); |
dec2b284 | 90 | tmp &= ~STATUS_IE_MASK; |
bc0c7ece | 91 | asm volatile("kflag %0 \n"::"r"(tmp)); |
820970a5 VG |
92 | } |
93 | ||
94 | static void arcv2_irq_mask(struct irq_data *data) | |
95 | { | |
2163266c | 96 | write_aux_reg(AUX_IRQ_SELECT, data->hwirq); |
820970a5 VG |
97 | write_aux_reg(AUX_IRQ_ENABLE, 0); |
98 | } | |
99 | ||
100 | static void arcv2_irq_unmask(struct irq_data *data) | |
101 | { | |
2163266c | 102 | write_aux_reg(AUX_IRQ_SELECT, data->hwirq); |
820970a5 VG |
103 | write_aux_reg(AUX_IRQ_ENABLE, 1); |
104 | } | |
105 | ||
106 | void arcv2_irq_enable(struct irq_data *data) | |
107 | { | |
108 | /* set default priority */ | |
2163266c | 109 | write_aux_reg(AUX_IRQ_SELECT, data->hwirq); |
107177b1 | 110 | write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); |
820970a5 VG |
111 | |
112 | /* | |
113 | * hw auto enables (linux unmask) all by default | |
114 | * So no need to do IRQ_ENABLE here | |
115 | * XXX: However OSCI LAN need it | |
116 | */ | |
117 | write_aux_reg(AUX_IRQ_ENABLE, 1); | |
118 | } | |
119 | ||
120 | static struct irq_chip arcv2_irq_chip = { | |
121 | .name = "ARCv2 core Intc", | |
122 | .irq_mask = arcv2_irq_mask, | |
123 | .irq_unmask = arcv2_irq_unmask, | |
124 | .irq_enable = arcv2_irq_enable | |
125 | }; | |
126 | ||
127 | static int arcv2_irq_map(struct irq_domain *d, unsigned int irq, | |
128 | irq_hw_number_t hw) | |
129 | { | |
8eb0984b VG |
130 | /* |
131 | * core intc IRQs [16, 23]: | |
132 | * Statically assigned always private-per-core (Timers, WDT, IPI, PCT) | |
133 | */ | |
179cf194 | 134 | if (hw < FIRST_EXT_IRQ) { |
8eb0984b VG |
135 | /* |
136 | * A subsequent request_percpu_irq() fails if percpu_devid is | |
137 | * not set. That in turns sets NOAUTOEN, meaning each core needs | |
138 | * to call enable_percpu_irq() | |
139 | */ | |
140 | irq_set_percpu_devid(irq); | |
820970a5 | 141 | irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq); |
8eb0984b | 142 | } else { |
820970a5 | 143 | irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq); |
8eb0984b | 144 | } |
820970a5 VG |
145 | |
146 | return 0; | |
147 | } | |
148 | ||
149 | static const struct irq_domain_ops arcv2_irq_ops = { | |
150 | .xlate = irq_domain_xlate_onecell, | |
151 | .map = arcv2_irq_map, | |
152 | }; | |
153 | ||
820970a5 VG |
154 | |
155 | static int __init | |
156 | init_onchip_IRQ(struct device_node *intc, struct device_node *parent) | |
157 | { | |
1b0ccb8a | 158 | struct irq_domain *root_domain; |
179cf194 VG |
159 | struct bcr_irq_arcv2 irq_bcr; |
160 | unsigned int nr_cpu_irqs; | |
161 | ||
162 | READ_BCR(ARC_REG_IRQ_BCR, irq_bcr); | |
163 | nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS; | |
1b0ccb8a | 164 | |
820970a5 VG |
165 | if (parent) |
166 | panic("DeviceTree incore intc not a root irq controller\n"); | |
167 | ||
179cf194 | 168 | root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL); |
820970a5 VG |
169 | if (!root_domain) |
170 | panic("root irq domain not avail\n"); | |
171 | ||
1b0ccb8a VG |
172 | /* |
173 | * Needed for primary domain lookup to succeed | |
174 | * This is a primary irqchip, and can never have a parent | |
175 | */ | |
820970a5 VG |
176 | irq_set_default_host(root_domain); |
177 | ||
d21beffb VG |
178 | #ifdef CONFIG_SMP |
179 | irq_create_mapping(root_domain, IPI_IRQ); | |
180 | #endif | |
181 | irq_create_mapping(root_domain, SOFTIRQ_IRQ); | |
182 | ||
820970a5 VG |
183 | return 0; |
184 | } | |
185 | ||
186 | IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ); |