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d8005e6b VG |
1 | /* |
2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * vineetg: Jan 1011 | |
9 | * -sched_clock( ) no longer jiffies based. Uses the same clocksource | |
10 | * as gtod | |
11 | * | |
12 | * Rajeshwarr/Vineetg: Mar 2008 | |
13 | * -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code) | |
14 | * for arch independent gettimeofday() | |
15 | * -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers | |
16 | * | |
17 | * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c | |
18 | */ | |
19 | ||
20 | /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1 | |
21 | * Each can programmed to go from @count to @limit and optionally | |
22 | * interrupt when that happens. | |
23 | * A write to Control Register clears the Interrupt | |
24 | * | |
25 | * We've designated TIMER0 for events (clockevents) | |
26 | * while TIMER1 for free running (clocksource) | |
27 | * | |
28 | * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1 | |
565a9b49 | 29 | * which however is currently broken |
d8005e6b VG |
30 | */ |
31 | ||
d8005e6b | 32 | #include <linux/interrupt.h> |
69fbd098 NC |
33 | #include <linux/clk.h> |
34 | #include <linux/clk-provider.h> | |
d8005e6b VG |
35 | #include <linux/clocksource.h> |
36 | #include <linux/clockchips.h> | |
eec3c58e | 37 | #include <linux/cpu.h> |
77c8d0d6 VG |
38 | #include <linux/of.h> |
39 | #include <linux/of_irq.h> | |
d8005e6b VG |
40 | #include <asm/irq.h> |
41 | #include <asm/arcregs.h> | |
d8005e6b | 42 | |
72d72880 VG |
43 | #include <asm/mcip.h> |
44 | ||
da1677b0 VG |
45 | /* Timer related Aux registers */ |
46 | #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ | |
47 | #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ | |
48 | #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ | |
49 | #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ | |
50 | #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ | |
51 | #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ | |
52 | ||
7423cc0c AB |
53 | #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ |
54 | #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ | |
da1677b0 | 55 | |
d8005e6b VG |
56 | #define ARC_TIMER_MAX 0xFFFFFFFF |
57 | ||
77c8d0d6 VG |
58 | static unsigned long arc_timer_freq; |
59 | ||
60 | static int noinline arc_get_timer_clk(struct device_node *node) | |
61 | { | |
62 | struct clk *clk; | |
63 | int ret; | |
64 | ||
65 | clk = of_clk_get(node, 0); | |
66 | if (IS_ERR(clk)) { | |
67 | pr_err("timer missing clk"); | |
68 | return PTR_ERR(clk); | |
69 | } | |
70 | ||
71 | ret = clk_prepare_enable(clk); | |
72 | if (ret) { | |
73 | pr_err("Couldn't enable parent clk\n"); | |
74 | return ret; | |
75 | } | |
76 | ||
77 | arc_timer_freq = clk_get_rate(clk); | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
d8005e6b VG |
82 | /********** Clock Source Device *********/ |
83 | ||
d584f0fb | 84 | #ifdef CONFIG_ARC_HAS_GFRC |
72d72880 VG |
85 | |
86 | static int arc_counter_setup(void) | |
87 | { | |
88 | return 1; | |
89 | } | |
90 | ||
91 | static cycle_t arc_counter_read(struct clocksource *cs) | |
92 | { | |
93 | unsigned long flags; | |
94 | union { | |
95 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
96 | struct { u32 h, l; }; | |
97 | #else | |
98 | struct { u32 l, h; }; | |
99 | #endif | |
100 | cycle_t full; | |
101 | } stamp; | |
102 | ||
103 | local_irq_save(flags); | |
104 | ||
d584f0fb | 105 | __mcip_cmd(CMD_GFRC_READ_LO, 0); |
72d72880 VG |
106 | stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK); |
107 | ||
d584f0fb | 108 | __mcip_cmd(CMD_GFRC_READ_HI, 0); |
72d72880 VG |
109 | stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK); |
110 | ||
111 | local_irq_restore(flags); | |
112 | ||
113 | return stamp.full; | |
114 | } | |
115 | ||
116 | static struct clocksource arc_counter = { | |
d584f0fb | 117 | .name = "ARConnect GFRC", |
72d72880 VG |
118 | .rating = 400, |
119 | .read = arc_counter_read, | |
120 | .mask = CLOCKSOURCE_MASK(64), | |
121 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
122 | }; | |
123 | ||
124 | #else | |
125 | ||
aa93e8ef VG |
126 | #ifdef CONFIG_ARC_HAS_RTC |
127 | ||
128 | #define AUX_RTC_CTRL 0x103 | |
129 | #define AUX_RTC_LOW 0x104 | |
130 | #define AUX_RTC_HIGH 0x105 | |
131 | ||
132 | int arc_counter_setup(void) | |
133 | { | |
134 | write_aux_reg(AUX_RTC_CTRL, 1); | |
135 | ||
136 | /* Not usable in SMP */ | |
137 | return !IS_ENABLED(CONFIG_SMP); | |
138 | } | |
139 | ||
140 | static cycle_t arc_counter_read(struct clocksource *cs) | |
141 | { | |
142 | unsigned long status; | |
143 | union { | |
144 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
145 | struct { u32 high, low; }; | |
146 | #else | |
147 | struct { u32 low, high; }; | |
148 | #endif | |
149 | cycle_t full; | |
150 | } stamp; | |
151 | ||
152 | ||
153 | __asm__ __volatile( | |
154 | "1: \n" | |
155 | " lr %0, [AUX_RTC_LOW] \n" | |
156 | " lr %1, [AUX_RTC_HIGH] \n" | |
157 | " lr %2, [AUX_RTC_CTRL] \n" | |
158 | " bbit0.nt %2, 31, 1b \n" | |
159 | : "=r" (stamp.low), "=r" (stamp.high), "=r" (status)); | |
160 | ||
161 | return stamp.full; | |
162 | } | |
163 | ||
164 | static struct clocksource arc_counter = { | |
165 | .name = "ARCv2 RTC", | |
166 | .rating = 350, | |
167 | .read = arc_counter_read, | |
168 | .mask = CLOCKSOURCE_MASK(64), | |
169 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
170 | }; | |
171 | ||
172 | #else /* !CONFIG_ARC_HAS_RTC */ | |
173 | ||
d8005e6b VG |
174 | /* |
175 | * set 32bit TIMER1 to keep counting monotonically and wraparound | |
176 | */ | |
ce759956 | 177 | int arc_counter_setup(void) |
d8005e6b VG |
178 | { |
179 | write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); | |
180 | write_aux_reg(ARC_REG_TIMER1_CNT, 0); | |
181 | write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); | |
182 | ||
5b9bd178 VG |
183 | /* Not usable in SMP */ |
184 | return !IS_ENABLED(CONFIG_SMP); | |
d8005e6b VG |
185 | } |
186 | ||
187 | static cycle_t arc_counter_read(struct clocksource *cs) | |
188 | { | |
189 | return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT); | |
190 | } | |
191 | ||
192 | static struct clocksource arc_counter = { | |
193 | .name = "ARC Timer1", | |
194 | .rating = 300, | |
195 | .read = arc_counter_read, | |
196 | .mask = CLOCKSOURCE_MASK(32), | |
197 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
198 | }; | |
199 | ||
72d72880 | 200 | #endif |
aa93e8ef VG |
201 | #endif |
202 | ||
d8005e6b VG |
203 | /********** Clock Event Device *********/ |
204 | ||
77c8d0d6 | 205 | static int arc_timer_irq; |
eec3c58e | 206 | |
d8005e6b | 207 | /* |
c9a98e18 | 208 | * Arm the timer to interrupt after @cycles |
d8005e6b VG |
209 | * The distinction for oneshot/periodic is done in arc_event_timer_ack() below |
210 | */ | |
c9a98e18 | 211 | static void arc_timer_event_setup(unsigned int cycles) |
d8005e6b | 212 | { |
c9a98e18 | 213 | write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); |
d8005e6b VG |
214 | write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ |
215 | ||
216 | write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); | |
217 | } | |
218 | ||
d8005e6b VG |
219 | |
220 | static int arc_clkevent_set_next_event(unsigned long delta, | |
221 | struct clock_event_device *dev) | |
222 | { | |
223 | arc_timer_event_setup(delta); | |
224 | return 0; | |
225 | } | |
226 | ||
aeec6cda | 227 | static int arc_clkevent_set_periodic(struct clock_event_device *dev) |
d8005e6b | 228 | { |
aeec6cda VK |
229 | /* |
230 | * At X Hz, 1 sec = 1000ms -> X cycles; | |
231 | * 10ms -> X / 100 cycles | |
232 | */ | |
77c8d0d6 | 233 | arc_timer_event_setup(arc_timer_freq / HZ); |
aeec6cda | 234 | return 0; |
d8005e6b VG |
235 | } |
236 | ||
237 | static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { | |
aeec6cda VK |
238 | .name = "ARC Timer0", |
239 | .features = CLOCK_EVT_FEAT_ONESHOT | | |
240 | CLOCK_EVT_FEAT_PERIODIC, | |
241 | .rating = 300, | |
aeec6cda VK |
242 | .set_next_event = arc_clkevent_set_next_event, |
243 | .set_state_periodic = arc_clkevent_set_periodic, | |
d8005e6b VG |
244 | }; |
245 | ||
246 | static irqreturn_t timer_irq_handler(int irq, void *dev_id) | |
247 | { | |
f8b34c3f VG |
248 | /* |
249 | * Note that generic IRQ core could have passed @evt for @dev_id if | |
250 | * irq_set_chip_and_handler() asked for handle_percpu_devid_irq() | |
251 | */ | |
252 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); | |
aeec6cda | 253 | int irq_reenable = clockevent_state_periodic(evt); |
f8b34c3f VG |
254 | |
255 | /* | |
256 | * Any write to CTRL reg ACks the interrupt, we rewrite the | |
257 | * Count when [N]ot [H]alted bit. | |
258 | * And re-arm it if perioid by [I]nterrupt [E]nable bit | |
259 | */ | |
260 | write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); | |
261 | ||
262 | evt->event_handler(evt); | |
d8005e6b | 263 | |
d8005e6b VG |
264 | return IRQ_HANDLED; |
265 | } | |
266 | ||
eec3c58e NC |
267 | static int arc_timer_cpu_notify(struct notifier_block *self, |
268 | unsigned long action, void *hcpu) | |
269 | { | |
270 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); | |
271 | ||
272 | evt->cpumask = cpumask_of(smp_processor_id()); | |
273 | ||
274 | switch (action & ~CPU_TASKS_FROZEN) { | |
275 | case CPU_STARTING: | |
77c8d0d6 | 276 | clockevents_config_and_register(evt, arc_timer_freq, |
eec3c58e NC |
277 | 0, ULONG_MAX); |
278 | enable_percpu_irq(arc_timer_irq, 0); | |
279 | break; | |
280 | case CPU_DYING: | |
281 | disable_percpu_irq(arc_timer_irq); | |
282 | break; | |
283 | } | |
284 | ||
285 | return NOTIFY_OK; | |
286 | } | |
287 | ||
288 | static struct notifier_block arc_timer_cpu_nb = { | |
289 | .notifier_call = arc_timer_cpu_notify, | |
290 | }; | |
291 | ||
d8005e6b | 292 | /* |
eec3c58e | 293 | * clockevent setup for boot CPU |
d8005e6b | 294 | */ |
77c8d0d6 | 295 | static void __init arc_clockevent_setup(struct device_node *node) |
d8005e6b | 296 | { |
2d4899f6 | 297 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); |
eec3c58e | 298 | int ret; |
d8005e6b | 299 | |
eec3c58e NC |
300 | register_cpu_notifier(&arc_timer_cpu_nb); |
301 | ||
77c8d0d6 VG |
302 | arc_timer_irq = irq_of_parse_and_map(node, 0); |
303 | if (arc_timer_irq <= 0) | |
304 | panic("clockevent: missing irq"); | |
305 | ||
306 | ret = arc_get_timer_clk(node); | |
307 | if (ret) | |
308 | panic("clockevent: missing clk"); | |
309 | ||
310 | evt->irq = arc_timer_irq; | |
eec3c58e | 311 | evt->cpumask = cpumask_of(smp_processor_id()); |
77c8d0d6 | 312 | clockevents_config_and_register(evt, arc_timer_freq, |
55c2e262 | 313 | 0, ARC_TIMER_MAX); |
d8005e6b | 314 | |
eec3c58e NC |
315 | /* Needs apriori irq_set_percpu_devid() done in intc map function */ |
316 | ret = request_percpu_irq(arc_timer_irq, timer_irq_handler, | |
317 | "Timer0 (per-cpu-tick)", evt); | |
318 | if (ret) | |
77c8d0d6 | 319 | panic("clockevent: unable to request irq\n"); |
56957940 | 320 | |
eec3c58e | 321 | enable_percpu_irq(arc_timer_irq, 0); |
d8005e6b | 322 | } |
77c8d0d6 | 323 | CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_clockevent_setup); |
d8005e6b VG |
324 | |
325 | /* | |
326 | * Called from start_kernel() - boot CPU only | |
327 | * | |
328 | * -Sets up h/w timers as applicable on boot cpu | |
329 | * -Also sets up any global state needed for timer subsystem: | |
330 | * - for "counting" timer, registers a clocksource, usable across CPUs | |
331 | * (provided that underlying counter h/w is synchronized across cores) | |
d8005e6b VG |
332 | */ |
333 | void __init time_init(void) | |
334 | { | |
69fbd098 NC |
335 | of_clk_init(NULL); |
336 | clocksource_probe(); | |
337 | ||
d8005e6b VG |
338 | /* |
339 | * sets up the timekeeping free-flowing counter which also returns | |
340 | * whether the counter is usable as clocksource | |
341 | */ | |
342 | if (arc_counter_setup()) | |
343 | /* | |
344 | * CLK upto 4.29 GHz can be safely represented in 32 bits | |
345 | * because Max 32 bit number is 4,294,967,295 | |
346 | */ | |
77c8d0d6 | 347 | clocksource_register_hz(&arc_counter, arc_timer_freq); |
d8005e6b | 348 | } |