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Commit | Line | Data |
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95d6976d | 1 | /* |
8ea2ddff | 2 | * ARC Cache Management |
95d6976d | 3 | * |
8ea2ddff | 4 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) |
95d6976d VG |
5 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
95d6976d VG |
10 | */ |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/cache.h> | |
16 | #include <linux/mmu_context.h> | |
17 | #include <linux/syscalls.h> | |
18 | #include <linux/uaccess.h> | |
4102b533 | 19 | #include <linux/pagemap.h> |
95d6976d VG |
20 | #include <asm/cacheflush.h> |
21 | #include <asm/cachectl.h> | |
22 | #include <asm/setup.h> | |
23 | ||
795f4558 VG |
24 | static int l2_line_sz; |
25 | ||
bcc4d65a VG |
26 | void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr, |
27 | unsigned long sz, const int cacheop); | |
28 | ||
c3441edd | 29 | char *arc_cache_mumbojumbo(int c, char *buf, int len) |
af617428 VG |
30 | { |
31 | int n = 0; | |
d1f317d8 | 32 | struct cpuinfo_arc_cache *p; |
af617428 | 33 | |
da40ff48 | 34 | #define PR_CACHE(p, cfg, str) \ |
af617428 VG |
35 | if (!(p)->ver) \ |
36 | n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ | |
37 | else \ | |
38 | n += scnprintf(buf + n, len - n, \ | |
da40ff48 VG |
39 | str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \ |
40 | (p)->sz_k, (p)->assoc, (p)->line_len, \ | |
41 | (p)->vipt ? "VIPT" : "PIPT", \ | |
42 | (p)->alias ? " aliasing" : "", \ | |
43 | IS_ENABLED(cfg) ? "" : " (not used)"); | |
af617428 | 44 | |
da40ff48 VG |
45 | PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); |
46 | PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); | |
af617428 | 47 | |
d1f317d8 VG |
48 | p = &cpuinfo_arc700[c].slc; |
49 | if (p->ver) | |
50 | n += scnprintf(buf + n, len - n, | |
51 | "SLC\t\t: %uK, %uB Line\n", p->sz_k, p->line_len); | |
52 | ||
af617428 VG |
53 | return buf; |
54 | } | |
55 | ||
95d6976d VG |
56 | /* |
57 | * Read the Cache Build Confuration Registers, Decode them and save into | |
58 | * the cpuinfo structure for later use. | |
59 | * No Validation done here, simply read/convert the BCRs | |
60 | */ | |
ce759956 | 61 | void read_decode_cache_bcr(void) |
95d6976d | 62 | { |
d1f317d8 | 63 | struct cpuinfo_arc_cache *p_ic, *p_dc, *p_slc; |
95d6976d | 64 | unsigned int cpu = smp_processor_id(); |
da1677b0 VG |
65 | struct bcr_cache { |
66 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
67 | unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; | |
68 | #else | |
69 | unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; | |
70 | #endif | |
71 | } ibcr, dbcr; | |
95d6976d | 72 | |
d1f317d8 VG |
73 | struct bcr_generic sbcr; |
74 | ||
75 | struct bcr_slc_cfg { | |
76 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
77 | unsigned int pad:24, way:2, lsz:2, sz:4; | |
78 | #else | |
79 | unsigned int sz:4, lsz:2, way:2, pad:24; | |
80 | #endif | |
81 | } slc_cfg; | |
82 | ||
95d6976d VG |
83 | p_ic = &cpuinfo_arc700[cpu].icache; |
84 | READ_BCR(ARC_REG_IC_BCR, ibcr); | |
85 | ||
da40ff48 VG |
86 | if (!ibcr.ver) |
87 | goto dc_chk; | |
88 | ||
d1f317d8 VG |
89 | if (ibcr.ver <= 3) { |
90 | BUG_ON(ibcr.config != 3); | |
91 | p_ic->assoc = 2; /* Fixed to 2w set assoc */ | |
92 | } else if (ibcr.ver >= 4) { | |
93 | p_ic->assoc = 1 << ibcr.config; /* 1,2,4,8 */ | |
94 | } | |
95 | ||
95d6976d | 96 | p_ic->line_len = 8 << ibcr.line_len; |
da40ff48 | 97 | p_ic->sz_k = 1 << (ibcr.sz - 1); |
95d6976d | 98 | p_ic->ver = ibcr.ver; |
da40ff48 VG |
99 | p_ic->vipt = 1; |
100 | p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1; | |
95d6976d | 101 | |
da40ff48 | 102 | dc_chk: |
95d6976d VG |
103 | p_dc = &cpuinfo_arc700[cpu].dcache; |
104 | READ_BCR(ARC_REG_DC_BCR, dbcr); | |
105 | ||
da40ff48 | 106 | if (!dbcr.ver) |
d1f317d8 VG |
107 | goto slc_chk; |
108 | ||
109 | if (dbcr.ver <= 3) { | |
110 | BUG_ON(dbcr.config != 2); | |
111 | p_dc->assoc = 4; /* Fixed to 4w set assoc */ | |
112 | p_dc->vipt = 1; | |
113 | p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1; | |
114 | } else if (dbcr.ver >= 4) { | |
115 | p_dc->assoc = 1 << dbcr.config; /* 1,2,4,8 */ | |
116 | p_dc->vipt = 0; | |
117 | p_dc->alias = 0; /* PIPT so can't VIPT alias */ | |
118 | } | |
da40ff48 | 119 | |
95d6976d | 120 | p_dc->line_len = 16 << dbcr.line_len; |
da40ff48 | 121 | p_dc->sz_k = 1 << (dbcr.sz - 1); |
95d6976d | 122 | p_dc->ver = dbcr.ver; |
d1f317d8 VG |
123 | |
124 | slc_chk: | |
795f4558 VG |
125 | if (!is_isa_arcv2()) |
126 | return; | |
127 | ||
d1f317d8 VG |
128 | p_slc = &cpuinfo_arc700[cpu].slc; |
129 | READ_BCR(ARC_REG_SLC_BCR, sbcr); | |
130 | if (sbcr.ver) { | |
131 | READ_BCR(ARC_REG_SLC_CFG, slc_cfg); | |
132 | p_slc->ver = sbcr.ver; | |
133 | p_slc->sz_k = 128 << slc_cfg.sz; | |
795f4558 | 134 | l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64; |
d1f317d8 | 135 | } |
95d6976d VG |
136 | } |
137 | ||
138 | /* | |
8ea2ddff | 139 | * Line Operation on {I,D}-Cache |
95d6976d | 140 | */ |
95d6976d VG |
141 | |
142 | #define OP_INV 0x1 | |
143 | #define OP_FLUSH 0x2 | |
144 | #define OP_FLUSH_N_INV 0x3 | |
bd12976c VG |
145 | #define OP_INV_IC 0x4 |
146 | ||
147 | /* | |
8ea2ddff VG |
148 | * I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3) |
149 | * | |
150 | * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag. | |
151 | * The orig Cache Management Module "CDU" only required paddr to invalidate a | |
152 | * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry. | |
153 | * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching | |
154 | * the exact same line. | |
155 | * | |
156 | * However for larger Caches (way-size > page-size) - i.e. in Aliasing config, | |
157 | * paddr alone could not be used to correctly index the cache. | |
158 | * | |
159 | * ------------------ | |
160 | * MMU v1/v2 (Fixed Page Size 8k) | |
161 | * ------------------ | |
162 | * The solution was to provide CDU with these additonal vaddr bits. These | |
163 | * would be bits [x:13], x would depend on cache-geometry, 13 comes from | |
164 | * standard page size of 8k. | |
165 | * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits | |
166 | * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the | |
167 | * orig 5 bits of paddr were anyways ignored by CDU line ops, as they | |
168 | * represent the offset within cache-line. The adv of using this "clumsy" | |
169 | * interface for additional info was no new reg was needed in CDU programming | |
170 | * model. | |
171 | * | |
172 | * 17:13 represented the max num of bits passable, actual bits needed were | |
173 | * fewer, based on the num-of-aliases possible. | |
174 | * -for 2 alias possibility, only bit 13 needed (32K cache) | |
175 | * -for 4 alias possibility, bits 14:13 needed (64K cache) | |
176 | * | |
177 | * ------------------ | |
178 | * MMU v3 | |
179 | * ------------------ | |
180 | * This ver of MMU supports variable page sizes (1k-16k): although Linux will | |
181 | * only support 8k (default), 16k and 4k. | |
182 | * However from hardware perspective, smaller page sizes aggrevate aliasing | |
183 | * meaning more vaddr bits needed to disambiguate the cache-line-op ; | |
184 | * the existing scheme of piggybacking won't work for certain configurations. | |
185 | * Two new registers IC_PTAG and DC_PTAG inttoduced. | |
186 | * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs | |
bd12976c | 187 | */ |
8ea2ddff | 188 | |
11e14896 VG |
189 | static inline |
190 | void __cache_line_loop_v2(unsigned long paddr, unsigned long vaddr, | |
191 | unsigned long sz, const int op) | |
bd12976c | 192 | { |
11e14896 | 193 | unsigned int aux_cmd; |
bd12976c | 194 | int num_lines; |
11e14896 | 195 | const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE; |
bd12976c | 196 | |
8ea2ddff | 197 | if (op == OP_INV_IC) { |
bd12976c | 198 | aux_cmd = ARC_REG_IC_IVIL; |
11e14896 | 199 | } else { |
bd12976c | 200 | /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ |
8ea2ddff | 201 | aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; |
bd12976c VG |
202 | } |
203 | ||
204 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
205 | * and have @paddr - aligned to cache line and integral @num_lines. | |
206 | * This however can be avoided for page sized since: | |
207 | * -@paddr will be cache-line aligned already (being page aligned) | |
208 | * -@sz will be integral multiple of line size (being page sized). | |
209 | */ | |
11e14896 | 210 | if (!full_page) { |
bd12976c VG |
211 | sz += paddr & ~CACHE_LINE_MASK; |
212 | paddr &= CACHE_LINE_MASK; | |
213 | vaddr &= CACHE_LINE_MASK; | |
214 | } | |
215 | ||
216 | num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); | |
217 | ||
bd12976c VG |
218 | /* MMUv2 and before: paddr contains stuffed vaddrs bits */ |
219 | paddr |= (vaddr >> PAGE_SHIFT) & 0x1F; | |
11e14896 VG |
220 | |
221 | while (num_lines-- > 0) { | |
222 | write_aux_reg(aux_cmd, paddr); | |
223 | paddr += L1_CACHE_BYTES; | |
224 | } | |
225 | } | |
226 | ||
227 | static inline | |
228 | void __cache_line_loop_v3(unsigned long paddr, unsigned long vaddr, | |
229 | unsigned long sz, const int op) | |
230 | { | |
231 | unsigned int aux_cmd, aux_tag; | |
232 | int num_lines; | |
233 | const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE; | |
234 | ||
235 | if (op == OP_INV_IC) { | |
236 | aux_cmd = ARC_REG_IC_IVIL; | |
237 | aux_tag = ARC_REG_IC_PTAG; | |
238 | } else { | |
239 | aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; | |
240 | aux_tag = ARC_REG_DC_PTAG; | |
241 | } | |
242 | ||
243 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
244 | * and have @paddr - aligned to cache line and integral @num_lines. | |
245 | * This however can be avoided for page sized since: | |
246 | * -@paddr will be cache-line aligned already (being page aligned) | |
247 | * -@sz will be integral multiple of line size (being page sized). | |
248 | */ | |
249 | if (!full_page) { | |
250 | sz += paddr & ~CACHE_LINE_MASK; | |
251 | paddr &= CACHE_LINE_MASK; | |
252 | vaddr &= CACHE_LINE_MASK; | |
253 | } | |
254 | num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); | |
255 | ||
256 | /* | |
257 | * MMUv3, cache ops require paddr in PTAG reg | |
258 | * if V-P const for loop, PTAG can be written once outside loop | |
259 | */ | |
260 | if (full_page) | |
b053940d | 261 | write_aux_reg(aux_tag, paddr); |
bd12976c VG |
262 | |
263 | while (num_lines-- > 0) { | |
11e14896 | 264 | if (!full_page) { |
d4599baf VG |
265 | write_aux_reg(aux_tag, paddr); |
266 | paddr += L1_CACHE_BYTES; | |
267 | } | |
bd12976c VG |
268 | |
269 | write_aux_reg(aux_cmd, vaddr); | |
270 | vaddr += L1_CACHE_BYTES; | |
bd12976c VG |
271 | } |
272 | } | |
95d6976d | 273 | |
d1f317d8 VG |
274 | /* |
275 | * In HS38x (MMU v4), although icache is VIPT, only paddr is needed for cache | |
276 | * maintenance ops (in IVIL reg), as long as icache doesn't alias. | |
277 | * | |
278 | * For Aliasing icache, vaddr is also needed (in IVIL), while paddr is | |
279 | * specified in PTAG (similar to MMU v3) | |
280 | */ | |
281 | static inline | |
282 | void __cache_line_loop_v4(unsigned long paddr, unsigned long vaddr, | |
283 | unsigned long sz, const int cacheop) | |
284 | { | |
285 | unsigned int aux_cmd; | |
286 | int num_lines; | |
287 | const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE; | |
288 | ||
289 | if (cacheop == OP_INV_IC) { | |
290 | aux_cmd = ARC_REG_IC_IVIL; | |
291 | } else { | |
292 | /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ | |
293 | aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; | |
294 | } | |
295 | ||
296 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
297 | * and have @paddr - aligned to cache line and integral @num_lines. | |
298 | * This however can be avoided for page sized since: | |
299 | * -@paddr will be cache-line aligned already (being page aligned) | |
300 | * -@sz will be integral multiple of line size (being page sized). | |
301 | */ | |
302 | if (!full_page_op) { | |
303 | sz += paddr & ~CACHE_LINE_MASK; | |
304 | paddr &= CACHE_LINE_MASK; | |
305 | } | |
306 | ||
307 | num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); | |
308 | ||
309 | while (num_lines-- > 0) { | |
310 | write_aux_reg(aux_cmd, paddr); | |
311 | paddr += L1_CACHE_BYTES; | |
312 | } | |
313 | } | |
314 | ||
11e14896 VG |
315 | #if (CONFIG_ARC_MMU_VER < 3) |
316 | #define __cache_line_loop __cache_line_loop_v2 | |
317 | #elif (CONFIG_ARC_MMU_VER == 3) | |
318 | #define __cache_line_loop __cache_line_loop_v3 | |
d1f317d8 VG |
319 | #elif (CONFIG_ARC_MMU_VER > 3) |
320 | #define __cache_line_loop __cache_line_loop_v4 | |
11e14896 VG |
321 | #endif |
322 | ||
95d6976d VG |
323 | #ifdef CONFIG_ARC_HAS_DCACHE |
324 | ||
325 | /*************************************************************** | |
326 | * Machine specific helpers for Entire D-Cache or Per Line ops | |
327 | */ | |
328 | ||
6c310681 | 329 | static inline void __before_dc_op(const int op) |
95d6976d | 330 | { |
1b1a22b1 VG |
331 | if (op == OP_FLUSH_N_INV) { |
332 | /* Dcache provides 2 cmd: FLUSH or INV | |
333 | * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE | |
334 | * flush-n-inv is achieved by INV cmd but with IM=1 | |
335 | * So toggle INV sub-mode depending on op request and default | |
336 | */ | |
6c310681 VG |
337 | const unsigned int ctl = ARC_REG_DC_CTRL; |
338 | write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); | |
1b1a22b1 | 339 | } |
1b1a22b1 VG |
340 | } |
341 | ||
6c310681 | 342 | static inline void __after_dc_op(const int op) |
1b1a22b1 | 343 | { |
6c310681 VG |
344 | if (op & OP_FLUSH) { |
345 | const unsigned int ctl = ARC_REG_DC_CTRL; | |
346 | unsigned int reg; | |
1b1a22b1 | 347 | |
6c310681 VG |
348 | /* flush / flush-n-inv both wait */ |
349 | while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS) | |
350 | ; | |
351 | ||
352 | /* Switch back to default Invalidate mode */ | |
353 | if (op == OP_FLUSH_N_INV) | |
354 | write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH); | |
355 | } | |
95d6976d VG |
356 | } |
357 | ||
358 | /* | |
359 | * Operation on Entire D-Cache | |
8ea2ddff | 360 | * @op = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV} |
95d6976d VG |
361 | * Note that constant propagation ensures all the checks are gone |
362 | * in generated code | |
363 | */ | |
8ea2ddff | 364 | static inline void __dc_entire_op(const int op) |
95d6976d | 365 | { |
95d6976d VG |
366 | int aux; |
367 | ||
6c310681 | 368 | __before_dc_op(op); |
95d6976d | 369 | |
8ea2ddff | 370 | if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ |
95d6976d VG |
371 | aux = ARC_REG_DC_IVDC; |
372 | else | |
373 | aux = ARC_REG_DC_FLSH; | |
374 | ||
375 | write_aux_reg(aux, 0x1); | |
376 | ||
6c310681 | 377 | __after_dc_op(op); |
95d6976d VG |
378 | } |
379 | ||
4102b533 | 380 | /* For kernel mappings cache operation: index is same as paddr */ |
6ec18a81 VG |
381 | #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op) |
382 | ||
95d6976d | 383 | /* |
8ea2ddff | 384 | * D-Cache Line ops: Per Line INV (discard or wback+discard) or FLUSH (wback) |
95d6976d | 385 | */ |
6ec18a81 | 386 | static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, |
8ea2ddff | 387 | unsigned long sz, const int op) |
95d6976d | 388 | { |
1b1a22b1 | 389 | unsigned long flags; |
95d6976d VG |
390 | |
391 | local_irq_save(flags); | |
392 | ||
6c310681 | 393 | __before_dc_op(op); |
95d6976d | 394 | |
8ea2ddff | 395 | __cache_line_loop(paddr, vaddr, sz, op); |
95d6976d | 396 | |
6c310681 | 397 | __after_dc_op(op); |
95d6976d VG |
398 | |
399 | local_irq_restore(flags); | |
400 | } | |
401 | ||
402 | #else | |
403 | ||
8ea2ddff VG |
404 | #define __dc_entire_op(op) |
405 | #define __dc_line_op(paddr, vaddr, sz, op) | |
406 | #define __dc_line_op_k(paddr, sz, op) | |
95d6976d VG |
407 | |
408 | #endif /* CONFIG_ARC_HAS_DCACHE */ | |
409 | ||
95d6976d VG |
410 | #ifdef CONFIG_ARC_HAS_ICACHE |
411 | ||
af5abf1b VG |
412 | static inline void __ic_entire_inv(void) |
413 | { | |
414 | write_aux_reg(ARC_REG_IC_IVIC, 1); | |
415 | read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ | |
416 | } | |
417 | ||
418 | static inline void | |
419 | __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, | |
420 | unsigned long sz) | |
95d6976d VG |
421 | { |
422 | unsigned long flags; | |
95d6976d VG |
423 | |
424 | local_irq_save(flags); | |
bcc4d65a | 425 | (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC); |
95d6976d VG |
426 | local_irq_restore(flags); |
427 | } | |
428 | ||
af5abf1b VG |
429 | #ifndef CONFIG_SMP |
430 | ||
431 | #define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s) | |
432 | ||
433 | #else | |
336e199e | 434 | |
af5abf1b | 435 | struct ic_inv_args { |
2328af0c VG |
436 | unsigned long paddr, vaddr; |
437 | int sz; | |
438 | }; | |
439 | ||
440 | static void __ic_line_inv_vaddr_helper(void *info) | |
441 | { | |
014018e0 | 442 | struct ic_inv_args *ic_inv = info; |
af5abf1b | 443 | |
2328af0c VG |
444 | __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz); |
445 | } | |
446 | ||
447 | static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr, | |
448 | unsigned long sz) | |
449 | { | |
af5abf1b VG |
450 | struct ic_inv_args ic_inv = { |
451 | .paddr = paddr, | |
452 | .vaddr = vaddr, | |
453 | .sz = sz | |
454 | }; | |
455 | ||
2328af0c VG |
456 | on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1); |
457 | } | |
af5abf1b VG |
458 | |
459 | #endif /* CONFIG_SMP */ | |
460 | ||
461 | #else /* !CONFIG_ARC_HAS_ICACHE */ | |
95d6976d | 462 | |
336e199e | 463 | #define __ic_entire_inv() |
95d6976d VG |
464 | #define __ic_line_inv_vaddr(pstart, vstart, sz) |
465 | ||
466 | #endif /* CONFIG_ARC_HAS_ICACHE */ | |
467 | ||
795f4558 VG |
468 | noinline void slc_op(unsigned long paddr, unsigned long sz, const int op) |
469 | { | |
470 | #ifdef CONFIG_ISA_ARCV2 | |
471 | unsigned long flags; | |
472 | unsigned int ctrl; | |
473 | ||
474 | local_irq_save(flags); | |
475 | ||
476 | /* | |
477 | * The Region Flush operation is specified by CTRL.RGN_OP[11..9] | |
478 | * - b'000 (default) is Flush, | |
479 | * - b'001 is Invalidate if CTRL.IM == 0 | |
480 | * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 | |
481 | */ | |
482 | ctrl = read_aux_reg(ARC_REG_SLC_CTRL); | |
483 | ||
484 | /* Don't rely on default value of IM bit */ | |
485 | if (!(op & OP_FLUSH)) /* i.e. OP_INV */ | |
486 | ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ | |
487 | else | |
488 | ctrl |= SLC_CTRL_IM; | |
489 | ||
490 | if (op & OP_INV) | |
491 | ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ | |
492 | else | |
493 | ctrl &= ~SLC_CTRL_RGN_OP_INV; | |
494 | ||
495 | write_aux_reg(ARC_REG_SLC_CTRL, ctrl); | |
496 | ||
497 | /* | |
498 | * Lower bits are ignored, no need to clip | |
499 | * END needs to be setup before START (latter triggers the operation) | |
500 | * END can't be same as START, so add (l2_line_sz - 1) to sz | |
501 | */ | |
502 | write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1)); | |
503 | write_aux_reg(ARC_REG_SLC_RGN_START, paddr); | |
504 | ||
505 | while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); | |
506 | ||
507 | local_irq_restore(flags); | |
508 | #endif | |
509 | } | |
510 | ||
511 | static inline int need_slc_flush(void) | |
512 | { | |
513 | return is_isa_arcv2() && l2_line_sz; | |
514 | } | |
95d6976d VG |
515 | |
516 | /*********************************************************** | |
517 | * Exported APIs | |
518 | */ | |
519 | ||
4102b533 VG |
520 | /* |
521 | * Handle cache congruency of kernel and userspace mappings of page when kernel | |
522 | * writes-to/reads-from | |
523 | * | |
524 | * The idea is to defer flushing of kernel mapping after a WRITE, possible if: | |
525 | * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent | |
526 | * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache) | |
527 | * -In SMP, if hardware caches are coherent | |
528 | * | |
529 | * There's a corollary case, where kernel READs from a userspace mapped page. | |
530 | * If the U-mapping is not congruent to to K-mapping, former needs flushing. | |
531 | */ | |
95d6976d VG |
532 | void flush_dcache_page(struct page *page) |
533 | { | |
4102b533 VG |
534 | struct address_space *mapping; |
535 | ||
536 | if (!cache_is_vipt_aliasing()) { | |
2ed21dae | 537 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
538 | return; |
539 | } | |
540 | ||
541 | /* don't handle anon pages here */ | |
542 | mapping = page_mapping(page); | |
543 | if (!mapping) | |
544 | return; | |
545 | ||
546 | /* | |
547 | * pagecache page, file not yet mapped to userspace | |
548 | * Make a note that K-mapping is dirty | |
549 | */ | |
550 | if (!mapping_mapped(mapping)) { | |
2ed21dae | 551 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
552 | } else if (page_mapped(page)) { |
553 | ||
554 | /* kernel reading from page with U-mapping */ | |
45309493 | 555 | unsigned long paddr = (unsigned long)page_address(page); |
4102b533 VG |
556 | unsigned long vaddr = page->index << PAGE_CACHE_SHIFT; |
557 | ||
558 | if (addr_not_cache_congruent(paddr, vaddr)) | |
559 | __flush_dcache_page(paddr, vaddr); | |
560 | } | |
95d6976d VG |
561 | } |
562 | EXPORT_SYMBOL(flush_dcache_page); | |
563 | ||
95d6976d VG |
564 | void dma_cache_wback_inv(unsigned long start, unsigned long sz) |
565 | { | |
6ec18a81 | 566 | __dc_line_op_k(start, sz, OP_FLUSH_N_INV); |
795f4558 VG |
567 | |
568 | if (need_slc_flush()) | |
569 | slc_op(start, sz, OP_FLUSH_N_INV); | |
95d6976d VG |
570 | } |
571 | EXPORT_SYMBOL(dma_cache_wback_inv); | |
572 | ||
573 | void dma_cache_inv(unsigned long start, unsigned long sz) | |
574 | { | |
6ec18a81 | 575 | __dc_line_op_k(start, sz, OP_INV); |
795f4558 VG |
576 | |
577 | if (need_slc_flush()) | |
578 | slc_op(start, sz, OP_INV); | |
95d6976d VG |
579 | } |
580 | EXPORT_SYMBOL(dma_cache_inv); | |
581 | ||
582 | void dma_cache_wback(unsigned long start, unsigned long sz) | |
583 | { | |
6ec18a81 | 584 | __dc_line_op_k(start, sz, OP_FLUSH); |
795f4558 VG |
585 | |
586 | if (need_slc_flush()) | |
587 | slc_op(start, sz, OP_FLUSH); | |
95d6976d VG |
588 | } |
589 | EXPORT_SYMBOL(dma_cache_wback); | |
590 | ||
591 | /* | |
7586bf72 VG |
592 | * This is API for making I/D Caches consistent when modifying |
593 | * kernel code (loadable modules, kprobes, kgdb...) | |
95d6976d VG |
594 | * This is called on insmod, with kernel virtual address for CODE of |
595 | * the module. ARC cache maintenance ops require PHY address thus we | |
596 | * need to convert vmalloc addr to PHY addr | |
597 | */ | |
598 | void flush_icache_range(unsigned long kstart, unsigned long kend) | |
599 | { | |
c59414cc | 600 | unsigned int tot_sz; |
95d6976d | 601 | |
c59414cc | 602 | WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__); |
95d6976d VG |
603 | |
604 | /* Shortcut for bigger flush ranges. | |
605 | * Here we don't care if this was kernel virtual or phy addr | |
606 | */ | |
607 | tot_sz = kend - kstart; | |
608 | if (tot_sz > PAGE_SIZE) { | |
609 | flush_cache_all(); | |
610 | return; | |
611 | } | |
612 | ||
613 | /* Case: Kernel Phy addr (0x8000_0000 onwards) */ | |
614 | if (likely(kstart > PAGE_OFFSET)) { | |
7586bf72 VG |
615 | /* |
616 | * The 2nd arg despite being paddr will be used to index icache | |
617 | * This is OK since no alternate virtual mappings will exist | |
618 | * given the callers for this case: kprobe/kgdb in built-in | |
619 | * kernel code only. | |
620 | */ | |
94bad1af | 621 | __sync_icache_dcache(kstart, kstart, kend - kstart); |
95d6976d VG |
622 | return; |
623 | } | |
624 | ||
625 | /* | |
626 | * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff) | |
627 | * (1) ARC Cache Maintenance ops only take Phy addr, hence special | |
628 | * handling of kernel vaddr. | |
629 | * | |
630 | * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already), | |
631 | * it still needs to handle a 2 page scenario, where the range | |
632 | * straddles across 2 virtual pages and hence need for loop | |
633 | */ | |
634 | while (tot_sz > 0) { | |
c59414cc VG |
635 | unsigned int off, sz; |
636 | unsigned long phy, pfn; | |
637 | ||
95d6976d VG |
638 | off = kstart % PAGE_SIZE; |
639 | pfn = vmalloc_to_pfn((void *)kstart); | |
640 | phy = (pfn << PAGE_SHIFT) + off; | |
641 | sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off); | |
94bad1af | 642 | __sync_icache_dcache(phy, kstart, sz); |
95d6976d VG |
643 | kstart += sz; |
644 | tot_sz -= sz; | |
645 | } | |
646 | } | |
e3560305 | 647 | EXPORT_SYMBOL(flush_icache_range); |
95d6976d VG |
648 | |
649 | /* | |
94bad1af VG |
650 | * General purpose helper to make I and D cache lines consistent. |
651 | * @paddr is phy addr of region | |
4b06ff35 VG |
652 | * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc) |
653 | * However in one instance, when called by kprobe (for a breakpt in | |
94bad1af VG |
654 | * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will |
655 | * use a paddr to index the cache (despite VIPT). This is fine since since a | |
4b06ff35 VG |
656 | * builtin kernel page will not have any virtual mappings. |
657 | * kprobe on loadable module will be kernel vaddr. | |
95d6976d | 658 | */ |
94bad1af | 659 | void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len) |
95d6976d | 660 | { |
f538881c | 661 | __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV); |
2328af0c | 662 | __ic_line_inv_vaddr(paddr, vaddr, len); |
95d6976d VG |
663 | } |
664 | ||
24603fdd VG |
665 | /* wrapper to compile time eliminate alignment checks in flush loop */ |
666 | void __inv_icache_page(unsigned long paddr, unsigned long vaddr) | |
95d6976d | 667 | { |
24603fdd | 668 | __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE); |
95d6976d VG |
669 | } |
670 | ||
6ec18a81 VG |
671 | /* |
672 | * wrapper to clearout kernel or userspace mappings of a page | |
673 | * For kernel mappings @vaddr == @paddr | |
674 | */ | |
45309493 | 675 | void __flush_dcache_page(unsigned long paddr, unsigned long vaddr) |
eacd0e95 | 676 | { |
6ec18a81 | 677 | __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV); |
eacd0e95 VG |
678 | } |
679 | ||
95d6976d VG |
680 | noinline void flush_cache_all(void) |
681 | { | |
682 | unsigned long flags; | |
683 | ||
684 | local_irq_save(flags); | |
685 | ||
336e199e | 686 | __ic_entire_inv(); |
95d6976d VG |
687 | __dc_entire_op(OP_FLUSH_N_INV); |
688 | ||
689 | local_irq_restore(flags); | |
690 | ||
691 | } | |
692 | ||
4102b533 VG |
693 | #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING |
694 | ||
695 | void flush_cache_mm(struct mm_struct *mm) | |
696 | { | |
697 | flush_cache_all(); | |
698 | } | |
699 | ||
700 | void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr, | |
701 | unsigned long pfn) | |
702 | { | |
703 | unsigned int paddr = pfn << PAGE_SHIFT; | |
704 | ||
5971bc71 VG |
705 | u_vaddr &= PAGE_MASK; |
706 | ||
45309493 | 707 | __flush_dcache_page(paddr, u_vaddr); |
5971bc71 VG |
708 | |
709 | if (vma->vm_flags & VM_EXEC) | |
710 | __inv_icache_page(paddr, u_vaddr); | |
4102b533 VG |
711 | } |
712 | ||
713 | void flush_cache_range(struct vm_area_struct *vma, unsigned long start, | |
714 | unsigned long end) | |
715 | { | |
716 | flush_cache_all(); | |
717 | } | |
718 | ||
7bb66f6e VG |
719 | void flush_anon_page(struct vm_area_struct *vma, struct page *page, |
720 | unsigned long u_vaddr) | |
721 | { | |
722 | /* TBD: do we really need to clear the kernel mapping */ | |
723 | __flush_dcache_page(page_address(page), u_vaddr); | |
724 | __flush_dcache_page(page_address(page), page_address(page)); | |
725 | ||
726 | } | |
727 | ||
728 | #endif | |
729 | ||
4102b533 VG |
730 | void copy_user_highpage(struct page *to, struct page *from, |
731 | unsigned long u_vaddr, struct vm_area_struct *vma) | |
732 | { | |
45309493 VG |
733 | unsigned long kfrom = (unsigned long)page_address(from); |
734 | unsigned long kto = (unsigned long)page_address(to); | |
4102b533 VG |
735 | int clean_src_k_mappings = 0; |
736 | ||
737 | /* | |
738 | * If SRC page was already mapped in userspace AND it's U-mapping is | |
739 | * not congruent with K-mapping, sync former to physical page so that | |
740 | * K-mapping in memcpy below, sees the right data | |
741 | * | |
742 | * Note that while @u_vaddr refers to DST page's userspace vaddr, it is | |
743 | * equally valid for SRC page as well | |
744 | */ | |
745 | if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) { | |
746 | __flush_dcache_page(kfrom, u_vaddr); | |
747 | clean_src_k_mappings = 1; | |
748 | } | |
749 | ||
45309493 | 750 | copy_page((void *)kto, (void *)kfrom); |
4102b533 VG |
751 | |
752 | /* | |
753 | * Mark DST page K-mapping as dirty for a later finalization by | |
754 | * update_mmu_cache(). Although the finalization could have been done | |
755 | * here as well (given that both vaddr/paddr are available). | |
756 | * But update_mmu_cache() already has code to do that for other | |
757 | * non copied user pages (e.g. read faults which wire in pagecache page | |
758 | * directly). | |
759 | */ | |
2ed21dae | 760 | clear_bit(PG_dc_clean, &to->flags); |
4102b533 VG |
761 | |
762 | /* | |
763 | * if SRC was already usermapped and non-congruent to kernel mapping | |
764 | * sync the kernel mapping back to physical page | |
765 | */ | |
766 | if (clean_src_k_mappings) { | |
767 | __flush_dcache_page(kfrom, kfrom); | |
2ed21dae | 768 | set_bit(PG_dc_clean, &from->flags); |
4102b533 | 769 | } else { |
2ed21dae | 770 | clear_bit(PG_dc_clean, &from->flags); |
4102b533 VG |
771 | } |
772 | } | |
773 | ||
774 | void clear_user_page(void *to, unsigned long u_vaddr, struct page *page) | |
775 | { | |
776 | clear_page(to); | |
2ed21dae | 777 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
778 | } |
779 | ||
4102b533 | 780 | |
95d6976d VG |
781 | /********************************************************************** |
782 | * Explicit Cache flush request from user space via syscall | |
783 | * Needed for JITs which generate code on the fly | |
784 | */ | |
785 | SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags) | |
786 | { | |
787 | /* TBD: optimize this */ | |
788 | flush_cache_all(); | |
789 | return 0; | |
790 | } | |
8ea2ddff VG |
791 | |
792 | void arc_cache_init(void) | |
793 | { | |
794 | unsigned int __maybe_unused cpu = smp_processor_id(); | |
795 | char str[256]; | |
796 | ||
797 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); | |
798 | ||
799 | if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { | |
800 | struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; | |
801 | ||
802 | if (!ic->ver) | |
803 | panic("cache support enabled but non-existent cache\n"); | |
804 | ||
805 | if (ic->line_len != L1_CACHE_BYTES) | |
806 | panic("ICache line [%d] != kernel Config [%d]", | |
807 | ic->line_len, L1_CACHE_BYTES); | |
808 | ||
809 | if (ic->ver != CONFIG_ARC_MMU_VER) | |
810 | panic("Cache ver [%d] doesn't match MMU ver [%d]\n", | |
811 | ic->ver, CONFIG_ARC_MMU_VER); | |
bcc4d65a VG |
812 | |
813 | /* | |
814 | * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG | |
815 | * pair to provide vaddr/paddr respectively, just as in MMU v3 | |
816 | */ | |
817 | if (is_isa_arcv2() && ic->alias) | |
818 | _cache_line_loop_ic_fn = __cache_line_loop_v3; | |
819 | else | |
820 | _cache_line_loop_ic_fn = __cache_line_loop; | |
8ea2ddff VG |
821 | } |
822 | ||
823 | if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { | |
824 | struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; | |
8ea2ddff VG |
825 | |
826 | if (!dc->ver) | |
827 | panic("cache support enabled but non-existent cache\n"); | |
828 | ||
829 | if (dc->line_len != L1_CACHE_BYTES) | |
830 | panic("DCache line [%d] != kernel Config [%d]", | |
831 | dc->line_len, L1_CACHE_BYTES); | |
832 | ||
d1f317d8 VG |
833 | /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ |
834 | if (is_isa_arcompact()) { | |
835 | int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); | |
8ea2ddff | 836 | |
d1f317d8 VG |
837 | if (dc->alias && !handled) |
838 | panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | |
839 | else if (!dc->alias && handled) | |
840 | panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | |
841 | } | |
8ea2ddff VG |
842 | } |
843 | } |