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Commit | Line | Data |
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95d6976d | 1 | /* |
8ea2ddff | 2 | * ARC Cache Management |
95d6976d | 3 | * |
8ea2ddff | 4 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) |
95d6976d VG |
5 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
95d6976d VG |
10 | */ |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/cache.h> | |
16 | #include <linux/mmu_context.h> | |
17 | #include <linux/syscalls.h> | |
18 | #include <linux/uaccess.h> | |
4102b533 | 19 | #include <linux/pagemap.h> |
95d6976d VG |
20 | #include <asm/cacheflush.h> |
21 | #include <asm/cachectl.h> | |
22 | #include <asm/setup.h> | |
23 | ||
795f4558 | 24 | static int l2_line_sz; |
cf986d47 | 25 | static int ioc_exists; |
d0e73e2a | 26 | int slc_enable = 1, ioc_enable = 1; |
deaf7565 | 27 | unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */ |
26c01c49 | 28 | unsigned long perip_end = 0xFFFFFFFF; /* legacy value */ |
795f4558 | 29 | |
28b4af72 | 30 | void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr, |
bcc4d65a VG |
31 | unsigned long sz, const int cacheop); |
32 | ||
f5db19e9 VG |
33 | void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz); |
34 | void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz); | |
35 | void (*__dma_cache_wback)(phys_addr_t start, unsigned long sz); | |
f2b0b25a | 36 | |
c3441edd | 37 | char *arc_cache_mumbojumbo(int c, char *buf, int len) |
af617428 VG |
38 | { |
39 | int n = 0; | |
d1f317d8 | 40 | struct cpuinfo_arc_cache *p; |
af617428 | 41 | |
da40ff48 | 42 | #define PR_CACHE(p, cfg, str) \ |
f64915be | 43 | if (!(p)->line_len) \ |
af617428 VG |
44 | n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ |
45 | else \ | |
46 | n += scnprintf(buf + n, len - n, \ | |
da40ff48 VG |
47 | str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \ |
48 | (p)->sz_k, (p)->assoc, (p)->line_len, \ | |
49 | (p)->vipt ? "VIPT" : "PIPT", \ | |
50 | (p)->alias ? " aliasing" : "", \ | |
964cf28f | 51 | IS_USED_CFG(cfg)); |
af617428 | 52 | |
da40ff48 VG |
53 | PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); |
54 | PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); | |
af617428 | 55 | |
d1f317d8 | 56 | p = &cpuinfo_arc700[c].slc; |
f64915be | 57 | if (p->line_len) |
d1f317d8 | 58 | n += scnprintf(buf + n, len - n, |
79335a2c VG |
59 | "SLC\t\t: %uK, %uB Line%s\n", |
60 | p->sz_k, p->line_len, IS_USED_RUN(slc_enable)); | |
d1f317d8 | 61 | |
711c1f26 VG |
62 | n += scnprintf(buf + n, len - n, "Peripherals\t: %#lx%s%s\n", |
63 | perip_base, | |
64 | IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency ")); | |
f2b0b25a | 65 | |
af617428 VG |
66 | return buf; |
67 | } | |
68 | ||
95d6976d VG |
69 | /* |
70 | * Read the Cache Build Confuration Registers, Decode them and save into | |
71 | * the cpuinfo structure for later use. | |
72 | * No Validation done here, simply read/convert the BCRs | |
73 | */ | |
fd0881a2 | 74 | static void read_decode_cache_bcr_arcv2(int cpu) |
95d6976d | 75 | { |
fd0881a2 | 76 | struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc; |
d1f317d8 VG |
77 | struct bcr_generic sbcr; |
78 | ||
79 | struct bcr_slc_cfg { | |
80 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
81 | unsigned int pad:24, way:2, lsz:2, sz:4; | |
82 | #else | |
83 | unsigned int sz:4, lsz:2, way:2, pad:24; | |
84 | #endif | |
85 | } slc_cfg; | |
86 | ||
f2b0b25a AB |
87 | struct bcr_clust_cfg { |
88 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
89 | unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; | |
90 | #else | |
91 | unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; | |
92 | #endif | |
93 | } cbcr; | |
94 | ||
26c01c49 VG |
95 | struct bcr_volatile { |
96 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
97 | unsigned int start:4, limit:4, pad:22, order:1, disable:1; | |
98 | #else | |
99 | unsigned int disable:1, order:1, pad:22, limit:4, start:4; | |
100 | #endif | |
101 | } vol; | |
102 | ||
103 | ||
fd0881a2 VG |
104 | READ_BCR(ARC_REG_SLC_BCR, sbcr); |
105 | if (sbcr.ver) { | |
106 | READ_BCR(ARC_REG_SLC_CFG, slc_cfg); | |
fd0881a2 VG |
107 | p_slc->sz_k = 128 << slc_cfg.sz; |
108 | l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64; | |
109 | } | |
110 | ||
111 | READ_BCR(ARC_REG_CLUSTER_BCR, cbcr); | |
cf986d47 | 112 | if (cbcr.c) |
fd0881a2 | 113 | ioc_exists = 1; |
cf986d47 VG |
114 | else |
115 | ioc_enable = 0; | |
deaf7565 | 116 | |
26c01c49 VG |
117 | /* HS 2.0 didn't have AUX_VOL */ |
118 | if (cpuinfo_arc700[cpu].core.family > 0x51) { | |
119 | READ_BCR(AUX_VOL, vol); | |
120 | perip_base = vol.start << 28; | |
121 | /* HS 3.0 has limit and strict-ordering fields */ | |
122 | if (cpuinfo_arc700[cpu].core.family > 0x52) | |
123 | perip_end = (vol.limit << 28) - 1; | |
124 | } | |
fd0881a2 VG |
125 | } |
126 | ||
127 | void read_decode_cache_bcr(void) | |
128 | { | |
129 | struct cpuinfo_arc_cache *p_ic, *p_dc; | |
130 | unsigned int cpu = smp_processor_id(); | |
131 | struct bcr_cache { | |
132 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
133 | unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; | |
134 | #else | |
135 | unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; | |
136 | #endif | |
137 | } ibcr, dbcr; | |
138 | ||
95d6976d VG |
139 | p_ic = &cpuinfo_arc700[cpu].icache; |
140 | READ_BCR(ARC_REG_IC_BCR, ibcr); | |
141 | ||
da40ff48 VG |
142 | if (!ibcr.ver) |
143 | goto dc_chk; | |
144 | ||
d1f317d8 VG |
145 | if (ibcr.ver <= 3) { |
146 | BUG_ON(ibcr.config != 3); | |
147 | p_ic->assoc = 2; /* Fixed to 2w set assoc */ | |
148 | } else if (ibcr.ver >= 4) { | |
149 | p_ic->assoc = 1 << ibcr.config; /* 1,2,4,8 */ | |
150 | } | |
151 | ||
95d6976d | 152 | p_ic->line_len = 8 << ibcr.line_len; |
da40ff48 | 153 | p_ic->sz_k = 1 << (ibcr.sz - 1); |
da40ff48 VG |
154 | p_ic->vipt = 1; |
155 | p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1; | |
95d6976d | 156 | |
da40ff48 | 157 | dc_chk: |
95d6976d VG |
158 | p_dc = &cpuinfo_arc700[cpu].dcache; |
159 | READ_BCR(ARC_REG_DC_BCR, dbcr); | |
160 | ||
da40ff48 | 161 | if (!dbcr.ver) |
d1f317d8 VG |
162 | goto slc_chk; |
163 | ||
164 | if (dbcr.ver <= 3) { | |
165 | BUG_ON(dbcr.config != 2); | |
166 | p_dc->assoc = 4; /* Fixed to 4w set assoc */ | |
167 | p_dc->vipt = 1; | |
168 | p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1; | |
169 | } else if (dbcr.ver >= 4) { | |
170 | p_dc->assoc = 1 << dbcr.config; /* 1,2,4,8 */ | |
171 | p_dc->vipt = 0; | |
172 | p_dc->alias = 0; /* PIPT so can't VIPT alias */ | |
173 | } | |
da40ff48 | 174 | |
95d6976d | 175 | p_dc->line_len = 16 << dbcr.line_len; |
da40ff48 | 176 | p_dc->sz_k = 1 << (dbcr.sz - 1); |
d1f317d8 VG |
177 | |
178 | slc_chk: | |
fd0881a2 VG |
179 | if (is_isa_arcv2()) |
180 | read_decode_cache_bcr_arcv2(cpu); | |
95d6976d VG |
181 | } |
182 | ||
183 | /* | |
8ea2ddff | 184 | * Line Operation on {I,D}-Cache |
95d6976d | 185 | */ |
95d6976d VG |
186 | |
187 | #define OP_INV 0x1 | |
188 | #define OP_FLUSH 0x2 | |
189 | #define OP_FLUSH_N_INV 0x3 | |
bd12976c VG |
190 | #define OP_INV_IC 0x4 |
191 | ||
192 | /* | |
8ea2ddff VG |
193 | * I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3) |
194 | * | |
195 | * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag. | |
196 | * The orig Cache Management Module "CDU" only required paddr to invalidate a | |
197 | * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry. | |
198 | * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching | |
199 | * the exact same line. | |
200 | * | |
201 | * However for larger Caches (way-size > page-size) - i.e. in Aliasing config, | |
202 | * paddr alone could not be used to correctly index the cache. | |
203 | * | |
204 | * ------------------ | |
205 | * MMU v1/v2 (Fixed Page Size 8k) | |
206 | * ------------------ | |
207 | * The solution was to provide CDU with these additonal vaddr bits. These | |
208 | * would be bits [x:13], x would depend on cache-geometry, 13 comes from | |
209 | * standard page size of 8k. | |
210 | * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits | |
211 | * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the | |
212 | * orig 5 bits of paddr were anyways ignored by CDU line ops, as they | |
213 | * represent the offset within cache-line. The adv of using this "clumsy" | |
214 | * interface for additional info was no new reg was needed in CDU programming | |
215 | * model. | |
216 | * | |
217 | * 17:13 represented the max num of bits passable, actual bits needed were | |
218 | * fewer, based on the num-of-aliases possible. | |
219 | * -for 2 alias possibility, only bit 13 needed (32K cache) | |
220 | * -for 4 alias possibility, bits 14:13 needed (64K cache) | |
221 | * | |
222 | * ------------------ | |
223 | * MMU v3 | |
224 | * ------------------ | |
225 | * This ver of MMU supports variable page sizes (1k-16k): although Linux will | |
226 | * only support 8k (default), 16k and 4k. | |
2547476a | 227 | * However from hardware perspective, smaller page sizes aggravate aliasing |
8ea2ddff VG |
228 | * meaning more vaddr bits needed to disambiguate the cache-line-op ; |
229 | * the existing scheme of piggybacking won't work for certain configurations. | |
230 | * Two new registers IC_PTAG and DC_PTAG inttoduced. | |
231 | * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs | |
bd12976c | 232 | */ |
8ea2ddff | 233 | |
11e14896 | 234 | static inline |
28b4af72 | 235 | void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr, |
11e14896 | 236 | unsigned long sz, const int op) |
bd12976c | 237 | { |
11e14896 | 238 | unsigned int aux_cmd; |
bd12976c | 239 | int num_lines; |
11e14896 | 240 | const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE; |
bd12976c | 241 | |
8ea2ddff | 242 | if (op == OP_INV_IC) { |
bd12976c | 243 | aux_cmd = ARC_REG_IC_IVIL; |
11e14896 | 244 | } else { |
bd12976c | 245 | /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ |
8ea2ddff | 246 | aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; |
bd12976c VG |
247 | } |
248 | ||
249 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
250 | * and have @paddr - aligned to cache line and integral @num_lines. | |
251 | * This however can be avoided for page sized since: | |
252 | * -@paddr will be cache-line aligned already (being page aligned) | |
253 | * -@sz will be integral multiple of line size (being page sized). | |
254 | */ | |
11e14896 | 255 | if (!full_page) { |
bd12976c VG |
256 | sz += paddr & ~CACHE_LINE_MASK; |
257 | paddr &= CACHE_LINE_MASK; | |
258 | vaddr &= CACHE_LINE_MASK; | |
259 | } | |
260 | ||
261 | num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); | |
262 | ||
bd12976c VG |
263 | /* MMUv2 and before: paddr contains stuffed vaddrs bits */ |
264 | paddr |= (vaddr >> PAGE_SHIFT) & 0x1F; | |
11e14896 VG |
265 | |
266 | while (num_lines-- > 0) { | |
267 | write_aux_reg(aux_cmd, paddr); | |
268 | paddr += L1_CACHE_BYTES; | |
269 | } | |
270 | } | |
271 | ||
5a364c2a VG |
272 | /* |
273 | * For ARC700 MMUv3 I-cache and D-cache flushes | |
fa84d731 VG |
274 | * - ARC700 programming model requires paddr and vaddr be passed in seperate |
275 | * AUX registers (*_IV*L and *_PTAG respectively) irrespective of whether the | |
276 | * caches actually alias or not. | |
277 | * - For HS38, only the aliasing I-cache configuration uses the PTAG reg | |
278 | * (non aliasing I-cache version doesn't; while D-cache can't possibly alias) | |
5a364c2a | 279 | */ |
11e14896 | 280 | static inline |
28b4af72 | 281 | void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr, |
11e14896 VG |
282 | unsigned long sz, const int op) |
283 | { | |
284 | unsigned int aux_cmd, aux_tag; | |
285 | int num_lines; | |
286 | const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE; | |
287 | ||
288 | if (op == OP_INV_IC) { | |
289 | aux_cmd = ARC_REG_IC_IVIL; | |
290 | aux_tag = ARC_REG_IC_PTAG; | |
291 | } else { | |
292 | aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; | |
293 | aux_tag = ARC_REG_DC_PTAG; | |
294 | } | |
295 | ||
296 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
297 | * and have @paddr - aligned to cache line and integral @num_lines. | |
298 | * This however can be avoided for page sized since: | |
299 | * -@paddr will be cache-line aligned already (being page aligned) | |
300 | * -@sz will be integral multiple of line size (being page sized). | |
301 | */ | |
302 | if (!full_page) { | |
303 | sz += paddr & ~CACHE_LINE_MASK; | |
304 | paddr &= CACHE_LINE_MASK; | |
305 | vaddr &= CACHE_LINE_MASK; | |
306 | } | |
307 | num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); | |
308 | ||
309 | /* | |
310 | * MMUv3, cache ops require paddr in PTAG reg | |
311 | * if V-P const for loop, PTAG can be written once outside loop | |
312 | */ | |
313 | if (full_page) | |
b053940d | 314 | write_aux_reg(aux_tag, paddr); |
bd12976c | 315 | |
5a364c2a VG |
316 | /* |
317 | * This is technically for MMU v4, using the MMU v3 programming model | |
2547476a | 318 | * Special work for HS38 aliasing I-cache configuration with PAE40 |
5a364c2a VG |
319 | * - upper 8 bits of paddr need to be written into PTAG_HI |
320 | * - (and needs to be written before the lower 32 bits) | |
321 | * Note that PTAG_HI is hoisted outside the line loop | |
322 | */ | |
323 | if (is_pae40_enabled() && op == OP_INV_IC) | |
324 | write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32); | |
325 | ||
bd12976c | 326 | while (num_lines-- > 0) { |
11e14896 | 327 | if (!full_page) { |
d4599baf VG |
328 | write_aux_reg(aux_tag, paddr); |
329 | paddr += L1_CACHE_BYTES; | |
330 | } | |
bd12976c VG |
331 | |
332 | write_aux_reg(aux_cmd, vaddr); | |
333 | vaddr += L1_CACHE_BYTES; | |
bd12976c VG |
334 | } |
335 | } | |
95d6976d | 336 | |
d1f317d8 | 337 | /* |
5a364c2a VG |
338 | * In HS38x (MMU v4), I-cache is VIPT (can alias), D-cache is PIPT |
339 | * Here's how cache ops are implemented | |
d1f317d8 | 340 | * |
5a364c2a VG |
341 | * - D-cache: only paddr needed (in DC_IVDL/DC_FLDL) |
342 | * - I-cache Non Aliasing: Despite VIPT, only paddr needed (in IC_IVIL) | |
343 | * - I-cache Aliasing: Both vaddr and paddr needed (in IC_IVIL, IC_PTAG | |
344 | * respectively, similar to MMU v3 programming model, hence | |
345 | * __cache_line_loop_v3() is used) | |
346 | * | |
347 | * If PAE40 is enabled, independent of aliasing considerations, the higher bits | |
348 | * needs to be written into PTAG_HI | |
d1f317d8 VG |
349 | */ |
350 | static inline | |
28b4af72 | 351 | void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr, |
d1f317d8 VG |
352 | unsigned long sz, const int cacheop) |
353 | { | |
354 | unsigned int aux_cmd; | |
355 | int num_lines; | |
356 | const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE; | |
357 | ||
358 | if (cacheop == OP_INV_IC) { | |
359 | aux_cmd = ARC_REG_IC_IVIL; | |
360 | } else { | |
361 | /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ | |
362 | aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; | |
363 | } | |
364 | ||
365 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
366 | * and have @paddr - aligned to cache line and integral @num_lines. | |
367 | * This however can be avoided for page sized since: | |
368 | * -@paddr will be cache-line aligned already (being page aligned) | |
369 | * -@sz will be integral multiple of line size (being page sized). | |
370 | */ | |
371 | if (!full_page_op) { | |
372 | sz += paddr & ~CACHE_LINE_MASK; | |
373 | paddr &= CACHE_LINE_MASK; | |
374 | } | |
375 | ||
376 | num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); | |
377 | ||
5a364c2a VG |
378 | /* |
379 | * For HS38 PAE40 configuration | |
380 | * - upper 8 bits of paddr need to be written into PTAG_HI | |
381 | * - (and needs to be written before the lower 32 bits) | |
382 | */ | |
383 | if (is_pae40_enabled()) { | |
384 | if (cacheop == OP_INV_IC) | |
385 | /* | |
386 | * Non aliasing I-cache in HS38, | |
387 | * aliasing I-cache handled in __cache_line_loop_v3() | |
388 | */ | |
389 | write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32); | |
390 | else | |
391 | write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32); | |
392 | } | |
393 | ||
d1f317d8 VG |
394 | while (num_lines-- > 0) { |
395 | write_aux_reg(aux_cmd, paddr); | |
396 | paddr += L1_CACHE_BYTES; | |
397 | } | |
398 | } | |
399 | ||
11e14896 VG |
400 | #if (CONFIG_ARC_MMU_VER < 3) |
401 | #define __cache_line_loop __cache_line_loop_v2 | |
402 | #elif (CONFIG_ARC_MMU_VER == 3) | |
403 | #define __cache_line_loop __cache_line_loop_v3 | |
d1f317d8 VG |
404 | #elif (CONFIG_ARC_MMU_VER > 3) |
405 | #define __cache_line_loop __cache_line_loop_v4 | |
11e14896 VG |
406 | #endif |
407 | ||
95d6976d VG |
408 | #ifdef CONFIG_ARC_HAS_DCACHE |
409 | ||
410 | /*************************************************************** | |
411 | * Machine specific helpers for Entire D-Cache or Per Line ops | |
412 | */ | |
413 | ||
6c310681 | 414 | static inline void __before_dc_op(const int op) |
95d6976d | 415 | { |
1b1a22b1 VG |
416 | if (op == OP_FLUSH_N_INV) { |
417 | /* Dcache provides 2 cmd: FLUSH or INV | |
418 | * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE | |
419 | * flush-n-inv is achieved by INV cmd but with IM=1 | |
420 | * So toggle INV sub-mode depending on op request and default | |
421 | */ | |
6c310681 VG |
422 | const unsigned int ctl = ARC_REG_DC_CTRL; |
423 | write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); | |
1b1a22b1 | 424 | } |
1b1a22b1 VG |
425 | } |
426 | ||
6c310681 | 427 | static inline void __after_dc_op(const int op) |
1b1a22b1 | 428 | { |
6c310681 VG |
429 | if (op & OP_FLUSH) { |
430 | const unsigned int ctl = ARC_REG_DC_CTRL; | |
431 | unsigned int reg; | |
1b1a22b1 | 432 | |
6c310681 VG |
433 | /* flush / flush-n-inv both wait */ |
434 | while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS) | |
435 | ; | |
436 | ||
437 | /* Switch back to default Invalidate mode */ | |
438 | if (op == OP_FLUSH_N_INV) | |
439 | write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH); | |
440 | } | |
95d6976d VG |
441 | } |
442 | ||
443 | /* | |
444 | * Operation on Entire D-Cache | |
8ea2ddff | 445 | * @op = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV} |
95d6976d VG |
446 | * Note that constant propagation ensures all the checks are gone |
447 | * in generated code | |
448 | */ | |
8ea2ddff | 449 | static inline void __dc_entire_op(const int op) |
95d6976d | 450 | { |
95d6976d VG |
451 | int aux; |
452 | ||
6c310681 | 453 | __before_dc_op(op); |
95d6976d | 454 | |
8ea2ddff | 455 | if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ |
95d6976d VG |
456 | aux = ARC_REG_DC_IVDC; |
457 | else | |
458 | aux = ARC_REG_DC_FLSH; | |
459 | ||
460 | write_aux_reg(aux, 0x1); | |
461 | ||
6c310681 | 462 | __after_dc_op(op); |
95d6976d VG |
463 | } |
464 | ||
8c47f83b VG |
465 | static inline void __dc_disable(void) |
466 | { | |
467 | const int r = ARC_REG_DC_CTRL; | |
468 | ||
469 | __dc_entire_op(OP_FLUSH_N_INV); | |
470 | write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS); | |
471 | } | |
472 | ||
473 | static void __dc_enable(void) | |
474 | { | |
475 | const int r = ARC_REG_DC_CTRL; | |
476 | ||
477 | write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS); | |
478 | } | |
479 | ||
4102b533 | 480 | /* For kernel mappings cache operation: index is same as paddr */ |
6ec18a81 VG |
481 | #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op) |
482 | ||
95d6976d | 483 | /* |
8ea2ddff | 484 | * D-Cache Line ops: Per Line INV (discard or wback+discard) or FLUSH (wback) |
95d6976d | 485 | */ |
28b4af72 | 486 | static inline void __dc_line_op(phys_addr_t paddr, unsigned long vaddr, |
8ea2ddff | 487 | unsigned long sz, const int op) |
95d6976d | 488 | { |
1b1a22b1 | 489 | unsigned long flags; |
95d6976d VG |
490 | |
491 | local_irq_save(flags); | |
492 | ||
6c310681 | 493 | __before_dc_op(op); |
95d6976d | 494 | |
8ea2ddff | 495 | __cache_line_loop(paddr, vaddr, sz, op); |
95d6976d | 496 | |
6c310681 | 497 | __after_dc_op(op); |
95d6976d VG |
498 | |
499 | local_irq_restore(flags); | |
500 | } | |
501 | ||
502 | #else | |
503 | ||
8ea2ddff | 504 | #define __dc_entire_op(op) |
8c47f83b VG |
505 | #define __dc_disable() |
506 | #define __dc_enable() | |
8ea2ddff VG |
507 | #define __dc_line_op(paddr, vaddr, sz, op) |
508 | #define __dc_line_op_k(paddr, sz, op) | |
95d6976d VG |
509 | |
510 | #endif /* CONFIG_ARC_HAS_DCACHE */ | |
511 | ||
95d6976d VG |
512 | #ifdef CONFIG_ARC_HAS_ICACHE |
513 | ||
af5abf1b VG |
514 | static inline void __ic_entire_inv(void) |
515 | { | |
516 | write_aux_reg(ARC_REG_IC_IVIC, 1); | |
517 | read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ | |
518 | } | |
519 | ||
520 | static inline void | |
28b4af72 | 521 | __ic_line_inv_vaddr_local(phys_addr_t paddr, unsigned long vaddr, |
af5abf1b | 522 | unsigned long sz) |
95d6976d VG |
523 | { |
524 | unsigned long flags; | |
95d6976d VG |
525 | |
526 | local_irq_save(flags); | |
bcc4d65a | 527 | (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC); |
95d6976d VG |
528 | local_irq_restore(flags); |
529 | } | |
530 | ||
af5abf1b VG |
531 | #ifndef CONFIG_SMP |
532 | ||
533 | #define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s) | |
534 | ||
535 | #else | |
336e199e | 536 | |
af5abf1b | 537 | struct ic_inv_args { |
28b4af72 | 538 | phys_addr_t paddr, vaddr; |
2328af0c VG |
539 | int sz; |
540 | }; | |
541 | ||
542 | static void __ic_line_inv_vaddr_helper(void *info) | |
543 | { | |
014018e0 | 544 | struct ic_inv_args *ic_inv = info; |
af5abf1b | 545 | |
2328af0c VG |
546 | __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz); |
547 | } | |
548 | ||
28b4af72 | 549 | static void __ic_line_inv_vaddr(phys_addr_t paddr, unsigned long vaddr, |
2328af0c VG |
550 | unsigned long sz) |
551 | { | |
af5abf1b VG |
552 | struct ic_inv_args ic_inv = { |
553 | .paddr = paddr, | |
554 | .vaddr = vaddr, | |
555 | .sz = sz | |
556 | }; | |
557 | ||
2328af0c VG |
558 | on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1); |
559 | } | |
af5abf1b VG |
560 | |
561 | #endif /* CONFIG_SMP */ | |
562 | ||
563 | #else /* !CONFIG_ARC_HAS_ICACHE */ | |
95d6976d | 564 | |
336e199e | 565 | #define __ic_entire_inv() |
95d6976d VG |
566 | #define __ic_line_inv_vaddr(pstart, vstart, sz) |
567 | ||
568 | #endif /* CONFIG_ARC_HAS_ICACHE */ | |
569 | ||
28b4af72 | 570 | noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) |
795f4558 VG |
571 | { |
572 | #ifdef CONFIG_ISA_ARCV2 | |
b607eddd AB |
573 | /* |
574 | * SLC is shared between all cores and concurrent aux operations from | |
575 | * multiple cores need to be serialized using a spinlock | |
576 | * A concurrent operation can be silently ignored and/or the old/new | |
577 | * operation can remain incomplete forever (lockup in SLC_CTRL_BUSY loop | |
578 | * below) | |
579 | */ | |
580 | static DEFINE_SPINLOCK(lock); | |
795f4558 VG |
581 | unsigned long flags; |
582 | unsigned int ctrl; | |
583 | ||
b607eddd | 584 | spin_lock_irqsave(&lock, flags); |
795f4558 VG |
585 | |
586 | /* | |
587 | * The Region Flush operation is specified by CTRL.RGN_OP[11..9] | |
588 | * - b'000 (default) is Flush, | |
589 | * - b'001 is Invalidate if CTRL.IM == 0 | |
590 | * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 | |
591 | */ | |
592 | ctrl = read_aux_reg(ARC_REG_SLC_CTRL); | |
593 | ||
594 | /* Don't rely on default value of IM bit */ | |
595 | if (!(op & OP_FLUSH)) /* i.e. OP_INV */ | |
596 | ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ | |
597 | else | |
598 | ctrl |= SLC_CTRL_IM; | |
599 | ||
600 | if (op & OP_INV) | |
601 | ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ | |
602 | else | |
603 | ctrl &= ~SLC_CTRL_RGN_OP_INV; | |
604 | ||
605 | write_aux_reg(ARC_REG_SLC_CTRL, ctrl); | |
606 | ||
607 | /* | |
608 | * Lower bits are ignored, no need to clip | |
609 | * END needs to be setup before START (latter triggers the operation) | |
610 | * END can't be same as START, so add (l2_line_sz - 1) to sz | |
611 | */ | |
612 | write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1)); | |
613 | write_aux_reg(ARC_REG_SLC_RGN_START, paddr); | |
614 | ||
615 | while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); | |
616 | ||
b607eddd | 617 | spin_unlock_irqrestore(&lock, flags); |
795f4558 VG |
618 | #endif |
619 | } | |
620 | ||
d4911cdd VG |
621 | noinline static void slc_entire_op(const int op) |
622 | { | |
623 | unsigned int ctrl, r = ARC_REG_SLC_CTRL; | |
624 | ||
625 | ctrl = read_aux_reg(r); | |
626 | ||
627 | if (!(op & OP_FLUSH)) /* i.e. OP_INV */ | |
628 | ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ | |
629 | else | |
630 | ctrl |= SLC_CTRL_IM; | |
631 | ||
632 | write_aux_reg(r, ctrl); | |
633 | ||
634 | write_aux_reg(ARC_REG_SLC_INVALIDATE, 1); | |
635 | ||
636 | /* Important to wait for flush to complete */ | |
637 | while (read_aux_reg(r) & SLC_CTRL_BUSY); | |
638 | } | |
639 | ||
640 | static inline void arc_slc_disable(void) | |
641 | { | |
642 | const int r = ARC_REG_SLC_CTRL; | |
643 | ||
644 | slc_entire_op(OP_FLUSH_N_INV); | |
645 | write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS); | |
646 | } | |
647 | ||
648 | static inline void arc_slc_enable(void) | |
649 | { | |
650 | const int r = ARC_REG_SLC_CTRL; | |
651 | ||
652 | write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS); | |
653 | } | |
654 | ||
95d6976d VG |
655 | /*********************************************************** |
656 | * Exported APIs | |
657 | */ | |
658 | ||
4102b533 VG |
659 | /* |
660 | * Handle cache congruency of kernel and userspace mappings of page when kernel | |
661 | * writes-to/reads-from | |
662 | * | |
663 | * The idea is to defer flushing of kernel mapping after a WRITE, possible if: | |
664 | * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent | |
665 | * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache) | |
666 | * -In SMP, if hardware caches are coherent | |
667 | * | |
668 | * There's a corollary case, where kernel READs from a userspace mapped page. | |
669 | * If the U-mapping is not congruent to to K-mapping, former needs flushing. | |
670 | */ | |
95d6976d VG |
671 | void flush_dcache_page(struct page *page) |
672 | { | |
4102b533 VG |
673 | struct address_space *mapping; |
674 | ||
675 | if (!cache_is_vipt_aliasing()) { | |
2ed21dae | 676 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
677 | return; |
678 | } | |
679 | ||
680 | /* don't handle anon pages here */ | |
681 | mapping = page_mapping(page); | |
682 | if (!mapping) | |
683 | return; | |
684 | ||
685 | /* | |
686 | * pagecache page, file not yet mapped to userspace | |
687 | * Make a note that K-mapping is dirty | |
688 | */ | |
689 | if (!mapping_mapped(mapping)) { | |
2ed21dae | 690 | clear_bit(PG_dc_clean, &page->flags); |
e1534ae9 | 691 | } else if (page_mapcount(page)) { |
4102b533 VG |
692 | |
693 | /* kernel reading from page with U-mapping */ | |
28b4af72 | 694 | phys_addr_t paddr = (unsigned long)page_address(page); |
09cbfeaf | 695 | unsigned long vaddr = page->index << PAGE_SHIFT; |
4102b533 VG |
696 | |
697 | if (addr_not_cache_congruent(paddr, vaddr)) | |
698 | __flush_dcache_page(paddr, vaddr); | |
699 | } | |
95d6976d VG |
700 | } |
701 | EXPORT_SYMBOL(flush_dcache_page); | |
702 | ||
f2b0b25a AB |
703 | /* |
704 | * DMA ops for systems with L1 cache only | |
705 | * Make memory coherent with L1 cache by flushing/invalidating L1 lines | |
706 | */ | |
f5db19e9 | 707 | static void __dma_cache_wback_inv_l1(phys_addr_t start, unsigned long sz) |
95d6976d | 708 | { |
6ec18a81 | 709 | __dc_line_op_k(start, sz, OP_FLUSH_N_INV); |
f2b0b25a | 710 | } |
795f4558 | 711 | |
f5db19e9 | 712 | static void __dma_cache_inv_l1(phys_addr_t start, unsigned long sz) |
f2b0b25a AB |
713 | { |
714 | __dc_line_op_k(start, sz, OP_INV); | |
95d6976d | 715 | } |
95d6976d | 716 | |
f5db19e9 | 717 | static void __dma_cache_wback_l1(phys_addr_t start, unsigned long sz) |
f2b0b25a AB |
718 | { |
719 | __dc_line_op_k(start, sz, OP_FLUSH); | |
720 | } | |
721 | ||
722 | /* | |
723 | * DMA ops for systems with both L1 and L2 caches, but without IOC | |
7423cc0c | 724 | * Both L1 and L2 lines need to be explicitly flushed/invalidated |
f2b0b25a | 725 | */ |
f5db19e9 | 726 | static void __dma_cache_wback_inv_slc(phys_addr_t start, unsigned long sz) |
f2b0b25a AB |
727 | { |
728 | __dc_line_op_k(start, sz, OP_FLUSH_N_INV); | |
729 | slc_op(start, sz, OP_FLUSH_N_INV); | |
730 | } | |
731 | ||
f5db19e9 | 732 | static void __dma_cache_inv_slc(phys_addr_t start, unsigned long sz) |
95d6976d | 733 | { |
6ec18a81 | 734 | __dc_line_op_k(start, sz, OP_INV); |
f2b0b25a AB |
735 | slc_op(start, sz, OP_INV); |
736 | } | |
795f4558 | 737 | |
f5db19e9 | 738 | static void __dma_cache_wback_slc(phys_addr_t start, unsigned long sz) |
f2b0b25a AB |
739 | { |
740 | __dc_line_op_k(start, sz, OP_FLUSH); | |
741 | slc_op(start, sz, OP_FLUSH); | |
742 | } | |
743 | ||
744 | /* | |
745 | * DMA ops for systems with IOC | |
746 | * IOC hardware snoops all DMA traffic keeping the caches consistent with | |
747 | * memory - eliding need for any explicit cache maintenance of DMA buffers | |
748 | */ | |
f5db19e9 VG |
749 | static void __dma_cache_wback_inv_ioc(phys_addr_t start, unsigned long sz) {} |
750 | static void __dma_cache_inv_ioc(phys_addr_t start, unsigned long sz) {} | |
751 | static void __dma_cache_wback_ioc(phys_addr_t start, unsigned long sz) {} | |
f2b0b25a AB |
752 | |
753 | /* | |
754 | * Exported DMA API | |
755 | */ | |
f5db19e9 | 756 | void dma_cache_wback_inv(phys_addr_t start, unsigned long sz) |
f2b0b25a AB |
757 | { |
758 | __dma_cache_wback_inv(start, sz); | |
759 | } | |
760 | EXPORT_SYMBOL(dma_cache_wback_inv); | |
761 | ||
f5db19e9 | 762 | void dma_cache_inv(phys_addr_t start, unsigned long sz) |
f2b0b25a AB |
763 | { |
764 | __dma_cache_inv(start, sz); | |
95d6976d VG |
765 | } |
766 | EXPORT_SYMBOL(dma_cache_inv); | |
767 | ||
f5db19e9 | 768 | void dma_cache_wback(phys_addr_t start, unsigned long sz) |
95d6976d | 769 | { |
f2b0b25a | 770 | __dma_cache_wback(start, sz); |
95d6976d VG |
771 | } |
772 | EXPORT_SYMBOL(dma_cache_wback); | |
773 | ||
774 | /* | |
7586bf72 VG |
775 | * This is API for making I/D Caches consistent when modifying |
776 | * kernel code (loadable modules, kprobes, kgdb...) | |
95d6976d VG |
777 | * This is called on insmod, with kernel virtual address for CODE of |
778 | * the module. ARC cache maintenance ops require PHY address thus we | |
779 | * need to convert vmalloc addr to PHY addr | |
780 | */ | |
781 | void flush_icache_range(unsigned long kstart, unsigned long kend) | |
782 | { | |
c59414cc | 783 | unsigned int tot_sz; |
95d6976d | 784 | |
c59414cc | 785 | WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__); |
95d6976d VG |
786 | |
787 | /* Shortcut for bigger flush ranges. | |
788 | * Here we don't care if this was kernel virtual or phy addr | |
789 | */ | |
790 | tot_sz = kend - kstart; | |
791 | if (tot_sz > PAGE_SIZE) { | |
792 | flush_cache_all(); | |
793 | return; | |
794 | } | |
795 | ||
796 | /* Case: Kernel Phy addr (0x8000_0000 onwards) */ | |
797 | if (likely(kstart > PAGE_OFFSET)) { | |
7586bf72 VG |
798 | /* |
799 | * The 2nd arg despite being paddr will be used to index icache | |
800 | * This is OK since no alternate virtual mappings will exist | |
801 | * given the callers for this case: kprobe/kgdb in built-in | |
802 | * kernel code only. | |
803 | */ | |
94bad1af | 804 | __sync_icache_dcache(kstart, kstart, kend - kstart); |
95d6976d VG |
805 | return; |
806 | } | |
807 | ||
808 | /* | |
809 | * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff) | |
810 | * (1) ARC Cache Maintenance ops only take Phy addr, hence special | |
811 | * handling of kernel vaddr. | |
812 | * | |
813 | * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already), | |
814 | * it still needs to handle a 2 page scenario, where the range | |
815 | * straddles across 2 virtual pages and hence need for loop | |
816 | */ | |
817 | while (tot_sz > 0) { | |
c59414cc VG |
818 | unsigned int off, sz; |
819 | unsigned long phy, pfn; | |
820 | ||
95d6976d VG |
821 | off = kstart % PAGE_SIZE; |
822 | pfn = vmalloc_to_pfn((void *)kstart); | |
823 | phy = (pfn << PAGE_SHIFT) + off; | |
824 | sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off); | |
94bad1af | 825 | __sync_icache_dcache(phy, kstart, sz); |
95d6976d VG |
826 | kstart += sz; |
827 | tot_sz -= sz; | |
828 | } | |
829 | } | |
e3560305 | 830 | EXPORT_SYMBOL(flush_icache_range); |
95d6976d VG |
831 | |
832 | /* | |
94bad1af VG |
833 | * General purpose helper to make I and D cache lines consistent. |
834 | * @paddr is phy addr of region | |
4b06ff35 VG |
835 | * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc) |
836 | * However in one instance, when called by kprobe (for a breakpt in | |
94bad1af VG |
837 | * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will |
838 | * use a paddr to index the cache (despite VIPT). This is fine since since a | |
4b06ff35 VG |
839 | * builtin kernel page will not have any virtual mappings. |
840 | * kprobe on loadable module will be kernel vaddr. | |
95d6976d | 841 | */ |
28b4af72 | 842 | void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len) |
95d6976d | 843 | { |
f538881c | 844 | __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV); |
2328af0c | 845 | __ic_line_inv_vaddr(paddr, vaddr, len); |
95d6976d VG |
846 | } |
847 | ||
24603fdd | 848 | /* wrapper to compile time eliminate alignment checks in flush loop */ |
28b4af72 | 849 | void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr) |
95d6976d | 850 | { |
24603fdd | 851 | __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE); |
95d6976d VG |
852 | } |
853 | ||
6ec18a81 VG |
854 | /* |
855 | * wrapper to clearout kernel or userspace mappings of a page | |
856 | * For kernel mappings @vaddr == @paddr | |
857 | */ | |
28b4af72 | 858 | void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr) |
eacd0e95 | 859 | { |
6ec18a81 | 860 | __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV); |
eacd0e95 VG |
861 | } |
862 | ||
95d6976d VG |
863 | noinline void flush_cache_all(void) |
864 | { | |
865 | unsigned long flags; | |
866 | ||
867 | local_irq_save(flags); | |
868 | ||
336e199e | 869 | __ic_entire_inv(); |
95d6976d VG |
870 | __dc_entire_op(OP_FLUSH_N_INV); |
871 | ||
872 | local_irq_restore(flags); | |
873 | ||
874 | } | |
875 | ||
4102b533 VG |
876 | #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING |
877 | ||
878 | void flush_cache_mm(struct mm_struct *mm) | |
879 | { | |
880 | flush_cache_all(); | |
881 | } | |
882 | ||
883 | void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr, | |
884 | unsigned long pfn) | |
885 | { | |
886 | unsigned int paddr = pfn << PAGE_SHIFT; | |
887 | ||
5971bc71 VG |
888 | u_vaddr &= PAGE_MASK; |
889 | ||
45309493 | 890 | __flush_dcache_page(paddr, u_vaddr); |
5971bc71 VG |
891 | |
892 | if (vma->vm_flags & VM_EXEC) | |
893 | __inv_icache_page(paddr, u_vaddr); | |
4102b533 VG |
894 | } |
895 | ||
896 | void flush_cache_range(struct vm_area_struct *vma, unsigned long start, | |
897 | unsigned long end) | |
898 | { | |
899 | flush_cache_all(); | |
900 | } | |
901 | ||
7bb66f6e VG |
902 | void flush_anon_page(struct vm_area_struct *vma, struct page *page, |
903 | unsigned long u_vaddr) | |
904 | { | |
905 | /* TBD: do we really need to clear the kernel mapping */ | |
906 | __flush_dcache_page(page_address(page), u_vaddr); | |
907 | __flush_dcache_page(page_address(page), page_address(page)); | |
908 | ||
909 | } | |
910 | ||
911 | #endif | |
912 | ||
4102b533 VG |
913 | void copy_user_highpage(struct page *to, struct page *from, |
914 | unsigned long u_vaddr, struct vm_area_struct *vma) | |
915 | { | |
336e2136 VG |
916 | void *kfrom = kmap_atomic(from); |
917 | void *kto = kmap_atomic(to); | |
4102b533 VG |
918 | int clean_src_k_mappings = 0; |
919 | ||
920 | /* | |
921 | * If SRC page was already mapped in userspace AND it's U-mapping is | |
922 | * not congruent with K-mapping, sync former to physical page so that | |
923 | * K-mapping in memcpy below, sees the right data | |
924 | * | |
925 | * Note that while @u_vaddr refers to DST page's userspace vaddr, it is | |
926 | * equally valid for SRC page as well | |
336e2136 VG |
927 | * |
928 | * For !VIPT cache, all of this gets compiled out as | |
929 | * addr_not_cache_congruent() is 0 | |
4102b533 | 930 | */ |
e1534ae9 | 931 | if (page_mapcount(from) && addr_not_cache_congruent(kfrom, u_vaddr)) { |
336e2136 | 932 | __flush_dcache_page((unsigned long)kfrom, u_vaddr); |
4102b533 VG |
933 | clean_src_k_mappings = 1; |
934 | } | |
935 | ||
336e2136 | 936 | copy_page(kto, kfrom); |
4102b533 VG |
937 | |
938 | /* | |
939 | * Mark DST page K-mapping as dirty for a later finalization by | |
940 | * update_mmu_cache(). Although the finalization could have been done | |
941 | * here as well (given that both vaddr/paddr are available). | |
942 | * But update_mmu_cache() already has code to do that for other | |
943 | * non copied user pages (e.g. read faults which wire in pagecache page | |
944 | * directly). | |
945 | */ | |
2ed21dae | 946 | clear_bit(PG_dc_clean, &to->flags); |
4102b533 VG |
947 | |
948 | /* | |
949 | * if SRC was already usermapped and non-congruent to kernel mapping | |
950 | * sync the kernel mapping back to physical page | |
951 | */ | |
952 | if (clean_src_k_mappings) { | |
336e2136 | 953 | __flush_dcache_page((unsigned long)kfrom, (unsigned long)kfrom); |
2ed21dae | 954 | set_bit(PG_dc_clean, &from->flags); |
4102b533 | 955 | } else { |
2ed21dae | 956 | clear_bit(PG_dc_clean, &from->flags); |
4102b533 | 957 | } |
336e2136 VG |
958 | |
959 | kunmap_atomic(kto); | |
960 | kunmap_atomic(kfrom); | |
4102b533 VG |
961 | } |
962 | ||
963 | void clear_user_page(void *to, unsigned long u_vaddr, struct page *page) | |
964 | { | |
965 | clear_page(to); | |
2ed21dae | 966 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
967 | } |
968 | ||
4102b533 | 969 | |
95d6976d VG |
970 | /********************************************************************** |
971 | * Explicit Cache flush request from user space via syscall | |
972 | * Needed for JITs which generate code on the fly | |
973 | */ | |
974 | SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags) | |
975 | { | |
976 | /* TBD: optimize this */ | |
977 | flush_cache_all(); | |
978 | return 0; | |
979 | } | |
8ea2ddff | 980 | |
8c47f83b VG |
981 | /* |
982 | * IO-Coherency (IOC) setup rules: | |
983 | * | |
984 | * 1. Needs to be at system level, so only once by Master core | |
985 | * Non-Masters need not be accessing caches at that time | |
986 | * - They are either HALT_ON_RESET and kick started much later or | |
987 | * - if run on reset, need to ensure that arc_platform_smp_wait_to_boot() | |
988 | * doesn't perturb caches or coherency unit | |
989 | * | |
990 | * 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC, | |
991 | * otherwise any straggler data might behave strangely post IOC enabling | |
992 | * | |
993 | * 3. All Caches need to be disabled when setting up IOC to elide any in-flight | |
994 | * Coherency transactions | |
995 | */ | |
76894a72 | 996 | noinline void __init arc_ioc_setup(void) |
d4911cdd | 997 | { |
e497c8e5 VG |
998 | unsigned int ap_sz; |
999 | ||
8c47f83b VG |
1000 | /* Flush + invalidate + disable L1 dcache */ |
1001 | __dc_disable(); | |
1002 | ||
1003 | /* Flush + invalidate SLC */ | |
1004 | if (read_aux_reg(ARC_REG_SLC_BCR)) | |
1005 | slc_entire_op(OP_FLUSH_N_INV); | |
1006 | ||
1007 | /* IOC Aperture start: TDB: handle non default CONFIG_LINUX_LINK_BASE */ | |
d4911cdd | 1008 | write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000); |
8c47f83b | 1009 | |
e497c8e5 VG |
1010 | /* |
1011 | * IOC Aperture size: | |
1012 | * decoded as 2 ^ (SIZE + 2) KB: so setting 0x11 implies 512M | |
1013 | * TBD: fix for PGU + 1GB of low mem | |
1014 | * TBD: fix for PAE | |
1015 | */ | |
1016 | ap_sz = order_base_2(arc_get_mem_sz()/1024) - 2; | |
1017 | write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, ap_sz); | |
8c47f83b | 1018 | |
d4911cdd VG |
1019 | write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1); |
1020 | write_aux_reg(ARC_REG_IO_COH_ENABLE, 1); | |
8c47f83b VG |
1021 | |
1022 | /* Re-enable L1 dcache */ | |
1023 | __dc_enable(); | |
d4911cdd VG |
1024 | } |
1025 | ||
76894a72 | 1026 | void __init arc_cache_init_master(void) |
8ea2ddff VG |
1027 | { |
1028 | unsigned int __maybe_unused cpu = smp_processor_id(); | |
45c3b08a | 1029 | |
8ea2ddff VG |
1030 | if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { |
1031 | struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; | |
1032 | ||
f64915be | 1033 | if (!ic->line_len) |
8ea2ddff VG |
1034 | panic("cache support enabled but non-existent cache\n"); |
1035 | ||
1036 | if (ic->line_len != L1_CACHE_BYTES) | |
1037 | panic("ICache line [%d] != kernel Config [%d]", | |
1038 | ic->line_len, L1_CACHE_BYTES); | |
1039 | ||
bcc4d65a | 1040 | /* |
2547476a | 1041 | * In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG |
bcc4d65a VG |
1042 | * pair to provide vaddr/paddr respectively, just as in MMU v3 |
1043 | */ | |
1044 | if (is_isa_arcv2() && ic->alias) | |
1045 | _cache_line_loop_ic_fn = __cache_line_loop_v3; | |
1046 | else | |
1047 | _cache_line_loop_ic_fn = __cache_line_loop; | |
8ea2ddff VG |
1048 | } |
1049 | ||
1050 | if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { | |
1051 | struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; | |
8ea2ddff | 1052 | |
f64915be | 1053 | if (!dc->line_len) |
8ea2ddff VG |
1054 | panic("cache support enabled but non-existent cache\n"); |
1055 | ||
1056 | if (dc->line_len != L1_CACHE_BYTES) | |
1057 | panic("DCache line [%d] != kernel Config [%d]", | |
1058 | dc->line_len, L1_CACHE_BYTES); | |
1059 | ||
d1f317d8 VG |
1060 | /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ |
1061 | if (is_isa_arcompact()) { | |
1062 | int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); | |
08fe0079 VG |
1063 | int num_colors = dc->sz_k/dc->assoc/TO_KB(PAGE_SIZE); |
1064 | ||
1065 | if (dc->alias) { | |
1066 | if (!handled) | |
1067 | panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | |
1068 | if (CACHE_COLORS_NUM != num_colors) | |
1069 | panic("CACHE_COLORS_NUM not optimized for config\n"); | |
1070 | } else if (!dc->alias && handled) { | |
d1f317d8 | 1071 | panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); |
08fe0079 | 1072 | } |
d1f317d8 | 1073 | } |
8ea2ddff | 1074 | } |
f2b0b25a | 1075 | |
d4911cdd VG |
1076 | /* Note that SLC disable not formally supported till HS 3.0 */ |
1077 | if (is_isa_arcv2() && l2_line_sz && !slc_enable) | |
1078 | arc_slc_disable(); | |
79335a2c | 1079 | |
d4911cdd VG |
1080 | if (is_isa_arcv2() && ioc_enable) |
1081 | arc_ioc_setup(); | |
79335a2c | 1082 | |
cf986d47 | 1083 | if (is_isa_arcv2() && ioc_enable) { |
f2b0b25a AB |
1084 | __dma_cache_wback_inv = __dma_cache_wback_inv_ioc; |
1085 | __dma_cache_inv = __dma_cache_inv_ioc; | |
1086 | __dma_cache_wback = __dma_cache_wback_ioc; | |
79335a2c | 1087 | } else if (is_isa_arcv2() && l2_line_sz && slc_enable) { |
f2b0b25a AB |
1088 | __dma_cache_wback_inv = __dma_cache_wback_inv_slc; |
1089 | __dma_cache_inv = __dma_cache_inv_slc; | |
1090 | __dma_cache_wback = __dma_cache_wback_slc; | |
1091 | } else { | |
1092 | __dma_cache_wback_inv = __dma_cache_wback_inv_l1; | |
1093 | __dma_cache_inv = __dma_cache_inv_l1; | |
1094 | __dma_cache_wback = __dma_cache_wback_l1; | |
1095 | } | |
8ea2ddff | 1096 | } |
76894a72 VG |
1097 | |
1098 | void __ref arc_cache_init(void) | |
1099 | { | |
1100 | unsigned int __maybe_unused cpu = smp_processor_id(); | |
1101 | char str[256]; | |
1102 | ||
1103 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); | |
1104 | ||
1105 | /* | |
1106 | * Only master CPU needs to execute rest of function: | |
1107 | * - Assume SMP so all cores will have same cache config so | |
1108 | * any geomtry checks will be same for all | |
1109 | * - IOC setup / dma callbacks only need to be setup once | |
1110 | */ | |
1111 | if (!cpu) | |
1112 | arc_cache_init_master(); | |
1113 | } |