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f1f3347d VG |
1 | /* |
2 | * TLB Management (flush/create/diagnostics) for ARC700 | |
3 | * | |
4 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
d79e678d VG |
9 | * |
10 | * vineetg: Aug 2011 | |
11 | * -Reintroduce duplicate PD fixup - some customer chips still have the issue | |
12 | * | |
13 | * vineetg: May 2011 | |
14 | * -No need to flush_cache_page( ) for each call to update_mmu_cache() | |
15 | * some of the LMBench tests improved amazingly | |
16 | * = page-fault thrice as fast (75 usec to 28 usec) | |
17 | * = mmap twice as fast (9.6 msec to 4.6 msec), | |
18 | * = fork (5.3 msec to 3.7 msec) | |
19 | * | |
20 | * vineetg: April 2011 : | |
21 | * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore, | |
22 | * helps avoid a shift when preparing PD0 from PTE | |
23 | * | |
24 | * vineetg: April 2011 : Preparing for MMU V3 | |
25 | * -MMU v2/v3 BCRs decoded differently | |
26 | * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512 | |
27 | * -tlb_entry_erase( ) can be void | |
28 | * -local_flush_tlb_range( ): | |
29 | * = need not "ceil" @end | |
30 | * = walks MMU only if range spans < 32 entries, as opposed to 256 | |
31 | * | |
32 | * Vineetg: Sept 10th 2008 | |
33 | * -Changes related to MMU v2 (Rel 4.8) | |
34 | * | |
35 | * Vineetg: Aug 29th 2008 | |
36 | * -In TLB Flush operations (Metal Fix MMU) there is a explict command to | |
37 | * flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd, | |
38 | * it fails. Thus need to load it with ANY valid value before invoking | |
39 | * TLBIVUTLB cmd | |
40 | * | |
41 | * Vineetg: Aug 21th 2008: | |
42 | * -Reduced the duration of IRQ lockouts in TLB Flush routines | |
43 | * -Multiple copies of TLB erase code seperated into a "single" function | |
44 | * -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID | |
45 | * in interrupt-safe region. | |
46 | * | |
47 | * Vineetg: April 23rd Bug #93131 | |
7423cc0c | 48 | * Problem: tlb_flush_kernel_range() doesn't do anything if the range to |
d79e678d VG |
49 | * flush is more than the size of TLB itself. |
50 | * | |
51 | * Rahul Trivedi : Codito Technologies 2004 | |
f1f3347d VG |
52 | */ |
53 | ||
54 | #include <linux/module.h> | |
483e9bcb | 55 | #include <linux/bug.h> |
589ee628 IM |
56 | #include <linux/mm_types.h> |
57 | ||
f1f3347d | 58 | #include <asm/arcregs.h> |
d79e678d | 59 | #include <asm/setup.h> |
f1f3347d | 60 | #include <asm/mmu_context.h> |
da1677b0 | 61 | #include <asm/mmu.h> |
f1f3347d | 62 | |
d79e678d VG |
63 | /* Need for ARC MMU v2 |
64 | * | |
65 | * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc. | |
66 | * For a memcpy operation with 3 players (src/dst/code) such that all 3 pages | |
67 | * map into same set, there would be contention for the 2 ways causing severe | |
68 | * Thrashing. | |
69 | * | |
70 | * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has | |
71 | * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways. | |
72 | * Given this, the thrasing problem should never happen because once the 3 | |
73 | * J-TLB entries are created (even though 3rd will knock out one of the prev | |
74 | * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy | |
75 | * | |
76 | * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs. | |
77 | * This is a simple design for keeping them in sync. So what do we do? | |
78 | * The solution which James came up was pretty neat. It utilised the assoc | |
79 | * of uTLBs by not invalidating always but only when absolutely necessary. | |
80 | * | |
81 | * - Existing TLB commands work as before | |
82 | * - New command (TLBWriteNI) for TLB write without clearing uTLBs | |
83 | * - New command (TLBIVUTLB) to invalidate uTLBs. | |
84 | * | |
85 | * The uTLBs need only be invalidated when pages are being removed from the | |
86 | * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB | |
87 | * as a result of a miss, the removed entry is still allowed to exist in the | |
88 | * uTLBs as it is still valid and present in the OS page table. This allows the | |
89 | * full associativity of the uTLBs to hide the limited associativity of the main | |
90 | * TLB. | |
91 | * | |
92 | * During a miss handler, the new "TLBWriteNI" command is used to load | |
93 | * entries without clearing the uTLBs. | |
94 | * | |
95 | * When the OS page table is updated, TLB entries that may be associated with a | |
96 | * removed page are removed (flushed) from the TLB using TLBWrite. In this | |
97 | * circumstance, the uTLBs must also be cleared. This is done by using the | |
98 | * existing TLBWrite command. An explicit IVUTLB is also required for those | |
99 | * corner cases when TLBWrite was not executed at all because the corresp | |
100 | * J-TLB entry got evicted/replaced. | |
101 | */ | |
102 | ||
da1677b0 | 103 | |
f1f3347d | 104 | /* A copy of the ASID from the PID reg is kept in asid_cache */ |
63eca94c | 105 | DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE; |
cc562d2e | 106 | |
b5ddb6d5 VG |
107 | static int __read_mostly pae_exists; |
108 | ||
d79e678d VG |
109 | /* |
110 | * Utility Routine to erase a J-TLB entry | |
483e9bcb | 111 | * Caller needs to setup Index Reg (manually or via getIndex) |
d79e678d | 112 | */ |
483e9bcb | 113 | static inline void __tlb_entry_erase(void) |
d79e678d VG |
114 | { |
115 | write_aux_reg(ARC_REG_TLBPD1, 0); | |
5a364c2a VG |
116 | |
117 | if (is_pae40_enabled()) | |
118 | write_aux_reg(ARC_REG_TLBPD1HI, 0); | |
119 | ||
d79e678d VG |
120 | write_aux_reg(ARC_REG_TLBPD0, 0); |
121 | write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); | |
122 | } | |
123 | ||
d7a512bf VG |
124 | #if (CONFIG_ARC_MMU_VER < 4) |
125 | ||
483e9bcb | 126 | static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid) |
d79e678d VG |
127 | { |
128 | unsigned int idx; | |
129 | ||
d79e678d | 130 | write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); |
483e9bcb | 131 | |
d79e678d VG |
132 | write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe); |
133 | idx = read_aux_reg(ARC_REG_TLBINDEX); | |
134 | ||
483e9bcb VG |
135 | return idx; |
136 | } | |
137 | ||
138 | static void tlb_entry_erase(unsigned int vaddr_n_asid) | |
139 | { | |
140 | unsigned int idx; | |
141 | ||
142 | /* Locate the TLB entry for this vaddr + ASID */ | |
143 | idx = tlb_entry_lkup(vaddr_n_asid); | |
144 | ||
d79e678d VG |
145 | /* No error means entry found, zero it out */ |
146 | if (likely(!(idx & TLB_LKUP_ERR))) { | |
147 | __tlb_entry_erase(); | |
483e9bcb | 148 | } else { |
d79e678d | 149 | /* Duplicate entry error */ |
483e9bcb VG |
150 | WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n", |
151 | vaddr_n_asid); | |
d79e678d VG |
152 | } |
153 | } | |
154 | ||
155 | /**************************************************************************** | |
156 | * ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs) | |
157 | * | |
158 | * New IVUTLB cmd in MMU v2 explictly invalidates the uTLB | |
159 | * | |
160 | * utlb_invalidate ( ) | |
161 | * -For v2 MMU calls Flush uTLB Cmd | |
162 | * -For v1 MMU does nothing (except for Metal Fix v1 MMU) | |
163 | * This is because in v1 TLBWrite itself invalidate uTLBs | |
164 | ***************************************************************************/ | |
165 | ||
166 | static void utlb_invalidate(void) | |
167 | { | |
168 | #if (CONFIG_ARC_MMU_VER >= 2) | |
169 | ||
483e9bcb | 170 | #if (CONFIG_ARC_MMU_VER == 2) |
d79e678d VG |
171 | /* MMU v2 introduced the uTLB Flush command. |
172 | * There was however an obscure hardware bug, where uTLB flush would | |
173 | * fail when a prior probe for J-TLB (both totally unrelated) would | |
7423cc0c | 174 | * return lkup err - because the entry didn't exist in MMU. |
d79e678d VG |
175 | * The Workround was to set Index reg with some valid value, prior to |
176 | * flush. This was fixed in MMU v3 hence not needed any more | |
177 | */ | |
178 | unsigned int idx; | |
179 | ||
180 | /* make sure INDEX Reg is valid */ | |
181 | idx = read_aux_reg(ARC_REG_TLBINDEX); | |
182 | ||
183 | /* If not write some dummy val */ | |
184 | if (unlikely(idx & TLB_LKUP_ERR)) | |
185 | write_aux_reg(ARC_REG_TLBINDEX, 0xa); | |
186 | #endif | |
187 | ||
188 | write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB); | |
189 | #endif | |
190 | ||
191 | } | |
192 | ||
5a364c2a | 193 | static void tlb_entry_insert(unsigned int pd0, pte_t pd1) |
483e9bcb VG |
194 | { |
195 | unsigned int idx; | |
196 | ||
197 | /* | |
198 | * First verify if entry for this vaddr+ASID already exists | |
199 | * This also sets up PD0 (vaddr, ASID..) for final commit | |
200 | */ | |
201 | idx = tlb_entry_lkup(pd0); | |
202 | ||
203 | /* | |
204 | * If Not already present get a free slot from MMU. | |
205 | * Otherwise, Probe would have located the entry and set INDEX Reg | |
206 | * with existing location. This will cause Write CMD to over-write | |
207 | * existing entry with new PD0 and PD1 | |
208 | */ | |
209 | if (likely(idx & TLB_LKUP_ERR)) | |
210 | write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex); | |
211 | ||
212 | /* setup the other half of TLB entry (pfn, rwx..) */ | |
213 | write_aux_reg(ARC_REG_TLBPD1, pd1); | |
214 | ||
215 | /* | |
216 | * Commit the Entry to MMU | |
7423cc0c | 217 | * It doesn't sound safe to use the TLBWriteNI cmd here |
483e9bcb VG |
218 | * which doesn't flush uTLBs. I'd rather be safe than sorry. |
219 | */ | |
220 | write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); | |
221 | } | |
222 | ||
d7a512bf VG |
223 | #else /* CONFIG_ARC_MMU_VER >= 4) */ |
224 | ||
225 | static void utlb_invalidate(void) | |
226 | { | |
227 | /* No need since uTLB is always in sync with JTLB */ | |
228 | } | |
229 | ||
230 | static void tlb_entry_erase(unsigned int vaddr_n_asid) | |
231 | { | |
232 | write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT); | |
233 | write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry); | |
234 | } | |
235 | ||
5a364c2a | 236 | static void tlb_entry_insert(unsigned int pd0, pte_t pd1) |
d7a512bf VG |
237 | { |
238 | write_aux_reg(ARC_REG_TLBPD0, pd0); | |
239 | write_aux_reg(ARC_REG_TLBPD1, pd1); | |
5a364c2a VG |
240 | |
241 | if (is_pae40_enabled()) | |
242 | write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32); | |
243 | ||
d7a512bf VG |
244 | write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry); |
245 | } | |
246 | ||
247 | #endif | |
248 | ||
d79e678d VG |
249 | /* |
250 | * Un-conditionally (without lookup) erase the entire MMU contents | |
251 | */ | |
252 | ||
253 | noinline void local_flush_tlb_all(void) | |
254 | { | |
b598e17f | 255 | struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu; |
d79e678d VG |
256 | unsigned long flags; |
257 | unsigned int entry; | |
b598e17f | 258 | int num_tlb = mmu->sets * mmu->ways; |
d79e678d VG |
259 | |
260 | local_irq_save(flags); | |
261 | ||
262 | /* Load PD0 and PD1 with template for a Blank Entry */ | |
263 | write_aux_reg(ARC_REG_TLBPD1, 0); | |
5a364c2a VG |
264 | |
265 | if (is_pae40_enabled()) | |
266 | write_aux_reg(ARC_REG_TLBPD1HI, 0); | |
267 | ||
d79e678d VG |
268 | write_aux_reg(ARC_REG_TLBPD0, 0); |
269 | ||
b598e17f | 270 | for (entry = 0; entry < num_tlb; entry++) { |
d79e678d VG |
271 | /* write this entry to the TLB */ |
272 | write_aux_reg(ARC_REG_TLBINDEX, entry); | |
273 | write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); | |
274 | } | |
275 | ||
fe6c1b86 VG |
276 | if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) { |
277 | const int stlb_idx = 0x800; | |
278 | ||
279 | /* Blank sTLB entry */ | |
280 | write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ); | |
281 | ||
282 | for (entry = stlb_idx; entry < stlb_idx + 16; entry++) { | |
283 | write_aux_reg(ARC_REG_TLBINDEX, entry); | |
284 | write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); | |
285 | } | |
286 | } | |
287 | ||
d79e678d VG |
288 | utlb_invalidate(); |
289 | ||
290 | local_irq_restore(flags); | |
291 | } | |
292 | ||
293 | /* | |
294 | * Flush the entrie MM for userland. The fastest way is to move to Next ASID | |
295 | */ | |
296 | noinline void local_flush_tlb_mm(struct mm_struct *mm) | |
297 | { | |
298 | /* | |
299 | * Small optimisation courtesy IA64 | |
300 | * flush_mm called during fork,exit,munmap etc, multiple times as well. | |
301 | * Only for fork( ) do we need to move parent to a new MMU ctxt, | |
302 | * all other cases are NOPs, hence this check. | |
303 | */ | |
304 | if (atomic_read(&mm->mm_users) == 0) | |
305 | return; | |
306 | ||
307 | /* | |
3daa48d1 VG |
308 | * - Move to a new ASID, but only if the mm is still wired in |
309 | * (Android Binder ended up calling this for vma->mm != tsk->mm, | |
310 | * causing h/w - s/w ASID to get out of sync) | |
311 | * - Also get_new_mmu_context() new implementation allocates a new | |
312 | * ASID only if it is not allocated already - so unallocate first | |
d79e678d | 313 | */ |
3daa48d1 VG |
314 | destroy_context(mm); |
315 | if (current->mm == mm) | |
d79e678d VG |
316 | get_new_mmu_context(mm); |
317 | } | |
318 | ||
319 | /* | |
320 | * Flush a Range of TLB entries for userland. | |
321 | * @start is inclusive, while @end is exclusive | |
322 | * Difference between this and Kernel Range Flush is | |
323 | * -Here the fastest way (if range is too large) is to move to next ASID | |
324 | * without doing any explicit Shootdown | |
325 | * -In case of kernel Flush, entry has to be shot down explictly | |
326 | */ | |
327 | void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |
328 | unsigned long end) | |
329 | { | |
63eca94c | 330 | const unsigned int cpu = smp_processor_id(); |
d79e678d | 331 | unsigned long flags; |
d79e678d VG |
332 | |
333 | /* If range @start to @end is more than 32 TLB entries deep, | |
334 | * its better to move to a new ASID rather than searching for | |
335 | * individual entries and then shooting them down | |
336 | * | |
337 | * The calc above is rough, doesn't account for unaligned parts, | |
338 | * since this is heuristics based anyways | |
339 | */ | |
340 | if (unlikely((end - start) >= PAGE_SIZE * 32)) { | |
341 | local_flush_tlb_mm(vma->vm_mm); | |
342 | return; | |
343 | } | |
344 | ||
345 | /* | |
346 | * @start moved to page start: this alone suffices for checking | |
347 | * loop end condition below, w/o need for aligning @end to end | |
348 | * e.g. 2000 to 4001 will anyhow loop twice | |
349 | */ | |
350 | start &= PAGE_MASK; | |
351 | ||
352 | local_irq_save(flags); | |
d79e678d | 353 | |
63eca94c | 354 | if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) { |
d79e678d | 355 | while (start < end) { |
63eca94c | 356 | tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu)); |
d79e678d VG |
357 | start += PAGE_SIZE; |
358 | } | |
359 | } | |
360 | ||
361 | utlb_invalidate(); | |
362 | ||
363 | local_irq_restore(flags); | |
364 | } | |
365 | ||
366 | /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective) | |
367 | * @start, @end interpreted as kvaddr | |
368 | * Interestingly, shared TLB entries can also be flushed using just | |
369 | * @start,@end alone (interpreted as user vaddr), although technically SASID | |
370 | * is also needed. However our smart TLbProbe lookup takes care of that. | |
371 | */ | |
372 | void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
373 | { | |
374 | unsigned long flags; | |
375 | ||
376 | /* exactly same as above, except for TLB entry not taking ASID */ | |
377 | ||
378 | if (unlikely((end - start) >= PAGE_SIZE * 32)) { | |
379 | local_flush_tlb_all(); | |
380 | return; | |
381 | } | |
382 | ||
383 | start &= PAGE_MASK; | |
384 | ||
385 | local_irq_save(flags); | |
386 | while (start < end) { | |
387 | tlb_entry_erase(start); | |
388 | start += PAGE_SIZE; | |
389 | } | |
390 | ||
391 | utlb_invalidate(); | |
392 | ||
393 | local_irq_restore(flags); | |
394 | } | |
395 | ||
396 | /* | |
397 | * Delete TLB entry in MMU for a given page (??? address) | |
398 | * NOTE One TLB entry contains translation for single PAGE | |
399 | */ | |
400 | ||
401 | void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
402 | { | |
63eca94c | 403 | const unsigned int cpu = smp_processor_id(); |
d79e678d VG |
404 | unsigned long flags; |
405 | ||
406 | /* Note that it is critical that interrupts are DISABLED between | |
407 | * checking the ASID and using it flush the TLB entry | |
408 | */ | |
409 | local_irq_save(flags); | |
410 | ||
63eca94c VG |
411 | if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) { |
412 | tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu)); | |
d79e678d VG |
413 | utlb_invalidate(); |
414 | } | |
415 | ||
416 | local_irq_restore(flags); | |
417 | } | |
cc562d2e | 418 | |
5ea72a90 VG |
419 | #ifdef CONFIG_SMP |
420 | ||
421 | struct tlb_args { | |
422 | struct vm_area_struct *ta_vma; | |
423 | unsigned long ta_start; | |
424 | unsigned long ta_end; | |
425 | }; | |
426 | ||
427 | static inline void ipi_flush_tlb_page(void *arg) | |
428 | { | |
429 | struct tlb_args *ta = arg; | |
430 | ||
431 | local_flush_tlb_page(ta->ta_vma, ta->ta_start); | |
432 | } | |
433 | ||
434 | static inline void ipi_flush_tlb_range(void *arg) | |
435 | { | |
436 | struct tlb_args *ta = arg; | |
437 | ||
438 | local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end); | |
439 | } | |
440 | ||
c7119d56 VG |
441 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
442 | static inline void ipi_flush_pmd_tlb_range(void *arg) | |
443 | { | |
444 | struct tlb_args *ta = arg; | |
445 | ||
446 | local_flush_pmd_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end); | |
447 | } | |
448 | #endif | |
449 | ||
5ea72a90 VG |
450 | static inline void ipi_flush_tlb_kernel_range(void *arg) |
451 | { | |
452 | struct tlb_args *ta = (struct tlb_args *)arg; | |
453 | ||
454 | local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end); | |
455 | } | |
456 | ||
457 | void flush_tlb_all(void) | |
458 | { | |
459 | on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1); | |
460 | } | |
461 | ||
462 | void flush_tlb_mm(struct mm_struct *mm) | |
463 | { | |
464 | on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm, | |
465 | mm, 1); | |
466 | } | |
467 | ||
468 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | |
469 | { | |
470 | struct tlb_args ta = { | |
471 | .ta_vma = vma, | |
472 | .ta_start = uaddr | |
473 | }; | |
474 | ||
475 | on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1); | |
476 | } | |
477 | ||
478 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |
479 | unsigned long end) | |
480 | { | |
481 | struct tlb_args ta = { | |
482 | .ta_vma = vma, | |
483 | .ta_start = start, | |
484 | .ta_end = end | |
485 | }; | |
486 | ||
487 | on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1); | |
488 | } | |
489 | ||
c7119d56 VG |
490 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
491 | void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, | |
492 | unsigned long end) | |
493 | { | |
494 | struct tlb_args ta = { | |
495 | .ta_vma = vma, | |
496 | .ta_start = start, | |
497 | .ta_end = end | |
498 | }; | |
499 | ||
500 | on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_pmd_tlb_range, &ta, 1); | |
501 | } | |
502 | #endif | |
503 | ||
5ea72a90 VG |
504 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) |
505 | { | |
506 | struct tlb_args ta = { | |
507 | .ta_start = start, | |
508 | .ta_end = end | |
509 | }; | |
510 | ||
511 | on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); | |
512 | } | |
513 | #endif | |
514 | ||
cc562d2e VG |
515 | /* |
516 | * Routine to create a TLB entry | |
517 | */ | |
28b4af72 | 518 | void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, pte_t *ptep) |
cc562d2e VG |
519 | { |
520 | unsigned long flags; | |
483e9bcb | 521 | unsigned int asid_or_sasid, rwx; |
5a364c2a VG |
522 | unsigned long pd0; |
523 | pte_t pd1; | |
cc562d2e VG |
524 | |
525 | /* | |
526 | * create_tlb() assumes that current->mm == vma->mm, since | |
527 | * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr) | |
528 | * -completes the lazy write to SASID reg (again valid for curr tsk) | |
529 | * | |
530 | * Removing the assumption involves | |
531 | * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg. | |
532 | * -Fix the TLB paranoid debug code to not trigger false negatives. | |
533 | * -More importantly it makes this handler inconsistent with fast-path | |
534 | * TLB Refill handler which always deals with "current" | |
535 | * | |
536 | * Lets see the use cases when current->mm != vma->mm and we land here | |
537 | * 1. execve->copy_strings()->__get_user_pages->handle_mm_fault | |
538 | * Here VM wants to pre-install a TLB entry for user stack while | |
539 | * current->mm still points to pre-execve mm (hence the condition). | |
540 | * However the stack vaddr is soon relocated (randomization) and | |
541 | * move_page_tables() tries to undo that TLB entry. | |
542 | * Thus not creating TLB entry is not any worse. | |
543 | * | |
544 | * 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a | |
545 | * breakpoint in debugged task. Not creating a TLB now is not | |
546 | * performance critical. | |
547 | * | |
548 | * Both the cases above are not good enough for code churn. | |
549 | */ | |
550 | if (current->active_mm != vma->vm_mm) | |
551 | return; | |
552 | ||
553 | local_irq_save(flags); | |
554 | ||
28b4af72 | 555 | tlb_paranoid_check(asid_mm(vma->vm_mm, smp_processor_id()), vaddr); |
cc562d2e | 556 | |
28b4af72 | 557 | vaddr &= PAGE_MASK; |
cc562d2e VG |
558 | |
559 | /* update this PTE credentials */ | |
560 | pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED); | |
561 | ||
d091fcb9 | 562 | /* Create HW TLB(PD0,PD1) from PTE */ |
cc562d2e VG |
563 | |
564 | /* ASID for this task */ | |
565 | asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff; | |
566 | ||
28b4af72 | 567 | pd0 = vaddr | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0); |
cc562d2e | 568 | |
64b703ef VG |
569 | /* |
570 | * ARC MMU provides fully orthogonal access bits for K/U mode, | |
571 | * however Linux only saves 1 set to save PTE real-estate | |
572 | * Here we convert 3 PTE bits into 6 MMU bits: | |
573 | * -Kernel only entries have Kr Kw Kx 0 0 0 | |
574 | * -User entries have mirrored K and U bits | |
575 | */ | |
576 | rwx = pte_val(*ptep) & PTE_BITS_RWX; | |
577 | ||
578 | if (pte_val(*ptep) & _PAGE_GLOBAL) | |
579 | rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */ | |
580 | else | |
581 | rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */ | |
582 | ||
483e9bcb | 583 | pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1); |
cc562d2e | 584 | |
483e9bcb | 585 | tlb_entry_insert(pd0, pd1); |
cc562d2e VG |
586 | |
587 | local_irq_restore(flags); | |
588 | } | |
589 | ||
eacd0e95 VG |
590 | /* |
591 | * Called at the end of pagefault, for a userspace mapped page | |
592 | * -pre-install the corresponding TLB entry into MMU | |
4102b533 VG |
593 | * -Finalize the delayed D-cache flush of kernel mapping of page due to |
594 | * flush_dcache_page(), copy_user_page() | |
595 | * | |
596 | * Note that flush (when done) involves both WBACK - so physical page is | |
597 | * in sync as well as INV - so any non-congruent aliases don't remain | |
cc562d2e | 598 | */ |
24603fdd | 599 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned, |
cc562d2e VG |
600 | pte_t *ptep) |
601 | { | |
24603fdd | 602 | unsigned long vaddr = vaddr_unaligned & PAGE_MASK; |
28b4af72 | 603 | phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK; |
29b93c68 | 604 | struct page *page = pfn_to_page(pte_pfn(*ptep)); |
24603fdd VG |
605 | |
606 | create_tlb(vma, vaddr, ptep); | |
cc562d2e | 607 | |
29b93c68 VG |
608 | if (page == ZERO_PAGE(0)) { |
609 | return; | |
610 | } | |
611 | ||
4102b533 VG |
612 | /* |
613 | * Exec page : Independent of aliasing/page-color considerations, | |
614 | * since icache doesn't snoop dcache on ARC, any dirty | |
615 | * K-mapping of a code page needs to be wback+inv so that | |
616 | * icache fetch by userspace sees code correctly. | |
617 | * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it | |
618 | * so userspace sees the right data. | |
619 | * (Avoids the flush for Non-exec + congruent mapping case) | |
620 | */ | |
3e87974d VG |
621 | if ((vma->vm_flags & VM_EXEC) || |
622 | addr_not_cache_congruent(paddr, vaddr)) { | |
eacd0e95 | 623 | |
2ed21dae | 624 | int dirty = !test_and_set_bit(PG_dc_clean, &page->flags); |
eacd0e95 | 625 | if (dirty) { |
61a16348 | 626 | /* wback + inv dcache lines (K-mapping) */ |
6ec18a81 | 627 | __flush_dcache_page(paddr, paddr); |
4102b533 | 628 | |
61a16348 | 629 | /* invalidate any existing icache lines (U-mapping) */ |
4102b533 VG |
630 | if (vma->vm_flags & VM_EXEC) |
631 | __inv_icache_page(paddr, vaddr); | |
eacd0e95 | 632 | } |
24603fdd | 633 | } |
cc562d2e VG |
634 | } |
635 | ||
fe6c1b86 VG |
636 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
637 | ||
638 | /* | |
639 | * MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP | |
640 | * support. | |
641 | * | |
642 | * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a | |
7423cc0c | 643 | * new bit "SZ" in TLB page descriptor to distinguish between them. |
fe6c1b86 VG |
644 | * Super Page size is configurable in hardware (4K to 16M), but fixed once |
645 | * RTL builds. | |
646 | * | |
647 | * The exact THP size a Linx configuration will support is a function of: | |
648 | * - MMU page size (typical 8K, RTL fixed) | |
649 | * - software page walker address split between PGD:PTE:PFN (typical | |
650 | * 11:8:13, but can be changed with 1 line) | |
651 | * So for above default, THP size supported is 8K * (2^8) = 2M | |
652 | * | |
653 | * Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime | |
654 | * reduces to 1 level (as PTE is folded into PGD and canonically referred | |
655 | * to as PMD). | |
656 | * Thus THP PMD accessors are implemented in terms of PTE (just like sparc) | |
657 | */ | |
658 | ||
659 | void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, | |
660 | pmd_t *pmd) | |
661 | { | |
662 | pte_t pte = __pte(pmd_val(*pmd)); | |
663 | update_mmu_cache(vma, addr, &pte); | |
664 | } | |
665 | ||
666 | void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, | |
667 | pgtable_t pgtable) | |
668 | { | |
669 | struct list_head *lh = (struct list_head *) pgtable; | |
670 | ||
671 | assert_spin_locked(&mm->page_table_lock); | |
672 | ||
673 | /* FIFO */ | |
674 | if (!pmd_huge_pte(mm, pmdp)) | |
675 | INIT_LIST_HEAD(lh); | |
676 | else | |
677 | list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp)); | |
678 | pmd_huge_pte(mm, pmdp) = pgtable; | |
679 | } | |
680 | ||
681 | pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp) | |
682 | { | |
683 | struct list_head *lh; | |
684 | pgtable_t pgtable; | |
685 | ||
686 | assert_spin_locked(&mm->page_table_lock); | |
687 | ||
688 | pgtable = pmd_huge_pte(mm, pmdp); | |
689 | lh = (struct list_head *) pgtable; | |
690 | if (list_empty(lh)) | |
691 | pmd_huge_pte(mm, pmdp) = NULL; | |
692 | else { | |
693 | pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next; | |
694 | list_del(lh); | |
695 | } | |
696 | ||
697 | pte_val(pgtable[0]) = 0; | |
698 | pte_val(pgtable[1]) = 0; | |
699 | ||
700 | return pgtable; | |
701 | } | |
702 | ||
c7119d56 VG |
703 | void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, |
704 | unsigned long end) | |
722fe8fd VG |
705 | { |
706 | unsigned int cpu; | |
707 | unsigned long flags; | |
708 | ||
709 | local_irq_save(flags); | |
710 | ||
711 | cpu = smp_processor_id(); | |
712 | ||
713 | if (likely(asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID)) { | |
714 | unsigned int asid = hw_pid(vma->vm_mm, cpu); | |
715 | ||
716 | /* No need to loop here: this will always be for 1 Huge Page */ | |
717 | tlb_entry_erase(start | _PAGE_HW_SZ | asid); | |
718 | } | |
719 | ||
720 | local_irq_restore(flags); | |
721 | } | |
722 | ||
fe6c1b86 VG |
723 | #endif |
724 | ||
cc562d2e VG |
725 | /* Read the Cache Build Confuration Registers, Decode them and save into |
726 | * the cpuinfo structure for later use. | |
727 | * No Validation is done here, simply read/convert the BCRs | |
728 | */ | |
ce759956 | 729 | void read_decode_mmu_bcr(void) |
cc562d2e | 730 | { |
cc562d2e | 731 | struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu; |
da1677b0 VG |
732 | unsigned int tmp; |
733 | struct bcr_mmu_1_2 { | |
734 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
735 | unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8; | |
736 | #else | |
737 | unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8; | |
738 | #endif | |
739 | } *mmu2; | |
740 | ||
741 | struct bcr_mmu_3 { | |
742 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
d0890ea5 | 743 | unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4, |
da1677b0 VG |
744 | u_itlb:4, u_dtlb:4; |
745 | #else | |
d0890ea5 | 746 | unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4, |
da1677b0 VG |
747 | ways:4, ver:8; |
748 | #endif | |
749 | } *mmu3; | |
cc562d2e | 750 | |
d7a512bf VG |
751 | struct bcr_mmu_4 { |
752 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
753 | unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, | |
754 | n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; | |
755 | #else | |
756 | /* DTLB ITLB JES JE JA */ | |
757 | unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, | |
758 | pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; | |
759 | #endif | |
760 | } *mmu4; | |
761 | ||
cc562d2e VG |
762 | tmp = read_aux_reg(ARC_REG_MMU_BCR); |
763 | mmu->ver = (tmp >> 24); | |
764 | ||
92d44128 VG |
765 | if (is_isa_arcompact()) { |
766 | if (mmu->ver <= 2) { | |
767 | mmu2 = (struct bcr_mmu_1_2 *)&tmp; | |
768 | mmu->pg_sz_k = TO_KB(0x2000); | |
769 | mmu->sets = 1 << mmu2->sets; | |
770 | mmu->ways = 1 << mmu2->ways; | |
771 | mmu->u_dtlb = mmu2->u_dtlb; | |
772 | mmu->u_itlb = mmu2->u_itlb; | |
773 | } else { | |
774 | mmu3 = (struct bcr_mmu_3 *)&tmp; | |
775 | mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1); | |
776 | mmu->sets = 1 << mmu3->sets; | |
777 | mmu->ways = 1 << mmu3->ways; | |
778 | mmu->u_dtlb = mmu3->u_dtlb; | |
779 | mmu->u_itlb = mmu3->u_itlb; | |
780 | mmu->sasid = mmu3->sasid; | |
781 | } | |
d7a512bf VG |
782 | } else { |
783 | mmu4 = (struct bcr_mmu_4 *)&tmp; | |
784 | mmu->pg_sz_k = 1 << (mmu4->sz0 - 1); | |
785 | mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11); | |
786 | mmu->sets = 64 << mmu4->n_entry; | |
787 | mmu->ways = mmu4->n_ways * 2; | |
788 | mmu->u_dtlb = mmu4->u_dtlb * 4; | |
789 | mmu->u_itlb = mmu4->u_itlb * 4; | |
d0890ea5 | 790 | mmu->sasid = mmu4->sasid; |
b5ddb6d5 | 791 | pae_exists = mmu->pae = mmu4->pae; |
cc562d2e | 792 | } |
cc562d2e VG |
793 | } |
794 | ||
af617428 VG |
795 | char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len) |
796 | { | |
797 | int n = 0; | |
e3edeb67 | 798 | struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu; |
d7a512bf VG |
799 | char super_pg[64] = ""; |
800 | ||
801 | if (p_mmu->s_pg_sz_m) | |
d7c46114 | 802 | scnprintf(super_pg, 64, "%dM Super Page %s", |
6ce18798 | 803 | p_mmu->s_pg_sz_m, |
964cf28f | 804 | IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE)); |
af617428 | 805 | |
af617428 | 806 | n += scnprintf(buf + n, len - n, |
d7c46114 | 807 | "MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n", |
d7a512bf | 808 | p_mmu->ver, p_mmu->pg_sz_k, super_pg, |
b598e17f | 809 | p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways, |
5a364c2a | 810 | p_mmu->u_dtlb, p_mmu->u_itlb, |
d7c46114 | 811 | IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40)); |
af617428 VG |
812 | |
813 | return buf; | |
814 | } | |
815 | ||
b5ddb6d5 VG |
816 | int pae40_exist_but_not_enab(void) |
817 | { | |
818 | return pae_exists && !is_pae40_enabled(); | |
819 | } | |
820 | ||
ce759956 | 821 | void arc_mmu_init(void) |
cc562d2e | 822 | { |
af617428 | 823 | struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu; |
92d44128 VG |
824 | char str[256]; |
825 | int compat = 0; | |
af617428 | 826 | |
18ee4bec | 827 | pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str))); |
af617428 | 828 | |
15ca68a9 NC |
829 | /* |
830 | * Can't be done in processor.h due to header include depenedencies | |
831 | */ | |
832 | BUILD_BUG_ON(!IS_ALIGNED((CONFIG_ARC_KVADDR_SIZE << 20), PMD_SIZE)); | |
833 | ||
8bcf2c48 NC |
834 | /* |
835 | * stack top size sanity check, | |
836 | * Can't be done in processor.h due to header include depenedencies | |
837 | */ | |
838 | BUILD_BUG_ON(!IS_ALIGNED(STACK_TOP, PMD_SIZE)); | |
839 | ||
92d44128 VG |
840 | /* |
841 | * Ensure that MMU features assumed by kernel exist in hardware. | |
842 | * For older ARC700 cpus, it has to be exact match, since the MMU | |
843 | * revisions were not backwards compatible (MMUv3 TLB layout changed | |
844 | * so even if kernel for v2 didn't use any new cmds of v3, it would | |
845 | * still not work. | |
846 | * For HS cpus, MMUv4 was baseline and v5 is backwards compatible | |
847 | * (will run older software). | |
af617428 | 848 | */ |
92d44128 VG |
849 | if (is_isa_arcompact() && mmu->ver == CONFIG_ARC_MMU_VER) |
850 | compat = 1; | |
851 | else if (is_isa_arcv2() && mmu->ver >= CONFIG_ARC_MMU_VER) | |
852 | compat = 1; | |
853 | ||
854 | if (!compat) { | |
af617428 VG |
855 | panic("MMU ver %d doesn't match kernel built for %d...\n", |
856 | mmu->ver, CONFIG_ARC_MMU_VER); | |
857 | } | |
858 | ||
40b552d9 | 859 | if (mmu->pg_sz_k != TO_KB(PAGE_SIZE)) |
af617428 VG |
860 | panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE)); |
861 | ||
6ce18798 VG |
862 | if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) && |
863 | mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE)) | |
864 | panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n", | |
865 | (unsigned long)TO_MB(HPAGE_PMD_SIZE)); | |
866 | ||
5a364c2a VG |
867 | if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae) |
868 | panic("Hardware doesn't support PAE40\n"); | |
869 | ||
cc562d2e VG |
870 | /* Enable the MMU */ |
871 | write_aux_reg(ARC_REG_PID, MMU_ENABLE); | |
41195d23 VG |
872 | |
873 | /* In smp we use this reg for interrupt 1 scratch */ | |
874 | #ifndef CONFIG_SMP | |
875 | /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */ | |
876 | write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir); | |
877 | #endif | |
b5ddb6d5 VG |
878 | |
879 | if (pae40_exist_but_not_enab()) | |
880 | write_aux_reg(ARC_REG_TLBPD1HI, 0); | |
cc562d2e VG |
881 | } |
882 | ||
883 | /* | |
884 | * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4} | |
885 | * The mapping is Column-first. | |
886 | * --------------------- ----------- | |
887 | * |way0|way1|way2|way3| |way0|way1| | |
888 | * --------------------- ----------- | |
889 | * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 | | |
890 | * [set1] | 4 | 5 | 6 | 7 | | 2 | 3 | | |
891 | * ~ ~ ~ ~ | |
892 | * [set127] | 508| 509| 510| 511| | 254| 255| | |
893 | * --------------------- ----------- | |
894 | * For normal operations we don't(must not) care how above works since | |
895 | * MMU cmd getIndex(vaddr) abstracts that out. | |
896 | * However for walking WAYS of a SET, we need to know this | |
897 | */ | |
898 | #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way)) | |
899 | ||
900 | /* Handling of Duplicate PD (TLB entry) in MMU. | |
901 | * -Could be due to buggy customer tapeouts or obscure kernel bugs | |
902 | * -MMU complaints not at the time of duplicate PD installation, but at the | |
903 | * time of lookup matching multiple ways. | |
904 | * -Ideally these should never happen - but if they do - workaround by deleting | |
905 | * the duplicate one. | |
906 | * -Knob to be verbose abt it.(TODO: hook them up to debugfs) | |
907 | */ | |
8840e14c | 908 | volatile int dup_pd_silent; /* Be slient abt it or complain (default) */ |
cc562d2e VG |
909 | |
910 | void do_tlb_overlap_fault(unsigned long cause, unsigned long address, | |
911 | struct pt_regs *regs) | |
912 | { | |
cc562d2e | 913 | struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu; |
8840e14c | 914 | unsigned long flags; |
89c92142 VG |
915 | int set, n_ways = mmu->ways; |
916 | ||
917 | n_ways = min(n_ways, 4); | |
918 | BUG_ON(mmu->ways > 4); | |
cc562d2e VG |
919 | |
920 | local_irq_save(flags); | |
921 | ||
cc562d2e VG |
922 | /* loop thru all sets of TLB */ |
923 | for (set = 0; set < mmu->sets; set++) { | |
924 | ||
8840e14c | 925 | int is_valid, way; |
89c92142 | 926 | unsigned int pd0[4]; |
8840e14c | 927 | |
cc562d2e | 928 | /* read out all the ways of current set */ |
89c92142 | 929 | for (way = 0, is_valid = 0; way < n_ways; way++) { |
cc562d2e VG |
930 | write_aux_reg(ARC_REG_TLBINDEX, |
931 | SET_WAY_TO_IDX(mmu, set, way)); | |
932 | write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead); | |
933 | pd0[way] = read_aux_reg(ARC_REG_TLBPD0); | |
cc562d2e | 934 | is_valid |= pd0[way] & _PAGE_PRESENT; |
8840e14c | 935 | pd0[way] &= PAGE_MASK; |
cc562d2e VG |
936 | } |
937 | ||
938 | /* If all the WAYS in SET are empty, skip to next SET */ | |
939 | if (!is_valid) | |
940 | continue; | |
941 | ||
942 | /* Scan the set for duplicate ways: needs a nested loop */ | |
89c92142 | 943 | for (way = 0; way < n_ways - 1; way++) { |
8840e14c VG |
944 | |
945 | int n; | |
946 | ||
cc562d2e VG |
947 | if (!pd0[way]) |
948 | continue; | |
949 | ||
89c92142 | 950 | for (n = way + 1; n < n_ways; n++) { |
8840e14c VG |
951 | if (pd0[way] != pd0[n]) |
952 | continue; | |
953 | ||
954 | if (!dup_pd_silent) | |
955 | pr_info("Dup TLB PD0 %08x @ set %d ways %d,%d\n", | |
956 | pd0[way], set, way, n); | |
957 | ||
958 | /* | |
959 | * clear entry @way and not @n. | |
960 | * This is critical to our optimised loop | |
961 | */ | |
962 | pd0[way] = 0; | |
963 | write_aux_reg(ARC_REG_TLBINDEX, | |
cc562d2e | 964 | SET_WAY_TO_IDX(mmu, set, way)); |
8840e14c | 965 | __tlb_entry_erase(); |
cc562d2e VG |
966 | } |
967 | } | |
968 | } | |
969 | ||
970 | local_irq_restore(flags); | |
971 | } | |
972 | ||
973 | /*********************************************************************** | |
974 | * Diagnostic Routines | |
975 | * -Called from Low Level TLB Hanlders if things don;t look good | |
976 | **********************************************************************/ | |
977 | ||
978 | #ifdef CONFIG_ARC_DBG_TLB_PARANOIA | |
979 | ||
980 | /* | |
981 | * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS | |
982 | * don't match | |
983 | */ | |
5bd87adf | 984 | void print_asid_mismatch(int mm_asid, int mmu_asid, int is_fast_path) |
cc562d2e | 985 | { |
cc562d2e | 986 | pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n", |
5bd87adf | 987 | is_fast_path ? "Fast" : "Slow", mm_asid, mmu_asid); |
cc562d2e VG |
988 | |
989 | __asm__ __volatile__("flag 1"); | |
990 | } | |
991 | ||
5bd87adf | 992 | void tlb_paranoid_check(unsigned int mm_asid, unsigned long addr) |
cc562d2e | 993 | { |
5bd87adf | 994 | unsigned int mmu_asid; |
cc562d2e | 995 | |
5bd87adf | 996 | mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff; |
cc562d2e | 997 | |
5bd87adf VG |
998 | /* |
999 | * At the time of a TLB miss/installation | |
1000 | * - HW version needs to match SW version | |
1001 | * - SW needs to have a valid ASID | |
1002 | */ | |
1003 | if (addr < 0x70000000 && | |
947bf103 VG |
1004 | ((mm_asid == MM_CTXT_NO_ASID) || |
1005 | (mmu_asid != (mm_asid & MM_CTXT_ASID_MASK)))) | |
5bd87adf | 1006 | print_asid_mismatch(mm_asid, mmu_asid, 0); |
cc562d2e VG |
1007 | } |
1008 | #endif |