[mirror_ubuntu-bionic-kernel.git] / arch / arc / plat-axs10x / axs10x.c

/*
 * AXS101/AXS103 Software Development Platform
 *
 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/libfdt.h>

#include <asm/asm-offsets.h>
#include <asm/io.h>
#include <asm/mach_desc.h>
#include <soc/arc/mcip.h>

#define AXS_MB_CGU		0xE0010000
#define AXS_MB_CREG		0xE0011000

#define CREG_MB_IRQ_MUX		(AXS_MB_CREG + 0x214)
#define CREG_MB_SW_RESET	(AXS_MB_CREG + 0x220)
#define CREG_MB_VER		(AXS_MB_CREG + 0x230)
#define CREG_MB_CONFIG		(AXS_MB_CREG + 0x234)

#define AXC001_CREG		0xF0001000
#define AXC001_GPIO_INTC	0xF0003000

static void __init axs10x_enable_gpio_intc_wire(void)
{
	/*
	 * Peripherals on CPU Card and Mother Board are wired to cpu intc via
	 * intermediate DW APB GPIO blocks (mainly for debouncing)
	 *
	 *         ---------------------
	 *        |  snps,arc700-intc |
	 *        ---------------------
	 *          | #7          | #15
	 * -------------------   -------------------
	 * | snps,dw-apb-gpio |  | snps,dw-apb-gpio |
	 * -------------------   -------------------
	 *        | #12                     |
	 *        |                 [ Debug UART on cpu card ]
	 *        |
	 * ------------------------
	 * | snps,dw-apb-intc (MB)|
	 * ------------------------
	 *  |      |       |      |
	 * [eth] [uart]        [... other perip on Main Board]
	 *
	 * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
	 * with stacked INTCs. In particular problem happens if its master INTC
	 * not yet instantiated. See discussion here -
	 * https://lkml.org/lkml/2015/3/4/755
	 *
	 * So setup the first gpio block as a passive pass thru and hide it from
	 * DT hardware topology - connect MB intc directly to cpu intc
	 * The GPIO "wire" needs to be init nevertheless (here)
	 *
	 * One side adv is that peripheral interrupt handling avoids one nested
	 * intc ISR hop
	 */
#define GPIO_INTEN		(AXC001_GPIO_INTC + 0x30)
#define GPIO_INTMASK		(AXC001_GPIO_INTC + 0x34)
#define GPIO_INTTYPE_LEVEL	(AXC001_GPIO_INTC + 0x38)
#define GPIO_INT_POLARITY	(AXC001_GPIO_INTC + 0x3c)
#define MB_TO_GPIO_IRQ		12

	iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
	iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
	iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
	iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
}

static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
{
	union ver {
		struct {
#ifdef CONFIG_CPU_BIG_ENDIAN
			unsigned int pad:11, y:12, m:4, d:5;
#else
			unsigned int d:5, m:4, y:12, pad:11;
#endif
		};
		unsigned int val;
	} board;

	board.val = ioread32((void __iomem *)creg);
	pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
		board.y);
}

static void __init axs10x_early_init(void)
{
	int mb_rev;
	char mb[32];

	/* Determine motherboard version */
	if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
		mb_rev = 3;	/* HT-3 (rev3.0) */
	else
		mb_rev = 2;	/* HT-2 (rev2.0) */

	axs10x_enable_gpio_intc_wire();

	scnprintf(mb, 32, "MainBoard v%d", mb_rev);
	axs10x_print_board_ver(CREG_MB_VER, mb);
}

#ifdef CONFIG_AXS101

#define CREG_CPU_ADDR_770	(AXC001_CREG + 0x20)
#define CREG_CPU_ADDR_TUNN	(AXC001_CREG + 0x60)
#define CREG_CPU_ADDR_770_UPD	(AXC001_CREG + 0x34)
#define CREG_CPU_ADDR_TUNN_UPD	(AXC001_CREG + 0x74)

#define CREG_CPU_ARC770_IRQ_MUX	(AXC001_CREG + 0x114)
#define CREG_CPU_GPIO_UART_MUX	(AXC001_CREG + 0x120)

/*
 * Set up System Memory Map for ARC cpu / peripherals controllers
 *
 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
 * of which maps to a corresponding 256MB aperture in Target slave memory map.
 *
 * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
 * (0x0000_0000) of DDR Port 0 (slave #1)
 *
 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
 * which has master/slaves on both ends.
 * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
 * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
 * MB AXI Tunnel Master, which also has a mem map setup
 *
 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
 * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
 */
struct aperture {
	unsigned int slave_sel:4, slave_off:4, pad:24;
};

/* CPU Card target slaves */
#define AXC001_SLV_NONE			0
#define AXC001_SLV_DDR_PORT0		1
#define AXC001_SLV_SRAM			2
#define AXC001_SLV_AXI_TUNNEL		3
#define AXC001_SLV_AXI2APB		6
#define AXC001_SLV_DDR_PORT1		7

/* MB AXI Target slaves */
#define AXS_MB_SLV_NONE			0
#define AXS_MB_SLV_AXI_TUNNEL_CPU	1
#define AXS_MB_SLV_AXI_TUNNEL_HAPS	2
#define AXS_MB_SLV_SRAM			3
#define AXS_MB_SLV_CONTROL		4

/* MB AXI masters */
#define AXS_MB_MST_TUNNEL_CPU		0
#define AXS_MB_MST_USB_OHCI		10

/*
 * memmap for ARC core on CPU Card
 */
static const struct aperture axc001_memmap[16] = {
	{AXC001_SLV_AXI_TUNNEL,		0x0},
	{AXC001_SLV_AXI_TUNNEL,		0x1},
	{AXC001_SLV_SRAM,		0x0}, /* 0x2000_0000: Local SRAM */
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_DDR_PORT0,		0x0}, /* 0x8000_0000: DDR   0..256M */
	{AXC001_SLV_DDR_PORT0,		0x1}, /* 0x9000_0000: DDR 256..512M */
	{AXC001_SLV_DDR_PORT0,		0x2},
	{AXC001_SLV_DDR_PORT0,		0x3},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_AXI_TUNNEL,		0xD},
	{AXC001_SLV_AXI_TUNNEL,		0xE}, /* MB: CREG, CGU... */
	{AXC001_SLV_AXI2APB,		0x0}, /* CPU Card local CREG, CGU... */
};

/*
 * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
 * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
 */
static const struct aperture axc001_axi_tunnel_memmap[16] = {
	{AXC001_SLV_AXI_TUNNEL,		0x0},
	{AXC001_SLV_AXI_TUNNEL,		0x1},
	{AXC001_SLV_SRAM,		0x0},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_DDR_PORT1,		0x0},
	{AXC001_SLV_DDR_PORT1,		0x1},
	{AXC001_SLV_DDR_PORT1,		0x2},
	{AXC001_SLV_DDR_PORT1,		0x3},
	{AXC001_SLV_NONE,		0x0},
	{AXC001_SLV_AXI_TUNNEL,		0xD},
	{AXC001_SLV_AXI_TUNNEL,		0xE},
	{AXC001_SLV_AXI2APB,		0x0},
};

/*
 * memmap for MB AXI Masters
 * Same mem map for all perip controllers as well as MB AXI Tunnel Master
 */
static const struct aperture axs_mb_memmap[16] = {
	{AXS_MB_SLV_SRAM,		0x0},
	{AXS_MB_SLV_SRAM,		0x0},
	{AXS_MB_SLV_NONE,		0x0},
	{AXS_MB_SLV_NONE,		0x0},
	{AXS_MB_SLV_NONE,		0x0},
	{AXS_MB_SLV_NONE,		0x0},
	{AXS_MB_SLV_NONE,		0x0},
	{AXS_MB_SLV_NONE,		0x0},
	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0x8},	/* DDR on CPU Card */
	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0x9},	/* DDR on CPU Card */
	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0xA},
	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0xB},
	{AXS_MB_SLV_NONE,		0x0},
	{AXS_MB_SLV_AXI_TUNNEL_HAPS,	0xD},
	{AXS_MB_SLV_CONTROL,		0x0},	/* MB Local CREG, CGU... */
	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0xF},
};

static noinline void __init
axs101_set_memmap(void __iomem *base, const struct aperture map[16])
{
	unsigned int slave_select, slave_offset;
	int i;

	slave_select = slave_offset = 0;
	for (i = 0; i < 8; i++) {
		slave_select |= map[i].slave_sel << (i << 2);
		slave_offset |= map[i].slave_off << (i << 2);
	}

	iowrite32(slave_select, base + 0x0);	/* SLV0 */
	iowrite32(slave_offset, base + 0x8);	/* OFFSET0 */

	slave_select = slave_offset = 0;
	for (i = 0; i < 8; i++) {
		slave_select |= map[i+8].slave_sel << (i << 2);
		slave_offset |= map[i+8].slave_off << (i << 2);
	}

	iowrite32(slave_select, base + 0x4);	/* SLV1 */
	iowrite32(slave_offset, base + 0xC);	/* OFFSET1 */
}

static void __init axs101_early_init(void)
{
	int i;

	/* ARC 770D memory view */
	axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);

	/* AXI tunnel memory map (incoming traffic from MB into CPU Card */
	axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
			      axc001_axi_tunnel_memmap);
	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);

	/* MB peripherals memory map */
	for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
		axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
				      axs_mb_memmap);

	iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */

	/* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);

	/* Set up the MB interrupt system: mux interrupts to GPIO7) */
	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);

	/* reset ethernet and ULPI interfaces */
	iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);

	/* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
	iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);

	axs10x_early_init();
}

#endif	/* CONFIG_AXS101 */

#ifdef CONFIG_AXS103

#define AXC003_CREG	0xF0001000
#define AXC003_MST_AXI_TUNNEL	0
#define AXC003_MST_HS38		1

#define CREG_CPU_AXI_M0_IRQ_MUX	(AXC003_CREG + 0x440)
#define CREG_CPU_GPIO_UART_MUX	(AXC003_CREG + 0x480)
#define CREG_CPU_TUN_IO_CTRL	(AXC003_CREG + 0x494)


static void __init axs103_early_init(void)
{
#ifdef CONFIG_ARC_MCIP
	/*
	 * AXS103 configurations for SMP/QUAD configurations share device tree
	 * which defaults to 100 MHz. However recent failures of Quad config
	 * revealed P&R timing violations so clamp it down to safe 50 MHz
	 * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
	 * of fudging the freq in DT
	 */
	unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
	if (num_cores > 2) {
		u32 freq = 50, orig;
		/*
		 * TODO: use cpu node "cpu-freq" param instead of platform-specific
		 * "/cpu_card/core_clk" as it works only if we use fixed-clock for cpu.
		 */
		int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
		const struct fdt_property *prop;

		prop = fdt_get_property(initial_boot_params, off,
					"clock-frequency", NULL);
		orig = be32_to_cpu(*(u32*)(prop->data)) / 1000000;

		/* Patching .dtb in-place with new core clock value */
		if (freq != orig ) {
			freq = cpu_to_be32(freq * 1000000);
			fdt_setprop_inplace(initial_boot_params, off,
					    "clock-frequency", &freq, sizeof(freq));
		}
	}
#endif

	/* Memory maps already config in pre-bootloader */

	/* set GPIO mux to UART */
	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);

	iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
		  (void __iomem *) CREG_CPU_TUN_IO_CTRL);

	/* Set up the AXS_MB interrupt system.*/
	iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
					 + (AXC003_MST_HS38 << 2)));

	/* connect ICTL - Main Board with GPIO line */
	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);

	axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");

	axs10x_early_init();
}
#endif

#ifdef CONFIG_AXS101

static const char *axs101_compat[] __initconst = {
	"snps,axs101",
	NULL,
};

MACHINE_START(AXS101, "axs101")
	.dt_compat	= axs101_compat,
	.init_early	= axs101_early_init,
MACHINE_END

#endif	/* CONFIG_AXS101 */

#ifdef CONFIG_AXS103

static const char *axs103_compat[] __initconst = {
	"snps,axs103",
	NULL,
};

MACHINE_START(AXS103, "axs103")
	.dt_compat	= axs103_compat,
	.init_early	= axs103_early_init,
MACHINE_END

/*
 * For the VDK OS-kit, to get the offset to pid and command fields
 */
char coware_swa_pid_offset[TASK_PID];
char coware_swa_comm_offset[TASK_COMM];

#endif	/* CONFIG_AXS103 */
Commit	Line	Data
556cc1c5	1	/*
5fa2daaa	2	* AXS101/AXS103 Software Development Platform
556cc1c5 AB	3	*
	4	* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
b3d6aba8	17	#include <linux/of_fdt.h>
556cc1c5	18	#include <linux/of_platform.h>
b3d6aba8	19	#include <linux/libfdt.h>
2924cd18 RD	20
2924cd18 RD	21	#include <asm/asm-offsets.h>
556cc1c5	22	#include <asm/io.h>
5fa2daaa	23	#include <asm/mach_desc.h>
2d7f5c48	24	#include <soc/arc/mcip.h>
556cc1c5 AB	25
	26	#define AXS_MB_CGU 0xE0010000
	27	#define AXS_MB_CREG 0xE0011000
	28
	29	#define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214)
	30	#define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220)
	31	#define CREG_MB_VER (AXS_MB_CREG + 0x230)
	32	#define CREG_MB_CONFIG (AXS_MB_CREG + 0x234)
	33
	34	#define AXC001_CREG 0xF0001000
	35	#define AXC001_GPIO_INTC 0xF0003000
	36
db7e9855	37	static void __init axs10x_enable_gpio_intc_wire(void)
556cc1c5 AB	38	{
	39	/*
	40	* Peripherals on CPU Card and Mother Board are wired to cpu intc via
	41	* intermediate DW APB GPIO blocks (mainly for debouncing)
	42	*
	43	* ---------------------
	44	* \| snps,arc700-intc \|
	45	* ---------------------
	46	* \| #7 \| #15
	47	* ------------------- -------------------
	48	* \| snps,dw-apb-gpio \| \| snps,dw-apb-gpio \|
	49	* ------------------- -------------------
09074950	50	* \| #12 \|
556cc1c5 AB	51	* \| [ Debug UART on cpu card ]
	52	* \|
	53	* ------------------------
	54	* \| snps,dw-apb-intc (MB)\|
	55	* ------------------------
	56	* \| \| \| \|
	57	* [eth] [uart] [... other perip on Main Board]
	58	*
	59	* Current implementation of "irq-dw-apb-ictl" driver doesn't work well
	60	* with stacked INTCs. In particular problem happens if its master INTC
	61	* not yet instantiated. See discussion here -
	62	* https://lkml.org/lkml/2015/3/4/755
	63	*
	64	* So setup the first gpio block as a passive pass thru and hide it from
	65	* DT hardware topology - connect MB intc directly to cpu intc
	66	* The GPIO "wire" needs to be init nevertheless (here)
	67	*
	68	* One side adv is that peripheral interrupt handling avoids one nested
	69	* intc ISR hop
	70	*/
	71	#define GPIO_INTEN (AXC001_GPIO_INTC + 0x30)
	72	#define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34)
	73	#define GPIO_INTTYPE_LEVEL (AXC001_GPIO_INTC + 0x38)
	74	#define GPIO_INT_POLARITY (AXC001_GPIO_INTC + 0x3c)
	75	#define MB_TO_GPIO_IRQ 12
	76
	77	iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
	78	iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
	79	iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
	80	iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
	81	}
	82
db7e9855	83	static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
556cc1c5 AB	84	{
	85	union ver {
	86	struct {
	87	#ifdef CONFIG_CPU_BIG_ENDIAN
	88	unsigned int pad:11, y:12, m:4, d:5;
	89	#else
	90	unsigned int d:5, m:4, y:12, pad:11;
	91	#endif
	92	};
	93	unsigned int val;
	94	} board;
	95
	96	board.val = ioread32((void __iomem *)creg);
	97	pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
	98	board.y);
	99	}
	100
db7e9855	101	static void __init axs10x_early_init(void)
556cc1c5 AB	102	{
	103	int mb_rev;
	104	char mb[32];
	105
	106	/* Determine motherboard version */
	107	if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
	108	mb_rev = 3; /* HT-3 (rev3.0) */
	109	else
	110	mb_rev = 2; /* HT-2 (rev2.0) */
	111
db7e9855	112	axs10x_enable_gpio_intc_wire();
556cc1c5 AB	113
	114	scnprintf(mb, 32, "MainBoard v%d", mb_rev);
	115	axs10x_print_board_ver(CREG_MB_VER, mb);
	116	}
	117
5fa2daaa VG	118	#ifdef CONFIG_AXS101
	119
	120	#define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20)
	121	#define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60)
	122	#define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34)
	123	#define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74)
	124
	125	#define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
	126	#define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120)
	127
556cc1c5 AB	128	/*
	129	* Set up System Memory Map for ARC cpu / peripherals controllers
	130	*
	131	* Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
	132	* of which maps to a corresponding 256MB aperture in Target slave memory map.
	133	*
	134	* e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
	135	* (0x0000_0000) of DDR Port 0 (slave #1)
	136	*
	137	* Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
	138	* which has master/slaves on both ends.
	139	* e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
	140	* (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
	141	* MB AXI Tunnel Master, which also has a mem map setup
	142	*
	143	* In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
	144	* to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
	145	*/
	146	struct aperture {
	147	unsigned int slave_sel:4, slave_off:4, pad:24;
	148	};
	149
	150	/* CPU Card target slaves */
	151	#define AXC001_SLV_NONE 0
	152	#define AXC001_SLV_DDR_PORT0 1
	153	#define AXC001_SLV_SRAM 2
	154	#define AXC001_SLV_AXI_TUNNEL 3
	155	#define AXC001_SLV_AXI2APB 6
	156	#define AXC001_SLV_DDR_PORT1 7
	157
	158	/* MB AXI Target slaves */
	159	#define AXS_MB_SLV_NONE 0
	160	#define AXS_MB_SLV_AXI_TUNNEL_CPU 1
	161	#define AXS_MB_SLV_AXI_TUNNEL_HAPS 2
	162	#define AXS_MB_SLV_SRAM 3
	163	#define AXS_MB_SLV_CONTROL 4
	164
	165	/* MB AXI masters */
	166	#define AXS_MB_MST_TUNNEL_CPU 0
	167	#define AXS_MB_MST_USB_OHCI 10
	168
	169	/*
	170	* memmap for ARC core on CPU Card
	171	*/
	172	static const struct aperture axc001_memmap[16] = {
	173	{AXC001_SLV_AXI_TUNNEL, 0x0},
	174	{AXC001_SLV_AXI_TUNNEL, 0x1},
	175	{AXC001_SLV_SRAM, 0x0}, /* 0x2000_0000: Local SRAM */
	176	{AXC001_SLV_NONE, 0x0},
	177	{AXC001_SLV_NONE, 0x0},
	178	{AXC001_SLV_NONE, 0x0},
	179	{AXC001_SLV_NONE, 0x0},
	180	{AXC001_SLV_NONE, 0x0},
	181	{AXC001_SLV_DDR_PORT0, 0x0}, /* 0x8000_0000: DDR 0..256M */
	182	{AXC001_SLV_DDR_PORT0, 0x1}, /* 0x9000_0000: DDR 256..512M */
749aa0e1 VG	183	{AXC001_SLV_DDR_PORT0, 0x2},
749aa0e1 VG	184	{AXC001_SLV_DDR_PORT0, 0x3},
556cc1c5 AB	185	{AXC001_SLV_NONE, 0x0},
	186	{AXC001_SLV_AXI_TUNNEL, 0xD},
	187	{AXC001_SLV_AXI_TUNNEL, 0xE}, /* MB: CREG, CGU... */
	188	{AXC001_SLV_AXI2APB, 0x0}, /* CPU Card local CREG, CGU... */
	189	};
	190
	191	/*
	192	* memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
	193	* GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
	194	*/
	195	static const struct aperture axc001_axi_tunnel_memmap[16] = {
	196	{AXC001_SLV_AXI_TUNNEL, 0x0},
	197	{AXC001_SLV_AXI_TUNNEL, 0x1},
	198	{AXC001_SLV_SRAM, 0x0},
	199	{AXC001_SLV_NONE, 0x0},
	200	{AXC001_SLV_NONE, 0x0},
	201	{AXC001_SLV_NONE, 0x0},
	202	{AXC001_SLV_NONE, 0x0},
	203	{AXC001_SLV_NONE, 0x0},
556cc1c5 AB	204	{AXC001_SLV_DDR_PORT1, 0x0},
556cc1c5 AB	205	{AXC001_SLV_DDR_PORT1, 0x1},
749aa0e1 VG	206	{AXC001_SLV_DDR_PORT1, 0x2},
749aa0e1 VG	207	{AXC001_SLV_DDR_PORT1, 0x3},
556cc1c5 AB	208	{AXC001_SLV_NONE, 0x0},
	209	{AXC001_SLV_AXI_TUNNEL, 0xD},
	210	{AXC001_SLV_AXI_TUNNEL, 0xE},
	211	{AXC001_SLV_AXI2APB, 0x0},
	212	};
	213
	214	/*
	215	* memmap for MB AXI Masters
	216	* Same mem map for all perip controllers as well as MB AXI Tunnel Master
	217	*/
	218	static const struct aperture axs_mb_memmap[16] = {
	219	{AXS_MB_SLV_SRAM, 0x0},
	220	{AXS_MB_SLV_SRAM, 0x0},
	221	{AXS_MB_SLV_NONE, 0x0},
	222	{AXS_MB_SLV_NONE, 0x0},
	223	{AXS_MB_SLV_NONE, 0x0},
	224	{AXS_MB_SLV_NONE, 0x0},
	225	{AXS_MB_SLV_NONE, 0x0},
	226	{AXS_MB_SLV_NONE, 0x0},
	227	{AXS_MB_SLV_AXI_TUNNEL_CPU, 0x8}, /* DDR on CPU Card */
	228	{AXS_MB_SLV_AXI_TUNNEL_CPU, 0x9}, /* DDR on CPU Card */
	229	{AXS_MB_SLV_AXI_TUNNEL_CPU, 0xA},
	230	{AXS_MB_SLV_AXI_TUNNEL_CPU, 0xB},
	231	{AXS_MB_SLV_NONE, 0x0},
	232	{AXS_MB_SLV_AXI_TUNNEL_HAPS, 0xD},
	233	{AXS_MB_SLV_CONTROL, 0x0}, /* MB Local CREG, CGU... */
	234	{AXS_MB_SLV_AXI_TUNNEL_CPU, 0xF},
	235	};
	236
db7e9855	237	static noinline void __init
556cc1c5 AB	238	axs101_set_memmap(void __iomem *base, const struct aperture map[16])
	239	{
	240	unsigned int slave_select, slave_offset;
	241	int i;
	242
	243	slave_select = slave_offset = 0;
	244	for (i = 0; i < 8; i++) {
	245	slave_select \|= map[i].slave_sel << (i << 2);
	246	slave_offset \|= map[i].slave_off << (i << 2);
	247	}
	248
	249	iowrite32(slave_select, base + 0x0); /* SLV0 */
	250	iowrite32(slave_offset, base + 0x8); /* OFFSET0 */
	251
	252	slave_select = slave_offset = 0;
	253	for (i = 0; i < 8; i++) {
	254	slave_select \|= map[i+8].slave_sel << (i << 2);
	255	slave_offset \|= map[i+8].slave_off << (i << 2);
	256	}
	257
	258	iowrite32(slave_select, base + 0x4); /* SLV1 */
	259	iowrite32(slave_offset, base + 0xC); /* OFFSET1 */
	260	}
	261
db7e9855	262	static void __init axs101_early_init(void)
556cc1c5 AB	263	{
	264	int i;
	265
	266	/* ARC 770D memory view */
	267	axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
	268	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);
	269
	270	/* AXI tunnel memory map (incoming traffic from MB into CPU Card */
	271	axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
	272	axc001_axi_tunnel_memmap);
	273	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);
	274
	275	/* MB peripherals memory map */
	276	for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
	277	axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
	278	axs_mb_memmap);
	279
	280	iowrite32(0x3ff, (void __iomem ) AXS_MB_CREG + 0x100); / Update */
	281
	282	/* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
	283	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
	284
	285	/* Set up the MB interrupt system: mux interrupts to GPIO7) */
	286	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
	287
	288	/* reset ethernet and ULPI interfaces */
	289	iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);
	290
	291	/* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
	292	iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);
	293
	294	axs10x_early_init();
	295	}
	296
5fa2daaa VG	297	#endif /* CONFIG_AXS101 */
	298
	299	#ifdef CONFIG_AXS103
	300
5fa2daaa VG	301	#define AXC003_CREG 0xF0001000
	302	#define AXC003_MST_AXI_TUNNEL 0
	303	#define AXC003_MST_HS38 1
	304
	305	#define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440)
	306	#define CREG_CPU_GPIO_UART_MUX (AXC003_CREG + 0x480)
	307	#define CREG_CPU_TUN_IO_CTRL (AXC003_CREG + 0x494)
	308
	309
5fa2daaa VG	310	static void __init axs103_early_init(void)
5fa2daaa VG	311	{
0fa400cb	312	#ifdef CONFIG_ARC_MCIP
6de7abfb VG	313	/*
6de7abfb VG	314	* AXS103 configurations for SMP/QUAD configurations share device tree
9926c29f	315	* which defaults to 100 MHz. However recent failures of Quad config
6de7abfb VG	316	* revealed P&R timing violations so clamp it down to safe 50 MHz
6de7abfb VG	317	* Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
0fa400cb	318	* of fudging the freq in DT
6de7abfb	319	*/
6de7abfb	320	unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
0fa400cb VG	321	if (num_cores > 2) {
	322	u32 freq = 50, orig;
	323	/*
	324	* TODO: use cpu node "cpu-freq" param instead of platform-specific
	325	* "/cpu_card/core_clk" as it works only if we use fixed-clock for cpu.
	326	*/
	327	int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
	328	const struct fdt_property *prop;
	329
	330	prop = fdt_get_property(initial_boot_params, off,
	331	"clock-frequency", NULL);
	332	orig = be32_to_cpu((u32)(prop->data)) / 1000000;
	333
	334	/* Patching .dtb in-place with new core clock value */
	335	if (freq != orig ) {
	336	freq = cpu_to_be32(freq * 1000000);
	337	fdt_setprop_inplace(initial_boot_params, off,
	338	"clock-frequency", &freq, sizeof(freq));
	339	}
0eeb3dfe	340	}
0fa400cb	341	#endif
5fa2daaa VG	342
	343	/* Memory maps already config in pre-bootloader */
	344
	345	/* set GPIO mux to UART */
	346	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
	347
	348	iowrite32((0x00100000U \| 0x000C0000U \| 0x00003322U),
	349	(void __iomem *) CREG_CPU_TUN_IO_CTRL);
	350
	351	/* Set up the AXS_MB interrupt system.*/
	352	iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
	353	+ (AXC003_MST_HS38 << 2)));
	354
	355	/* connect ICTL - Main Board with GPIO line */
	356	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
	357
	358	axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");
	359
	360	axs10x_early_init();
5fa2daaa VG	361	}
	362	#endif
	363
	364	#ifdef CONFIG_AXS101
	365
556cc1c5 AB	366	static const char *axs101_compat[] __initconst = {
	367	"snps,axs101",
	368	NULL,
	369	};
	370
	371	MACHINE_START(AXS101, "axs101")
	372	.dt_compat = axs101_compat,
	373	.init_early = axs101_early_init,
	374	MACHINE_END
5fa2daaa VG	375
	376	#endif /* CONFIG_AXS101 */
	377
	378	#ifdef CONFIG_AXS103
	379
	380	static const char *axs103_compat[] __initconst = {
	381	"snps,axs103",
	382	NULL,
	383	};
	384
	385	MACHINE_START(AXS103, "axs103")
	386	.dt_compat = axs103_compat,
	387	.init_early = axs103_early_init,
5fa2daaa VG	388	MACHINE_END
5fa2daaa VG	389
2924cd18 RD	390	/*
	391	* For the VDK OS-kit, to get the offset to pid and command fields
	392	*/
	393	char coware_swa_pid_offset[TASK_PID];
	394	char coware_swa_comm_offset[TASK_COMM];
	395
5fa2daaa	396	#endif /* CONFIG_AXS103 */