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1 | /* |
2 | * AXS101 Software Development Platform | |
3 | * | |
4 | * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/of_platform.h> | |
18 | #include <asm/mach_desc.h> | |
19 | #include <asm/io.h> | |
20 | ||
21 | #define AXS_MB_CGU 0xE0010000 | |
22 | #define AXS_MB_CREG 0xE0011000 | |
23 | ||
24 | #define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214) | |
25 | #define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220) | |
26 | #define CREG_MB_VER (AXS_MB_CREG + 0x230) | |
27 | #define CREG_MB_CONFIG (AXS_MB_CREG + 0x234) | |
28 | ||
29 | #define AXC001_CREG 0xF0001000 | |
30 | #define AXC001_GPIO_INTC 0xF0003000 | |
31 | ||
32 | #define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20) | |
33 | #define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60) | |
34 | #define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34) | |
35 | #define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74) | |
36 | ||
37 | #define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114) | |
38 | #define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120) | |
39 | ||
40 | static void enable_gpio_intc_wire(void) | |
41 | { | |
42 | /* | |
43 | * Peripherals on CPU Card and Mother Board are wired to cpu intc via | |
44 | * intermediate DW APB GPIO blocks (mainly for debouncing) | |
45 | * | |
46 | * --------------------- | |
47 | * | snps,arc700-intc | | |
48 | * --------------------- | |
49 | * | #7 | #15 | |
50 | * ------------------- ------------------- | |
51 | * | snps,dw-apb-gpio | | snps,dw-apb-gpio | | |
52 | * ------------------- ------------------- | |
53 | * | | | |
54 | * | [ Debug UART on cpu card ] | |
55 | * | | |
56 | * ------------------------ | |
57 | * | snps,dw-apb-intc (MB)| | |
58 | * ------------------------ | |
59 | * | | | | | |
60 | * [eth] [uart] [... other perip on Main Board] | |
61 | * | |
62 | * Current implementation of "irq-dw-apb-ictl" driver doesn't work well | |
63 | * with stacked INTCs. In particular problem happens if its master INTC | |
64 | * not yet instantiated. See discussion here - | |
65 | * https://lkml.org/lkml/2015/3/4/755 | |
66 | * | |
67 | * So setup the first gpio block as a passive pass thru and hide it from | |
68 | * DT hardware topology - connect MB intc directly to cpu intc | |
69 | * The GPIO "wire" needs to be init nevertheless (here) | |
70 | * | |
71 | * One side adv is that peripheral interrupt handling avoids one nested | |
72 | * intc ISR hop | |
73 | */ | |
74 | #define GPIO_INTEN (AXC001_GPIO_INTC + 0x30) | |
75 | #define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34) | |
76 | #define GPIO_INTTYPE_LEVEL (AXC001_GPIO_INTC + 0x38) | |
77 | #define GPIO_INT_POLARITY (AXC001_GPIO_INTC + 0x3c) | |
78 | #define MB_TO_GPIO_IRQ 12 | |
79 | ||
80 | iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK); | |
81 | iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL); | |
82 | iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY); | |
83 | iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN); | |
84 | } | |
85 | ||
86 | static void axs10x_print_board_ver(unsigned int creg, const char *str) | |
87 | { | |
88 | union ver { | |
89 | struct { | |
90 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
91 | unsigned int pad:11, y:12, m:4, d:5; | |
92 | #else | |
93 | unsigned int d:5, m:4, y:12, pad:11; | |
94 | #endif | |
95 | }; | |
96 | unsigned int val; | |
97 | } board; | |
98 | ||
99 | board.val = ioread32((void __iomem *)creg); | |
100 | pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m, | |
101 | board.y); | |
102 | } | |
103 | ||
104 | static void axs10x_early_init(void) | |
105 | { | |
106 | int mb_rev; | |
107 | char mb[32]; | |
108 | ||
109 | /* Determine motherboard version */ | |
110 | if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28)) | |
111 | mb_rev = 3; /* HT-3 (rev3.0) */ | |
112 | else | |
113 | mb_rev = 2; /* HT-2 (rev2.0) */ | |
114 | ||
115 | enable_gpio_intc_wire(); | |
116 | ||
117 | scnprintf(mb, 32, "MainBoard v%d", mb_rev); | |
118 | axs10x_print_board_ver(CREG_MB_VER, mb); | |
119 | } | |
120 | ||
121 | /* | |
122 | * Set up System Memory Map for ARC cpu / peripherals controllers | |
123 | * | |
124 | * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each | |
125 | * of which maps to a corresponding 256MB aperture in Target slave memory map. | |
126 | * | |
127 | * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0 | |
128 | * (0x0000_0000) of DDR Port 0 (slave #1) | |
129 | * | |
130 | * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel: | |
131 | * which has master/slaves on both ends. | |
132 | * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14 | |
133 | * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to | |
134 | * MB AXI Tunnel Master, which also has a mem map setup | |
135 | * | |
136 | * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup | |
137 | * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master | |
138 | */ | |
139 | struct aperture { | |
140 | unsigned int slave_sel:4, slave_off:4, pad:24; | |
141 | }; | |
142 | ||
143 | /* CPU Card target slaves */ | |
144 | #define AXC001_SLV_NONE 0 | |
145 | #define AXC001_SLV_DDR_PORT0 1 | |
146 | #define AXC001_SLV_SRAM 2 | |
147 | #define AXC001_SLV_AXI_TUNNEL 3 | |
148 | #define AXC001_SLV_AXI2APB 6 | |
149 | #define AXC001_SLV_DDR_PORT1 7 | |
150 | ||
151 | /* MB AXI Target slaves */ | |
152 | #define AXS_MB_SLV_NONE 0 | |
153 | #define AXS_MB_SLV_AXI_TUNNEL_CPU 1 | |
154 | #define AXS_MB_SLV_AXI_TUNNEL_HAPS 2 | |
155 | #define AXS_MB_SLV_SRAM 3 | |
156 | #define AXS_MB_SLV_CONTROL 4 | |
157 | ||
158 | /* MB AXI masters */ | |
159 | #define AXS_MB_MST_TUNNEL_CPU 0 | |
160 | #define AXS_MB_MST_USB_OHCI 10 | |
161 | ||
162 | /* | |
163 | * memmap for ARC core on CPU Card | |
164 | */ | |
165 | static const struct aperture axc001_memmap[16] = { | |
166 | {AXC001_SLV_AXI_TUNNEL, 0x0}, | |
167 | {AXC001_SLV_AXI_TUNNEL, 0x1}, | |
168 | {AXC001_SLV_SRAM, 0x0}, /* 0x2000_0000: Local SRAM */ | |
169 | {AXC001_SLV_NONE, 0x0}, | |
170 | {AXC001_SLV_NONE, 0x0}, | |
171 | {AXC001_SLV_NONE, 0x0}, | |
172 | {AXC001_SLV_NONE, 0x0}, | |
173 | {AXC001_SLV_NONE, 0x0}, | |
174 | {AXC001_SLV_DDR_PORT0, 0x0}, /* 0x8000_0000: DDR 0..256M */ | |
175 | {AXC001_SLV_DDR_PORT0, 0x1}, /* 0x9000_0000: DDR 256..512M */ | |
176 | {AXC001_SLV_DDR_PORT1, 0x0}, | |
177 | {AXC001_SLV_DDR_PORT1, 0x1}, | |
178 | {AXC001_SLV_NONE, 0x0}, | |
179 | {AXC001_SLV_AXI_TUNNEL, 0xD}, | |
180 | {AXC001_SLV_AXI_TUNNEL, 0xE}, /* MB: CREG, CGU... */ | |
181 | {AXC001_SLV_AXI2APB, 0x0}, /* CPU Card local CREG, CGU... */ | |
182 | }; | |
183 | ||
184 | /* | |
185 | * memmap for CPU Card AXI Tunnel Master (for access by MB controllers) | |
186 | * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR | |
187 | */ | |
188 | static const struct aperture axc001_axi_tunnel_memmap[16] = { | |
189 | {AXC001_SLV_AXI_TUNNEL, 0x0}, | |
190 | {AXC001_SLV_AXI_TUNNEL, 0x1}, | |
191 | {AXC001_SLV_SRAM, 0x0}, | |
192 | {AXC001_SLV_NONE, 0x0}, | |
193 | {AXC001_SLV_NONE, 0x0}, | |
194 | {AXC001_SLV_NONE, 0x0}, | |
195 | {AXC001_SLV_NONE, 0x0}, | |
196 | {AXC001_SLV_NONE, 0x0}, | |
197 | {AXC001_SLV_DDR_PORT0, 0x0}, | |
198 | {AXC001_SLV_DDR_PORT0, 0x1}, | |
199 | {AXC001_SLV_DDR_PORT1, 0x0}, | |
200 | {AXC001_SLV_DDR_PORT1, 0x1}, | |
201 | {AXC001_SLV_NONE, 0x0}, | |
202 | {AXC001_SLV_AXI_TUNNEL, 0xD}, | |
203 | {AXC001_SLV_AXI_TUNNEL, 0xE}, | |
204 | {AXC001_SLV_AXI2APB, 0x0}, | |
205 | }; | |
206 | ||
207 | /* | |
208 | * memmap for MB AXI Masters | |
209 | * Same mem map for all perip controllers as well as MB AXI Tunnel Master | |
210 | */ | |
211 | static const struct aperture axs_mb_memmap[16] = { | |
212 | {AXS_MB_SLV_SRAM, 0x0}, | |
213 | {AXS_MB_SLV_SRAM, 0x0}, | |
214 | {AXS_MB_SLV_NONE, 0x0}, | |
215 | {AXS_MB_SLV_NONE, 0x0}, | |
216 | {AXS_MB_SLV_NONE, 0x0}, | |
217 | {AXS_MB_SLV_NONE, 0x0}, | |
218 | {AXS_MB_SLV_NONE, 0x0}, | |
219 | {AXS_MB_SLV_NONE, 0x0}, | |
220 | {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x8}, /* DDR on CPU Card */ | |
221 | {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x9}, /* DDR on CPU Card */ | |
222 | {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xA}, | |
223 | {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xB}, | |
224 | {AXS_MB_SLV_NONE, 0x0}, | |
225 | {AXS_MB_SLV_AXI_TUNNEL_HAPS, 0xD}, | |
226 | {AXS_MB_SLV_CONTROL, 0x0}, /* MB Local CREG, CGU... */ | |
227 | {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xF}, | |
228 | }; | |
229 | ||
230 | static noinline void | |
231 | axs101_set_memmap(void __iomem *base, const struct aperture map[16]) | |
232 | { | |
233 | unsigned int slave_select, slave_offset; | |
234 | int i; | |
235 | ||
236 | slave_select = slave_offset = 0; | |
237 | for (i = 0; i < 8; i++) { | |
238 | slave_select |= map[i].slave_sel << (i << 2); | |
239 | slave_offset |= map[i].slave_off << (i << 2); | |
240 | } | |
241 | ||
242 | iowrite32(slave_select, base + 0x0); /* SLV0 */ | |
243 | iowrite32(slave_offset, base + 0x8); /* OFFSET0 */ | |
244 | ||
245 | slave_select = slave_offset = 0; | |
246 | for (i = 0; i < 8; i++) { | |
247 | slave_select |= map[i+8].slave_sel << (i << 2); | |
248 | slave_offset |= map[i+8].slave_off << (i << 2); | |
249 | } | |
250 | ||
251 | iowrite32(slave_select, base + 0x4); /* SLV1 */ | |
252 | iowrite32(slave_offset, base + 0xC); /* OFFSET1 */ | |
253 | } | |
254 | ||
255 | static void axs101_early_init(void) | |
256 | { | |
257 | int i; | |
258 | ||
259 | /* ARC 770D memory view */ | |
260 | axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap); | |
261 | iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD); | |
262 | ||
263 | /* AXI tunnel memory map (incoming traffic from MB into CPU Card */ | |
264 | axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN, | |
265 | axc001_axi_tunnel_memmap); | |
266 | iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD); | |
267 | ||
268 | /* MB peripherals memory map */ | |
269 | for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++) | |
270 | axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4), | |
271 | axs_mb_memmap); | |
272 | ||
273 | iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */ | |
274 | ||
275 | /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */ | |
276 | iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX); | |
277 | ||
278 | /* Set up the MB interrupt system: mux interrupts to GPIO7) */ | |
279 | iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX); | |
280 | ||
281 | /* reset ethernet and ULPI interfaces */ | |
282 | iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET); | |
283 | ||
284 | /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */ | |
285 | iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX); | |
286 | ||
287 | axs10x_early_init(); | |
288 | } | |
289 | ||
290 | static const char *axs101_compat[] __initconst = { | |
291 | "snps,axs101", | |
292 | NULL, | |
293 | }; | |
294 | ||
295 | MACHINE_START(AXS101, "axs101") | |
296 | .dt_compat = axs101_compat, | |
297 | .init_early = axs101_early_init, | |
298 | MACHINE_END |