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b2441318 1# SPDX-License-Identifier: GPL-2.0
1da177e4
LT
2config ARM
3 bool
4 default y
1d8f51d4 5 select ARCH_CLOCKSOURCE_DATA
cf1b0990 6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID
e377cd82 7 select ARCH_HAS_DEBUG_VIRTUAL
21266be9 8 select ARCH_HAS_DEVMEM_IS_ALLOWED
2b68f6ca 9 select ARCH_HAS_ELF_RANDOMIZE
d2852a22 10 select ARCH_HAS_SET_MEMORY
ad21fc4f
LA
11 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
12 select ARCH_HAS_STRICT_MODULE_RWX if MMU
3d06770e 13 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
171b3f0d 14 select ARCH_HAVE_CUSTOM_GPIO_H
957e3fac 15 select ARCH_HAS_GCOV_PROFILE_ALL
d7018848 16 select ARCH_MIGHT_HAVE_PC_PARPORT
ad21fc4f
LA
17 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
18 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
4badad35 19 select ARCH_SUPPORTS_ATOMIC_RMW
017f161a 20 select ARCH_USE_BUILTIN_BSWAP
0cbad9c9 21 select ARCH_USE_CMPXCHG_LOCKREF
b1b3f49c 22 select ARCH_WANT_IPC_PARSE_VERSION
ee951c63 23 select BUILDTIME_EXTABLE_SORT if MMU
171b3f0d 24 select CLONE_BACKWARDS
b1b3f49c 25 select CPU_PM if (SUSPEND || CPU_IDLE)
dce5c9e3 26 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
1c51c429 27 select DMA_NOOP_OPS if !MMU
b01aec9b
BP
28 select EDAC_SUPPORT
29 select EDAC_ATOMIC_SCRUB
36d0fd21 30 select GENERIC_ALLOCATOR
2ef7a295 31 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
4477ca45 32 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
b1b3f49c 33 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
ea2d9a96 34 select GENERIC_CPU_AUTOPROBE
2937367b 35 select GENERIC_EARLY_IOREMAP
171b3f0d 36 select GENERIC_IDLE_POLL_SETUP
b1b3f49c
RK
37 select GENERIC_IRQ_PROBE
38 select GENERIC_IRQ_SHOW
7c07005e 39 select GENERIC_IRQ_SHOW_LEVEL
b1b3f49c 40 select GENERIC_PCI_IOMAP
38ff87f7 41 select GENERIC_SCHED_CLOCK
b1b3f49c
RK
42 select GENERIC_SMP_IDLE_THREAD
43 select GENERIC_STRNCPY_FROM_USER
44 select GENERIC_STRNLEN_USER
a71b092a 45 select HANDLE_DOMAIN_IRQ
b1b3f49c 46 select HARDIRQS_SW_RESEND
7a017721 47 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
0b7857db 48 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
437682ee
AB
49 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
50 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
e0c25d95 51 select HAVE_ARCH_MMAP_RND_BITS if MMU
91702175 52 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
0693bf68 53 select HAVE_ARCH_TRACEHOOK
b329f95d 54 select HAVE_ARM_SMCCC if CPU_V7
39c13c20 55 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
51aaf81f 56 select HAVE_CC_STACKPROTECTOR
171b3f0d 57 select HAVE_CONTEXT_TRACKING
b1b3f49c
RK
58 select HAVE_C_RECORDMCOUNT
59 select HAVE_DEBUG_KMEMLEAK
60 select HAVE_DMA_API_DEBUG
b1b3f49c 61 select HAVE_DMA_CONTIGUOUS if MMU
437682ee 62 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
620176f3 63 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
dce5c9e3 64 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
5f56a5df 65 select HAVE_EXIT_THREAD
b1b3f49c 66 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
0e341af8 67 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
b1b3f49c 68 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
6b90bd4b 69 select HAVE_GCC_PLUGINS
1fe53268 70 select HAVE_GENERIC_DMA_COHERENT
b1b3f49c
RK
71 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
72 select HAVE_IDE if PCI || ISA || PCMCIA
87c46b6c 73 select HAVE_IRQ_TIME_ACCOUNTING
e7db7b42 74 select HAVE_KERNEL_GZIP
f9b493ac 75 select HAVE_KERNEL_LZ4
6e8699f7 76 select HAVE_KERNEL_LZMA
b1b3f49c 77 select HAVE_KERNEL_LZO
a7f464f3 78 select HAVE_KERNEL_XZ
cb1293e2 79 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
b1b3f49c
RK
80 select HAVE_KRETPROBES if (HAVE_KPROBES)
81 select HAVE_MEMBLOCK
7d485f64 82 select HAVE_MOD_ARCH_SPECIFIC
42a0bb3f 83 select HAVE_NMI
b1b3f49c 84 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
0dc016db 85 select HAVE_OPTPROBES if !THUMB2_KERNEL
7ada189f 86 select HAVE_PERF_EVENTS
49863894
WD
87 select HAVE_PERF_REGS
88 select HAVE_PERF_USER_STACK_DUMP
a0ad5496 89 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
e513f8bf 90 select HAVE_REGS_AND_STACK_ACCESS_API
b1b3f49c 91 select HAVE_SYSCALL_TRACEPOINTS
af1839eb 92 select HAVE_UID16
31c1fc81 93 select HAVE_VIRT_CPU_ACCOUNTING_GEN
da0ec6f7 94 select IRQ_FORCED_THREADING
171b3f0d 95 select MODULES_USE_ELF_REL
84f452b1 96 select NO_BOOTMEM
aa7d5f18
AB
97 select OF_EARLY_FLATTREE if OF
98 select OF_RESERVED_MEM if OF
171b3f0d
RK
99 select OLD_SIGACTION
100 select OLD_SIGSUSPEND3
b1b3f49c
RK
101 select PERF_USE_VMALLOC
102 select RTC_LIB
103 select SYS_SUPPORTS_APM_EMULATION
171b3f0d
RK
104 # Above selects are sorted alphabetically; please add new ones
105 # according to that. Thanks.
1da177e4
LT
106 help
107 The ARM series is a line of low-power-consumption RISC chip designs
f6c8965a 108 licensed by ARM Ltd and targeted at embedded applications and
1da177e4 109 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
f6c8965a 110 manufactured, but legacy ARM-based PC hardware remains popular in
1da177e4
LT
111 Europe. There is an ARM Linux project with a web page at
112 <http://www.arm.linux.org.uk/>.
113
74facffe 114config ARM_HAS_SG_CHAIN
308c09f1 115 select ARCH_HAS_SG_CHAIN
74facffe
RK
116 bool
117
4ce63fcd
MS
118config NEED_SG_DMA_LENGTH
119 bool
120
121config ARM_DMA_USE_IOMMU
4ce63fcd 122 bool
b1b3f49c
RK
123 select ARM_HAS_SG_CHAIN
124 select NEED_SG_DMA_LENGTH
4ce63fcd 125
60460abf
SWK
126if ARM_DMA_USE_IOMMU
127
128config ARM_DMA_IOMMU_ALIGNMENT
129 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
130 range 4 9
131 default 8
132 help
133 DMA mapping framework by default aligns all buffers to the smallest
134 PAGE_SIZE order which is greater than or equal to the requested buffer
135 size. This works well for buffers up to a few hundreds kilobytes, but
136 for larger buffers it just a waste of address space. Drivers which has
137 relatively small addressing window (like 64Mib) might run out of
138 virtual space with just a few allocations.
139
140 With this parameter you can specify the maximum PAGE_SIZE order for
141 DMA IOMMU buffers. Larger buffers will be aligned only to this
142 specified order. The order is expressed as a power of two multiplied
143 by the PAGE_SIZE.
144
145endif
146
0b05da72
HUK
147config MIGHT_HAVE_PCI
148 bool
149
75e7153a
RB
150config SYS_SUPPORTS_APM_EMULATION
151 bool
152
bc581770
LW
153config HAVE_TCM
154 bool
155 select GENERIC_ALLOCATOR
156
e119bfff
RK
157config HAVE_PROC_CPU
158 bool
159
ce816fa8 160config NO_IOPORT_MAP
5ea81769 161 bool
5ea81769 162
1da177e4
LT
163config EISA
164 bool
165 ---help---
166 The Extended Industry Standard Architecture (EISA) bus was
167 developed as an open alternative to the IBM MicroChannel bus.
168
169 The EISA bus provided some of the features of the IBM MicroChannel
170 bus while maintaining backward compatibility with cards made for
171 the older ISA bus. The EISA bus saw limited use between 1988 and
172 1995 when it was made obsolete by the PCI bus.
173
174 Say Y here if you are building a kernel for an EISA-based machine.
175
176 Otherwise, say N.
177
178config SBUS
179 bool
180
f16fb1ec
RK
181config STACKTRACE_SUPPORT
182 bool
183 default y
184
185config LOCKDEP_SUPPORT
186 bool
187 default y
188
7ad1bcb2
RK
189config TRACE_IRQFLAGS_SUPPORT
190 bool
cb1293e2 191 default !CPU_V7M
7ad1bcb2 192
1da177e4
LT
193config RWSEM_XCHGADD_ALGORITHM
194 bool
8a87411b 195 default y
1da177e4 196
f0d1b0b3
DH
197config ARCH_HAS_ILOG2_U32
198 bool
f0d1b0b3
DH
199
200config ARCH_HAS_ILOG2_U64
201 bool
f0d1b0b3 202
4a1b5733
EV
203config ARCH_HAS_BANDGAP
204 bool
205
a5f4c561
SA
206config FIX_EARLYCON_MEM
207 def_bool y if MMU
208
b89c3b16
AM
209config GENERIC_HWEIGHT
210 bool
211 default y
212
1da177e4
LT
213config GENERIC_CALIBRATE_DELAY
214 bool
215 default y
216
a08b6b79
AV
217config ARCH_MAY_HAVE_PC_FDC
218 bool
219
5ac6da66
CL
220config ZONE_DMA
221 bool
5ac6da66 222
ccd7ab7f
FT
223config NEED_DMA_MAP_STATE
224 def_bool y
225
c7edc9e3
DL
226config ARCH_SUPPORTS_UPROBES
227 def_bool y
228
58af4a24
RH
229config ARCH_HAS_DMA_SET_COHERENT_MASK
230 bool
231
1da177e4
LT
232config GENERIC_ISA_DMA
233 bool
234
1da177e4
LT
235config FIQ
236 bool
237
13a5045d
RH
238config NEED_RET_TO_USER
239 bool
240
034d2f5a
AV
241config ARCH_MTD_XIP
242 bool
243
dc21af99 244config ARM_PATCH_PHYS_VIRT
c1becedc
RK
245 bool "Patch physical to virtual translations at runtime" if EMBEDDED
246 default y
b511d75d 247 depends on !XIP_KERNEL && MMU
dc21af99 248 help
111e9a5c
RK
249 Patch phys-to-virt and virt-to-phys translation functions at
250 boot and module load time according to the position of the
251 kernel in system memory.
dc21af99 252
111e9a5c 253 This can only be used with non-XIP MMU kernels where the base
daece596 254 of physical memory is at a 16MB boundary.
dc21af99 255
c1becedc
RK
256 Only disable this option if you know that you do not require
257 this feature (eg, building a kernel for a single machine) and
258 you need to shrink the kernel to the minimal size.
dc21af99 259
c334bc15
RH
260config NEED_MACH_IO_H
261 bool
262 help
263 Select this when mach/io.h is required to provide special
264 definitions for this platform. The need for mach/io.h should
265 be avoided when possible.
266
0cdc8b92 267config NEED_MACH_MEMORY_H
1b9f95f8
NP
268 bool
269 help
0cdc8b92
NP
270 Select this when mach/memory.h is required to provide special
271 definitions for this platform. The need for mach/memory.h should
272 be avoided when possible.
dc21af99 273
1b9f95f8 274config PHYS_OFFSET
974c0724 275 hex "Physical address of main memory" if MMU
c6f54a9b 276 depends on !ARM_PATCH_PHYS_VIRT
974c0724 277 default DRAM_BASE if !MMU
c6f54a9b 278 default 0x00000000 if ARCH_EBSA110 || \
c6f54a9b
UKK
279 ARCH_FOOTBRIDGE || \
280 ARCH_INTEGRATOR || \
281 ARCH_IOP13XX || \
282 ARCH_KS8695 || \
8f2c0062 283 ARCH_REALVIEW
c6f54a9b
UKK
284 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
285 default 0x20000000 if ARCH_S5PV210
b8824c9a 286 default 0xc0000000 if ARCH_SA1100
111e9a5c 287 help
1b9f95f8
NP
288 Please provide the physical address corresponding to the
289 location of main memory in your system.
cada3c08 290
87e040b6
SG
291config GENERIC_BUG
292 def_bool y
293 depends on BUG
294
1bcad26e
KS
295config PGTABLE_LEVELS
296 int
297 default 3 if ARM_LPAE
298 default 2
299
1da177e4
LT
300source "init/Kconfig"
301
dc52ddc0
MH
302source "kernel/Kconfig.freezer"
303
1da177e4
LT
304menu "System Type"
305
3c427975
HC
306config MMU
307 bool "MMU-based Paged Memory Management Support"
308 default y
309 help
310 Select if you want MMU-based virtualised addressing space
311 support by paged memory management. If unsure, say 'Y'.
312
e0c25d95
DC
313config ARCH_MMAP_RND_BITS_MIN
314 default 8
315
316config ARCH_MMAP_RND_BITS_MAX
317 default 14 if PAGE_OFFSET=0x40000000
318 default 15 if PAGE_OFFSET=0x80000000
319 default 16
320
ccf50e23
RK
321#
322# The "ARM system type" choice list is ordered alphabetically by option
323# text. Please add new entries in the option alphabetic order.
324#
1da177e4
LT
325choice
326 prompt "ARM system type"
70722803 327 default ARM_SINGLE_ARMV7M if !MMU
1420b22b 328 default ARCH_MULTIPLATFORM if MMU
1da177e4 329
387798b3
RH
330config ARCH_MULTIPLATFORM
331 bool "Allow multiple platforms to be selected"
b1b3f49c 332 depends on MMU
42dc836d 333 select ARM_HAS_SG_CHAIN
387798b3
RH
334 select ARM_PATCH_PHYS_VIRT
335 select AUTO_ZRELADDR
bb0eb050 336 select TIMER_OF
66314223 337 select COMMON_CLK
ddb902cc 338 select GENERIC_CLOCKEVENTS
08d38beb 339 select MIGHT_HAVE_PCI
387798b3 340 select MULTI_IRQ_HANDLER
e13688fe 341 select PCI_DOMAINS if PCI
66314223
DN
342 select SPARSE_IRQ
343 select USE_OF
66314223 344
9c77bc43
SA
345config ARM_SINGLE_ARMV7M
346 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
347 depends on !MMU
9c77bc43 348 select ARM_NVIC
499f1640 349 select AUTO_ZRELADDR
bb0eb050 350 select TIMER_OF
9c77bc43
SA
351 select COMMON_CLK
352 select CPU_V7M
353 select GENERIC_CLOCKEVENTS
354 select NO_IOPORT_MAP
355 select SPARSE_IRQ
356 select USE_OF
357
1da177e4
LT
358config ARCH_EBSA110
359 bool "EBSA-110"
b1b3f49c 360 select ARCH_USES_GETTIMEOFFSET
c750815e 361 select CPU_SA110
f7e68bbf 362 select ISA
c334bc15 363 select NEED_MACH_IO_H
0cdc8b92 364 select NEED_MACH_MEMORY_H
ce816fa8 365 select NO_IOPORT_MAP
1da177e4
LT
366 help
367 This is an evaluation board for the StrongARM processor available
f6c8965a 368 from Digital. It has limited hardware on-board, including an
1da177e4
LT
369 Ethernet interface, two PCMCIA sockets, two serial ports and a
370 parallel port.
371
e7736d47
LB
372config ARCH_EP93XX
373 bool "EP93xx-based"
80320927 374 select ARCH_SPARSEMEM_ENABLE
e7736d47 375 select ARM_AMBA
cd5bad41 376 imply ARM_PATCH_PHYS_VIRT
e7736d47 377 select ARM_VIC
b8824c9a 378 select AUTO_ZRELADDR
6d803ba7 379 select CLKDEV_LOOKUP
000bc178 380 select CLKSRC_MMIO
b1b3f49c 381 select CPU_ARM920T
000bc178 382 select GENERIC_CLOCKEVENTS
5c34a4e8 383 select GPIOLIB
e7736d47
LB
384 help
385 This enables support for the Cirrus EP93xx series of CPUs.
386
1da177e4
LT
387config ARCH_FOOTBRIDGE
388 bool "FootBridge"
c750815e 389 select CPU_SA110
1da177e4 390 select FOOTBRIDGE
4e8d7637 391 select GENERIC_CLOCKEVENTS
d0ee9f40 392 select HAVE_IDE
8ef6e620 393 select NEED_MACH_IO_H if !MMU
0cdc8b92 394 select NEED_MACH_MEMORY_H
f999b8bd
MM
395 help
396 Support for systems based on the DC21285 companion chip
397 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
1da177e4 398
4af6fee1
DS
399config ARCH_NETX
400 bool "Hilscher NetX based"
b1b3f49c 401 select ARM_VIC
234b6ced 402 select CLKSRC_MMIO
c750815e 403 select CPU_ARM926T
2fcfe6b8 404 select GENERIC_CLOCKEVENTS
f999b8bd 405 help
4af6fee1
DS
406 This enables support for systems based on the Hilscher NetX Soc
407
3b938be6
RK
408config ARCH_IOP13XX
409 bool "IOP13xx-based"
410 depends on MMU
b1b3f49c 411 select CPU_XSC3
0cdc8b92 412 select NEED_MACH_MEMORY_H
13a5045d 413 select NEED_RET_TO_USER
b1b3f49c
RK
414 select PCI
415 select PLAT_IOP
416 select VMSPLIT_1G
37ebbcff 417 select SPARSE_IRQ
3b938be6
RK
418 help
419 Support for Intel's IOP13XX (XScale) family of processors.
420
3f7e5815
LB
421config ARCH_IOP32X
422 bool "IOP32x-based"
a4f7e763 423 depends on MMU
c750815e 424 select CPU_XSCALE
e9004f50 425 select GPIO_IOP
5c34a4e8 426 select GPIOLIB
13a5045d 427 select NEED_RET_TO_USER
f7e68bbf 428 select PCI
b1b3f49c 429 select PLAT_IOP
f999b8bd 430 help
3f7e5815
LB
431 Support for Intel's 80219 and IOP32X (XScale) family of
432 processors.
433
434config ARCH_IOP33X
435 bool "IOP33x-based"
436 depends on MMU
c750815e 437 select CPU_XSCALE
e9004f50 438 select GPIO_IOP
5c34a4e8 439 select GPIOLIB
13a5045d 440 select NEED_RET_TO_USER
3f7e5815 441 select PCI
b1b3f49c 442 select PLAT_IOP
3f7e5815
LB
443 help
444 Support for Intel's IOP33X (XScale) family of processors.
1da177e4 445
3b938be6
RK
446config ARCH_IXP4XX
447 bool "IXP4xx-based"
a4f7e763 448 depends on MMU
58af4a24 449 select ARCH_HAS_DMA_SET_COHERENT_MASK
51aaf81f 450 select ARCH_SUPPORTS_BIG_ENDIAN
234b6ced 451 select CLKSRC_MMIO
c750815e 452 select CPU_XSCALE
b1b3f49c 453 select DMABOUNCE if PCI
3b938be6 454 select GENERIC_CLOCKEVENTS
5c34a4e8 455 select GPIOLIB
0b05da72 456 select MIGHT_HAVE_PCI
c334bc15 457 select NEED_MACH_IO_H
9296d94d 458 select USB_EHCI_BIG_ENDIAN_DESC
171b3f0d 459 select USB_EHCI_BIG_ENDIAN_MMIO
c4713074 460 help
3b938be6 461 Support for Intel's IXP4XX (XScale) family of processors.
c4713074 462
edabd38e
SB
463config ARCH_DOVE
464 bool "Marvell Dove"
756b2531 465 select CPU_PJ4
edabd38e 466 select GENERIC_CLOCKEVENTS
5c34a4e8 467 select GPIOLIB
0f81bd43 468 select MIGHT_HAVE_PCI
b8cd337c 469 select MULTI_IRQ_HANDLER
171b3f0d 470 select MVEBU_MBUS
9139acd1
SH
471 select PINCTRL
472 select PINCTRL_DOVE
abcda1dc 473 select PLAT_ORION_LEGACY
0bd86961 474 select SPARSE_IRQ
c5d431e8 475 select PM_GENERIC_DOMAINS if PM
788c9700 476 help
edabd38e 477 Support for the Marvell Dove SoC 88AP510
788c9700
RK
478
479config ARCH_KS8695
480 bool "Micrel/Kendin KS8695"
c7e783d6 481 select CLKSRC_MMIO
b1b3f49c 482 select CPU_ARM922T
c7e783d6 483 select GENERIC_CLOCKEVENTS
5c34a4e8 484 select GPIOLIB
b1b3f49c 485 select NEED_MACH_MEMORY_H
788c9700
RK
486 help
487 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
488 System-on-Chip devices.
489
788c9700
RK
490config ARCH_W90X900
491 bool "Nuvoton W90X900 CPU"
6d803ba7 492 select CLKDEV_LOOKUP
6fa5d5f7 493 select CLKSRC_MMIO
b1b3f49c 494 select CPU_ARM926T
58b5369e 495 select GENERIC_CLOCKEVENTS
5c34a4e8 496 select GPIOLIB
788c9700 497 help
a8bc4ead 498 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
499 At present, the w90x900 has been renamed nuc900, regarding
500 the ARM series product line, you can login the following
501 link address to know more.
502
503 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
504 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
788c9700 505
93e22567
RK
506config ARCH_LPC32XX
507 bool "NXP LPC32XX"
93e22567
RK
508 select ARM_AMBA
509 select CLKDEV_LOOKUP
c227f127
VZ
510 select CLKSRC_LPC32XX
511 select COMMON_CLK
93e22567
RK
512 select CPU_ARM926T
513 select GENERIC_CLOCKEVENTS
5c34a4e8 514 select GPIOLIB
8cb17b5e
VZ
515 select MULTI_IRQ_HANDLER
516 select SPARSE_IRQ
93e22567
RK
517 select USE_OF
518 help
519 Support for the NXP LPC32XX family of processors
520
1da177e4 521config ARCH_PXA
2c8086a5 522 bool "PXA2xx/PXA3xx-based"
a4f7e763 523 depends on MMU
b1b3f49c 524 select ARCH_MTD_XIP
b1b3f49c
RK
525 select ARM_CPU_SUSPEND if PM
526 select AUTO_ZRELADDR
a1c0a6ad 527 select COMMON_CLK
6d803ba7 528 select CLKDEV_LOOKUP
389d9b58 529 select CLKSRC_PXA
234b6ced 530 select CLKSRC_MMIO
bb0eb050 531 select TIMER_OF
2f202861 532 select CPU_XSCALE if !CPU_XSC3
981d0f39 533 select GENERIC_CLOCKEVENTS
157d2644 534 select GPIO_PXA
5c34a4e8 535 select GPIOLIB
d0ee9f40 536 select HAVE_IDE
d6cf30ca 537 select IRQ_DOMAIN
b1b3f49c 538 select MULTI_IRQ_HANDLER
b1b3f49c
RK
539 select PLAT_PXA
540 select SPARSE_IRQ
f999b8bd 541 help
2c8086a5 542 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
1da177e4
LT
543
544config ARCH_RPC
545 bool "RiscPC"
868e87cc 546 depends on MMU
1da177e4 547 select ARCH_ACORN
a08b6b79 548 select ARCH_MAY_HAVE_PC_FDC
07f841b7 549 select ARCH_SPARSEMEM_ENABLE
5cfc8ee0 550 select ARCH_USES_GETTIMEOFFSET
fa04e209 551 select CPU_SA110
b1b3f49c 552 select FIQ
d0ee9f40 553 select HAVE_IDE
b1b3f49c
RK
554 select HAVE_PATA_PLATFORM
555 select ISA_DMA_API
c334bc15 556 select NEED_MACH_IO_H
0cdc8b92 557 select NEED_MACH_MEMORY_H
ce816fa8 558 select NO_IOPORT_MAP
1da177e4
LT
559 help
560 On the Acorn Risc-PC, Linux can support the internal IDE disk and
561 CD-ROM interface, serial and parallel port, and the floppy drive.
562
563config ARCH_SA1100
564 bool "SA1100-based"
b1b3f49c 565 select ARCH_MTD_XIP
b1b3f49c
RK
566 select ARCH_SPARSEMEM_ENABLE
567 select CLKDEV_LOOKUP
568 select CLKSRC_MMIO
389d9b58 569 select CLKSRC_PXA
bb0eb050 570 select TIMER_OF if OF
1937f5b9 571 select CPU_FREQ
b1b3f49c 572 select CPU_SA1100
3e238be2 573 select GENERIC_CLOCKEVENTS
5c34a4e8 574 select GPIOLIB
d0ee9f40 575 select HAVE_IDE
1eca42b4 576 select IRQ_DOMAIN
b1b3f49c 577 select ISA
affcab32 578 select MULTI_IRQ_HANDLER
0cdc8b92 579 select NEED_MACH_MEMORY_H
375dec92 580 select SPARSE_IRQ
f999b8bd
MM
581 help
582 Support for StrongARM 11x0 based boards.
1da177e4 583
b130d5c2
KK
584config ARCH_S3C24XX
585 bool "Samsung S3C24XX SoCs"
335cce74 586 select ATAGS
b1b3f49c 587 select CLKDEV_LOOKUP
4280506a 588 select CLKSRC_SAMSUNG_PWM
7f78b6eb 589 select GENERIC_CLOCKEVENTS
880cf071 590 select GPIO_SAMSUNG
5c34a4e8 591 select GPIOLIB
20676c15 592 select HAVE_S3C2410_I2C if I2C
b130d5c2 593 select HAVE_S3C2410_WATCHDOG if WATCHDOG
b1b3f49c 594 select HAVE_S3C_RTC if RTC_CLASS
17453dd2 595 select MULTI_IRQ_HANDLER
c334bc15 596 select NEED_MACH_IO_H
cd8dc7ae 597 select SAMSUNG_ATAGS
1da177e4 598 help
b130d5c2
KK
599 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
600 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
601 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
602 Samsung SMDK2410 development board (and derivatives).
63b1f51b 603
7c6337e2
KH
604config ARCH_DAVINCI
605 bool "TI DaVinci"
b1b3f49c 606 select ARCH_HAS_HOLES_MEMORYMODEL
6d803ba7 607 select CLKDEV_LOOKUP
ce32c5c5 608 select CPU_ARM926T
20e9969b 609 select GENERIC_ALLOCATOR
b1b3f49c 610 select GENERIC_CLOCKEVENTS
dc7ad3b3 611 select GENERIC_IRQ_CHIP
5c34a4e8 612 select GPIOLIB
b1b3f49c 613 select HAVE_IDE
689e331f 614 select USE_OF
b1b3f49c 615 select ZONE_DMA
7c6337e2
KH
616 help
617 Support for TI's DaVinci platform.
618
a0694861
TL
619config ARCH_OMAP1
620 bool "TI OMAP1"
00a36698 621 depends on MMU
9af915da 622 select ARCH_HAS_HOLES_MEMORYMODEL
a0694861 623 select ARCH_OMAP
b1b3f49c 624 select CLKDEV_LOOKUP
d6e15d78 625 select CLKSRC_MMIO
b1b3f49c 626 select GENERIC_CLOCKEVENTS
a0694861 627 select GENERIC_IRQ_CHIP
5c34a4e8 628 select GPIOLIB
a0694861
TL
629 select HAVE_IDE
630 select IRQ_DOMAIN
b694331c 631 select MULTI_IRQ_HANDLER
a0694861
TL
632 select NEED_MACH_IO_H if PCCARD
633 select NEED_MACH_MEMORY_H
685e2d08 634 select SPARSE_IRQ
21f47fbc 635 help
a0694861 636 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
02c981c0 637
1da177e4
LT
638endchoice
639
387798b3
RH
640menu "Multiple platform selection"
641 depends on ARCH_MULTIPLATFORM
642
643comment "CPU Core family selection"
644
f8afae40
AB
645config ARCH_MULTI_V4
646 bool "ARMv4 based platforms (FA526)"
647 depends on !ARCH_MULTI_V6_V7
648 select ARCH_MULTI_V4_V5
649 select CPU_FA526
650
387798b3
RH
651config ARCH_MULTI_V4T
652 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
387798b3 653 depends on !ARCH_MULTI_V6_V7
b1b3f49c 654 select ARCH_MULTI_V4_V5
24e860fb
AB
655 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
656 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
657 CPU_ARM925T || CPU_ARM940T)
387798b3
RH
658
659config ARCH_MULTI_V5
660 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
387798b3 661 depends on !ARCH_MULTI_V6_V7
b1b3f49c 662 select ARCH_MULTI_V4_V5
12567bbd 663 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
24e860fb
AB
664 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
665 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
387798b3
RH
666
667config ARCH_MULTI_V4_V5
668 bool
669
670config ARCH_MULTI_V6
8dda05cc 671 bool "ARMv6 based platforms (ARM11)"
387798b3 672 select ARCH_MULTI_V6_V7
42f4754a 673 select CPU_V6K
387798b3
RH
674
675config ARCH_MULTI_V7
8dda05cc 676 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
387798b3
RH
677 default y
678 select ARCH_MULTI_V6_V7
b1b3f49c 679 select CPU_V7
90bc8ac7 680 select HAVE_SMP
387798b3
RH
681
682config ARCH_MULTI_V6_V7
683 bool
9352b05b 684 select MIGHT_HAVE_CACHE_L2X0
387798b3
RH
685
686config ARCH_MULTI_CPU_AUTO
687 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
688 select ARCH_MULTI_V5
689
690endmenu
691
05e2a3de 692config ARCH_VIRT
e3246542
MY
693 bool "Dummy Virtual Machine"
694 depends on ARCH_MULTI_V7
4b8b5f25 695 select ARM_AMBA
05e2a3de 696 select ARM_GIC
3ee80364 697 select ARM_GIC_V2M if PCI
0b28f1db 698 select ARM_GIC_V3
bb29cecb 699 select ARM_GIC_V3_ITS if PCI
05e2a3de 700 select ARM_PSCI
4b8b5f25 701 select HAVE_ARM_ARCH_TIMER
05e2a3de 702
ccf50e23
RK
703#
704# This is sorted alphabetically by mach-* pathname. However, plat-*
705# Kconfigs may be included either alphabetically (according to the
706# plat- suffix) or along side the corresponding mach-* source.
707#
3e93a22b
GC
708source "arch/arm/mach-mvebu/Kconfig"
709
6bb8536c
AF
710source "arch/arm/mach-actions/Kconfig"
711
445d9b30
TZ
712source "arch/arm/mach-alpine/Kconfig"
713
590b460c
LP
714source "arch/arm/mach-artpec/Kconfig"
715
d9bfc86d
OR
716source "arch/arm/mach-asm9260/Kconfig"
717
95b8f20f
RK
718source "arch/arm/mach-at91/Kconfig"
719
1d22924e
AB
720source "arch/arm/mach-axxia/Kconfig"
721
8ac49e04
CD
722source "arch/arm/mach-bcm/Kconfig"
723
1c37fa10
SH
724source "arch/arm/mach-berlin/Kconfig"
725
1da177e4
LT
726source "arch/arm/mach-clps711x/Kconfig"
727
d94f944e
AV
728source "arch/arm/mach-cns3xxx/Kconfig"
729
95b8f20f
RK
730source "arch/arm/mach-davinci/Kconfig"
731
df8d742e
BS
732source "arch/arm/mach-digicolor/Kconfig"
733
95b8f20f
RK
734source "arch/arm/mach-dove/Kconfig"
735
e7736d47
LB
736source "arch/arm/mach-ep93xx/Kconfig"
737
1da177e4
LT
738source "arch/arm/mach-footbridge/Kconfig"
739
59d3a193
PZ
740source "arch/arm/mach-gemini/Kconfig"
741
387798b3
RH
742source "arch/arm/mach-highbank/Kconfig"
743
389ee0c2
HZ
744source "arch/arm/mach-hisi/Kconfig"
745
1da177e4
LT
746source "arch/arm/mach-integrator/Kconfig"
747
3f7e5815
LB
748source "arch/arm/mach-iop32x/Kconfig"
749
750source "arch/arm/mach-iop33x/Kconfig"
1da177e4 751
285f5fa7
DW
752source "arch/arm/mach-iop13xx/Kconfig"
753
1da177e4
LT
754source "arch/arm/mach-ixp4xx/Kconfig"
755
828989ad
SS
756source "arch/arm/mach-keystone/Kconfig"
757
95b8f20f
RK
758source "arch/arm/mach-ks8695/Kconfig"
759
3b8f5030
CC
760source "arch/arm/mach-meson/Kconfig"
761
17723fd3
JJ
762source "arch/arm/mach-moxart/Kconfig"
763
8c2ed9bc
JS
764source "arch/arm/mach-aspeed/Kconfig"
765
794d15b2
SS
766source "arch/arm/mach-mv78xx0/Kconfig"
767
3995eb82 768source "arch/arm/mach-imx/Kconfig"
1da177e4 769
f682a218
MB
770source "arch/arm/mach-mediatek/Kconfig"
771
1d3f33d5
SG
772source "arch/arm/mach-mxs/Kconfig"
773
95b8f20f 774source "arch/arm/mach-netx/Kconfig"
49cbe786 775
95b8f20f 776source "arch/arm/mach-nomadik/Kconfig"
95b8f20f 777
9851ca57
DT
778source "arch/arm/mach-nspire/Kconfig"
779
d48af15e
TL
780source "arch/arm/plat-omap/Kconfig"
781
782source "arch/arm/mach-omap1/Kconfig"
1da177e4 783
1dbae815
TL
784source "arch/arm/mach-omap2/Kconfig"
785
9dd0b194 786source "arch/arm/mach-orion5x/Kconfig"
585cf175 787
387798b3
RH
788source "arch/arm/mach-picoxcell/Kconfig"
789
95b8f20f
RK
790source "arch/arm/mach-pxa/Kconfig"
791source "arch/arm/plat-pxa/Kconfig"
585cf175 792
95b8f20f
RK
793source "arch/arm/mach-mmp/Kconfig"
794
8c9184b7
NA
795source "arch/arm/mach-oxnas/Kconfig"
796
8fc1b0f8
KG
797source "arch/arm/mach-qcom/Kconfig"
798
95b8f20f
RK
799source "arch/arm/mach-realview/Kconfig"
800
d63dc051
HS
801source "arch/arm/mach-rockchip/Kconfig"
802
95b8f20f 803source "arch/arm/mach-sa1100/Kconfig"
edabd38e 804
387798b3
RH
805source "arch/arm/mach-socfpga/Kconfig"
806
a7ed099f 807source "arch/arm/mach-spear/Kconfig"
a21765a7 808
65ebcc11
SK
809source "arch/arm/mach-sti/Kconfig"
810
bcb84fb4
AT
811source "arch/arm/mach-stm32/Kconfig"
812
85fd6d63 813source "arch/arm/mach-s3c24xx/Kconfig"
1da177e4 814
431107ea 815source "arch/arm/mach-s3c64xx/Kconfig"
a08ab637 816
170f4e42
KK
817source "arch/arm/mach-s5pv210/Kconfig"
818
83014579 819source "arch/arm/mach-exynos/Kconfig"
e509b289 820source "arch/arm/plat-samsung/Kconfig"
cc0e72b8 821
882d01f9 822source "arch/arm/mach-shmobile/Kconfig"
52c543f9 823
3b52634f
MR
824source "arch/arm/mach-sunxi/Kconfig"
825
156a0997
BS
826source "arch/arm/mach-prima2/Kconfig"
827
d6de5b02
MG
828source "arch/arm/mach-tango/Kconfig"
829
c5f80065
EG
830source "arch/arm/mach-tegra/Kconfig"
831
95b8f20f 832source "arch/arm/mach-u300/Kconfig"
1da177e4 833
ba56a987
MY
834source "arch/arm/mach-uniphier/Kconfig"
835
95b8f20f 836source "arch/arm/mach-ux500/Kconfig"
1da177e4
LT
837
838source "arch/arm/mach-versatile/Kconfig"
839
ceade897 840source "arch/arm/mach-vexpress/Kconfig"
420c34e4 841source "arch/arm/plat-versatile/Kconfig"
ceade897 842
6f35f9a9
TP
843source "arch/arm/mach-vt8500/Kconfig"
844
7ec80ddf 845source "arch/arm/mach-w90x900/Kconfig"
846
acede515
JN
847source "arch/arm/mach-zx/Kconfig"
848
9a45eb69
JC
849source "arch/arm/mach-zynq/Kconfig"
850
499f1640
SA
851# ARMv7-M architecture
852config ARCH_EFM32
853 bool "Energy Micro efm32"
854 depends on ARM_SINGLE_ARMV7M
5c34a4e8 855 select GPIOLIB
499f1640
SA
856 help
857 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
858 processors.
859
860config ARCH_LPC18XX
861 bool "NXP LPC18xx/LPC43xx"
862 depends on ARM_SINGLE_ARMV7M
863 select ARCH_HAS_RESET_CONTROLLER
864 select ARM_AMBA
865 select CLKSRC_LPC32XX
866 select PINCTRL
867 help
868 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
869 high performance microcontrollers.
870
1847119d 871config ARCH_MPS2
17bd274e 872 bool "ARM MPS2 platform"
1847119d
VM
873 depends on ARM_SINGLE_ARMV7M
874 select ARM_AMBA
875 select CLKSRC_MPS2
876 help
877 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
878 with a range of available cores like Cortex-M3/M4/M7.
879
880 Please, note that depends which Application Note is used memory map
881 for the platform may vary, so adjustment of RAM base might be needed.
882
1da177e4
LT
883# Definitions to make life easier
884config ARCH_ACORN
885 bool
886
7ae1f7ec
LB
887config PLAT_IOP
888 bool
469d3044 889 select GENERIC_CLOCKEVENTS
7ae1f7ec 890
69b02f6a
LB
891config PLAT_ORION
892 bool
bfe45e0b 893 select CLKSRC_MMIO
b1b3f49c 894 select COMMON_CLK
dc7ad3b3 895 select GENERIC_IRQ_CHIP
278b45b0 896 select IRQ_DOMAIN
69b02f6a 897
abcda1dc
TP
898config PLAT_ORION_LEGACY
899 bool
900 select PLAT_ORION
901
bd5ce433
EM
902config PLAT_PXA
903 bool
904
f4b8b319
RK
905config PLAT_VERSATILE
906 bool
907
d9a1beaa
AC
908source "arch/arm/firmware/Kconfig"
909
1da177e4
LT
910source arch/arm/mm/Kconfig
911
afe4b25e 912config IWMMXT
d93003e8
SH
913 bool "Enable iWMMXt support"
914 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
915 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
afe4b25e
LB
916 help
917 Enable support for iWMMXt context switching at run time if
918 running on a CPU that supports it.
919
52108641 920config MULTI_IRQ_HANDLER
921 bool
922 help
923 Allow each machine to specify it's own IRQ handler at run time.
924
3b93e7b0
HC
925if !MMU
926source "arch/arm/Kconfig-nommu"
927endif
928
3e0a07f8
GC
929config PJ4B_ERRATA_4742
930 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
931 depends on CPU_PJ4B && MACH_ARMADA_370
932 default y
933 help
934 When coming out of either a Wait for Interrupt (WFI) or a Wait for
935 Event (WFE) IDLE states, a specific timing sensitivity exists between
936 the retiring WFI/WFE instructions and the newly issued subsequent
937 instructions. This sensitivity can result in a CPU hang scenario.
938 Workaround:
939 The software must insert either a Data Synchronization Barrier (DSB)
940 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
941 instruction
942
f0c4b8d6
WD
943config ARM_ERRATA_326103
944 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
945 depends on CPU_V6
946 help
947 Executing a SWP instruction to read-only memory does not set bit 11
948 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
949 treat the access as a read, preventing a COW from occurring and
950 causing the faulting task to livelock.
951
9cba3ccc
CM
952config ARM_ERRATA_411920
953 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
e399b1a4 954 depends on CPU_V6 || CPU_V6K
9cba3ccc
CM
955 help
956 Invalidation of the Instruction Cache operation can
957 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
958 It does not affect the MPCore. This option enables the ARM Ltd.
959 recommended workaround.
960
7ce236fc
CM
961config ARM_ERRATA_430973
962 bool "ARM errata: Stale prediction on replaced interworking branch"
963 depends on CPU_V7
964 help
965 This option enables the workaround for the 430973 Cortex-A8
79403cda 966 r1p* erratum. If a code sequence containing an ARM/Thumb
7ce236fc
CM
967 interworking branch is replaced with another code sequence at the
968 same virtual address, whether due to self-modifying code or virtual
969 to physical address re-mapping, Cortex-A8 does not recover from the
970 stale interworking branch prediction. This results in Cortex-A8
971 executing the new code sequence in the incorrect ARM or Thumb state.
972 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
973 and also flushes the branch target cache at every context switch.
974 Note that setting specific bits in the ACTLR register may not be
975 available in non-secure mode.
976
855c551f
CM
977config ARM_ERRATA_458693
978 bool "ARM errata: Processor deadlock when a false hazard is created"
979 depends on CPU_V7
62e4d357 980 depends on !ARCH_MULTIPLATFORM
855c551f
CM
981 help
982 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
983 erratum. For very specific sequences of memory operations, it is
984 possible for a hazard condition intended for a cache line to instead
985 be incorrectly associated with a different cache line. This false
986 hazard might then cause a processor deadlock. The workaround enables
987 the L1 caching of the NEON accesses and disables the PLD instruction
988 in the ACTLR register. Note that setting specific bits in the ACTLR
989 register may not be available in non-secure mode.
990
0516e464
CM
991config ARM_ERRATA_460075
992 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
993 depends on CPU_V7
62e4d357 994 depends on !ARCH_MULTIPLATFORM
0516e464
CM
995 help
996 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
997 erratum. Any asynchronous access to the L2 cache may encounter a
998 situation in which recent store transactions to the L2 cache are lost
999 and overwritten with stale memory contents from external memory. The
1000 workaround disables the write-allocate mode for the L2 cache via the
1001 ACTLR register. Note that setting specific bits in the ACTLR register
1002 may not be available in non-secure mode.
1003
9f05027c
WD
1004config ARM_ERRATA_742230
1005 bool "ARM errata: DMB operation may be faulty"
1006 depends on CPU_V7 && SMP
62e4d357 1007 depends on !ARCH_MULTIPLATFORM
9f05027c
WD
1008 help
1009 This option enables the workaround for the 742230 Cortex-A9
1010 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1011 between two write operations may not ensure the correct visibility
1012 ordering of the two writes. This workaround sets a specific bit in
1013 the diagnostic register of the Cortex-A9 which causes the DMB
1014 instruction to behave as a DSB, ensuring the correct behaviour of
1015 the two writes.
1016
a672e99b
WD
1017config ARM_ERRATA_742231
1018 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1019 depends on CPU_V7 && SMP
62e4d357 1020 depends on !ARCH_MULTIPLATFORM
a672e99b
WD
1021 help
1022 This option enables the workaround for the 742231 Cortex-A9
1023 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1024 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1025 accessing some data located in the same cache line, may get corrupted
1026 data due to bad handling of the address hazard when the line gets
1027 replaced from one of the CPUs at the same time as another CPU is
1028 accessing it. This workaround sets specific bits in the diagnostic
1029 register of the Cortex-A9 which reduces the linefill issuing
1030 capabilities of the processor.
1031
69155794
JM
1032config ARM_ERRATA_643719
1033 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1034 depends on CPU_V7 && SMP
e5a5de44 1035 default y
69155794
JM
1036 help
1037 This option enables the workaround for the 643719 Cortex-A9 (prior to
1038 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1039 register returns zero when it should return one. The workaround
1040 corrects this value, ensuring cache maintenance operations which use
1041 it behave as intended and avoiding data corruption.
1042
cdf357f1
WD
1043config ARM_ERRATA_720789
1044 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
e66dc745 1045 depends on CPU_V7
cdf357f1
WD
1046 help
1047 This option enables the workaround for the 720789 Cortex-A9 (prior to
1048 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1049 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1050 As a consequence of this erratum, some TLB entries which should be
1051 invalidated are not, resulting in an incoherency in the system page
1052 tables. The workaround changes the TLB flushing routines to invalidate
1053 entries regardless of the ASID.
475d92fc
WD
1054
1055config ARM_ERRATA_743622
1056 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1057 depends on CPU_V7
62e4d357 1058 depends on !ARCH_MULTIPLATFORM
475d92fc
WD
1059 help
1060 This option enables the workaround for the 743622 Cortex-A9
efbc74ac 1061 (r2p*) erratum. Under very rare conditions, a faulty
475d92fc
WD
1062 optimisation in the Cortex-A9 Store Buffer may lead to data
1063 corruption. This workaround sets a specific bit in the diagnostic
1064 register of the Cortex-A9 which disables the Store Buffer
1065 optimisation, preventing the defect from occurring. This has no
1066 visible impact on the overall performance or power consumption of the
1067 processor.
1068
9a27c27c
WD
1069config ARM_ERRATA_751472
1070 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
ba90c516 1071 depends on CPU_V7
62e4d357 1072 depends on !ARCH_MULTIPLATFORM
9a27c27c
WD
1073 help
1074 This option enables the workaround for the 751472 Cortex-A9 (prior
1075 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1076 completion of a following broadcasted operation if the second
1077 operation is received by a CPU before the ICIALLUIS has completed,
1078 potentially leading to corrupted entries in the cache or TLB.
1079
fcbdc5fe
WD
1080config ARM_ERRATA_754322
1081 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1082 depends on CPU_V7
1083 help
1084 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1085 r3p*) erratum. A speculative memory access may cause a page table walk
1086 which starts prior to an ASID switch but completes afterwards. This
1087 can populate the micro-TLB with a stale entry which may be hit with
1088 the new ASID. This workaround places two dsb instructions in the mm
1089 switching code so that no page table walks can cross the ASID switch.
1090
5dab26af
WD
1091config ARM_ERRATA_754327
1092 bool "ARM errata: no automatic Store Buffer drain"
1093 depends on CPU_V7 && SMP
1094 help
1095 This option enables the workaround for the 754327 Cortex-A9 (prior to
1096 r2p0) erratum. The Store Buffer does not have any automatic draining
1097 mechanism and therefore a livelock may occur if an external agent
1098 continuously polls a memory location waiting to observe an update.
1099 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1100 written polling loops from denying visibility of updates to memory.
1101
145e10e1
CM
1102config ARM_ERRATA_364296
1103 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
fd832478 1104 depends on CPU_V6
145e10e1
CM
1105 help
1106 This options enables the workaround for the 364296 ARM1136
1107 r0p2 erratum (possible cache data corruption with
1108 hit-under-miss enabled). It sets the undocumented bit 31 in
1109 the auxiliary control register and the FI bit in the control
1110 register, thus disabling hit-under-miss without putting the
1111 processor into full low interrupt latency mode. ARM11MPCore
1112 is not affected.
1113
f630c1bd
WD
1114config ARM_ERRATA_764369
1115 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1116 depends on CPU_V7 && SMP
1117 help
1118 This option enables the workaround for erratum 764369
1119 affecting Cortex-A9 MPCore with two or more processors (all
1120 current revisions). Under certain timing circumstances, a data
1121 cache line maintenance operation by MVA targeting an Inner
1122 Shareable memory region may fail to proceed up to either the
1123 Point of Coherency or to the Point of Unification of the
1124 system. This workaround adds a DSB instruction before the
1125 relevant cache maintenance functions and sets a specific bit
1126 in the diagnostic control register of the SCU.
1127
7253b85c
SH
1128config ARM_ERRATA_775420
1129 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1130 depends on CPU_V7
1131 help
1132 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1133 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1134 operation aborts with MMU exception, it might cause the processor
1135 to deadlock. This workaround puts DSB before executing ISB if
1136 an abort may occur on cache maintenance.
1137
93dc6887
CM
1138config ARM_ERRATA_798181
1139 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1140 depends on CPU_V7 && SMP
1141 help
1142 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1143 adequately shooting down all use of the old entries. This
1144 option enables the Linux kernel workaround for this erratum
1145 which sends an IPI to the CPUs that are running the same ASID
1146 as the one being invalidated.
1147
84b6504f
WD
1148config ARM_ERRATA_773022
1149 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1150 depends on CPU_V7
1151 help
1152 This option enables the workaround for the 773022 Cortex-A15
1153 (up to r0p4) erratum. In certain rare sequences of code, the
1154 loop buffer may deliver incorrect instructions. This
1155 workaround disables the loop buffer to avoid the erratum.
1156
62c0f4a5
DA
1157config ARM_ERRATA_818325_852422
1158 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1159 depends on CPU_V7
1160 help
1161 This option enables the workaround for:
1162 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1163 instruction might deadlock. Fixed in r0p1.
1164 - Cortex-A12 852422: Execution of a sequence of instructions might
1165 lead to either a data corruption or a CPU deadlock. Not fixed in
1166 any Cortex-A12 cores yet.
1167 This workaround for all both errata involves setting bit[12] of the
1168 Feature Register. This bit disables an optimisation applied to a
1169 sequence of 2 instructions that use opposing condition codes.
1170
416bcf21
DA
1171config ARM_ERRATA_821420
1172 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1173 depends on CPU_V7
1174 help
1175 This option enables the workaround for the 821420 Cortex-A12
1176 (all revs) erratum. In very rare timing conditions, a sequence
1177 of VMOV to Core registers instructions, for which the second
1178 one is in the shadow of a branch or abort, can lead to a
1179 deadlock when the VMOV instructions are issued out-of-order.
1180
9f6f9354
DA
1181config ARM_ERRATA_825619
1182 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1183 depends on CPU_V7
1184 help
1185 This option enables the workaround for the 825619 Cortex-A12
1186 (all revs) erratum. Within rare timing constraints, executing a
1187 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1188 and Device/Strongly-Ordered loads and stores might cause deadlock
1189
1190config ARM_ERRATA_852421
1191 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1192 depends on CPU_V7
1193 help
1194 This option enables the workaround for the 852421 Cortex-A17
1195 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1196 execution of a DMB ST instruction might fail to properly order
1197 stores from GroupA and stores from GroupB.
1198
62c0f4a5
DA
1199config ARM_ERRATA_852423
1200 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1201 depends on CPU_V7
1202 help
1203 This option enables the workaround for:
1204 - Cortex-A17 852423: Execution of a sequence of instructions might
1205 lead to either a data corruption or a CPU deadlock. Not fixed in
1206 any Cortex-A17 cores yet.
1207 This is identical to Cortex-A12 erratum 852422. It is a separate
1208 config option from the A12 erratum due to the way errata are checked
1209 for and handled.
1210
1da177e4
LT
1211endmenu
1212
1213source "arch/arm/common/Kconfig"
1214
1da177e4
LT
1215menu "Bus support"
1216
1da177e4
LT
1217config ISA
1218 bool
1da177e4
LT
1219 help
1220 Find out whether you have ISA slots on your motherboard. ISA is the
1221 name of a bus system, i.e. the way the CPU talks to the other stuff
1222 inside your box. Other bus systems are PCI, EISA, MicroChannel
1223 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1224 newer boards don't support it. If you have ISA, say Y, otherwise N.
1225
065909b9 1226# Select ISA DMA controller support
1da177e4
LT
1227config ISA_DMA
1228 bool
065909b9 1229 select ISA_DMA_API
1da177e4 1230
065909b9 1231# Select ISA DMA interface
5cae841b
AV
1232config ISA_DMA_API
1233 bool
5cae841b 1234
1da177e4 1235config PCI
0b05da72 1236 bool "PCI support" if MIGHT_HAVE_PCI
1da177e4
LT
1237 help
1238 Find out whether you have a PCI motherboard. PCI is the name of a
1239 bus system, i.e. the way the CPU talks to the other stuff inside
1240 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1241 VESA. If you have PCI, say Y, otherwise N.
1242
52882173
AV
1243config PCI_DOMAINS
1244 bool
1245 depends on PCI
1246
8c7d1474
LP
1247config PCI_DOMAINS_GENERIC
1248 def_bool PCI_DOMAINS
1249
b080ac8a
MRJ
1250config PCI_NANOENGINE
1251 bool "BSE nanoEngine PCI support"
1252 depends on SA1100_NANOENGINE
1253 help
1254 Enable PCI on the BSE nanoEngine board.
1255
36e23590
MW
1256config PCI_SYSCALL
1257 def_bool PCI
1258
a0113a99
MR
1259config PCI_HOST_ITE8152
1260 bool
1261 depends on PCI && MACH_ARMCORE
1262 default y
1263 select DMABOUNCE
1264
1da177e4
LT
1265source "drivers/pci/Kconfig"
1266
1267source "drivers/pcmcia/Kconfig"
1268
1269endmenu
1270
1271menu "Kernel Features"
1272
3b55658a
DM
1273config HAVE_SMP
1274 bool
1275 help
1276 This option should be selected by machines which have an SMP-
1277 capable CPU.
1278
1279 The only effect of this option is to make the SMP-related
1280 options available to the user for configuration.
1281
1da177e4 1282config SMP
bb2d8130 1283 bool "Symmetric Multi-Processing"
fbb4ddac 1284 depends on CPU_V6K || CPU_V7
bc28248e 1285 depends on GENERIC_CLOCKEVENTS
3b55658a 1286 depends on HAVE_SMP
801bb21c 1287 depends on MMU || ARM_MPU
0361748f 1288 select IRQ_WORK
1da177e4
LT
1289 help
1290 This enables support for systems with more than one CPU. If you have
4a474157
RG
1291 a system with only one CPU, say N. If you have a system with more
1292 than one CPU, say Y.
1da177e4 1293
4a474157 1294 If you say N here, the kernel will run on uni- and multiprocessor
1da177e4 1295 machines, but will use only one CPU of a multiprocessor machine. If
4a474157
RG
1296 you say Y here, the kernel will run on many, but not all,
1297 uniprocessor machines. On a uniprocessor machine, the kernel
1298 will run faster if you say N here.
1da177e4 1299
395cf969 1300 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1da177e4 1301 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
50a23e6e 1302 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1da177e4
LT
1303
1304 If you don't know what to do here, say N.
1305
f00ec48f 1306config SMP_ON_UP
5744ff43 1307 bool "Allow booting SMP kernel on uniprocessor systems"
801bb21c 1308 depends on SMP && !XIP_KERNEL && MMU
f00ec48f
RK
1309 default y
1310 help
1311 SMP kernels contain instructions which fail on non-SMP processors.
1312 Enabling this option allows the kernel to modify itself to make
1313 these instructions safe. Disabling it allows about 1K of space
1314 savings.
1315
1316 If you don't know what to do here, say Y.
1317
c9018aab
VG
1318config ARM_CPU_TOPOLOGY
1319 bool "Support cpu topology definition"
1320 depends on SMP && CPU_V7
1321 default y
1322 help
1323 Support ARM cpu topology definition. The MPIDR register defines
1324 affinity between processors which is then used to describe the cpu
1325 topology of an ARM System.
1326
1327config SCHED_MC
1328 bool "Multi-core scheduler support"
1329 depends on ARM_CPU_TOPOLOGY
1330 help
1331 Multi-core scheduler support improves the CPU scheduler's decision
1332 making when dealing with multi-core CPU chips at a cost of slightly
1333 increased overhead in some places. If unsure say N here.
1334
1335config SCHED_SMT
1336 bool "SMT scheduler support"
1337 depends on ARM_CPU_TOPOLOGY
1338 help
1339 Improves the CPU scheduler's decision making when dealing with
1340 MultiThreading at a cost of slightly increased overhead in some
1341 places. If unsure say N here.
1342
a8cbcd92
RK
1343config HAVE_ARM_SCU
1344 bool
a8cbcd92
RK
1345 help
1346 This option enables support for the ARM system coherency unit
1347
8a4da6e3 1348config HAVE_ARM_ARCH_TIMER
022c03a2
MZ
1349 bool "Architected timer support"
1350 depends on CPU_V7
8a4da6e3 1351 select ARM_ARCH_TIMER
0c403462 1352 select GENERIC_CLOCKEVENTS
022c03a2
MZ
1353 help
1354 This option enables support for the ARM architected timer
1355
f32f4ce2
RK
1356config HAVE_ARM_TWD
1357 bool
bb0eb050 1358 select TIMER_OF if OF
f32f4ce2
RK
1359 help
1360 This options enables support for the ARM timer and watchdog unit
1361
e8db288e
NP
1362config MCPM
1363 bool "Multi-Cluster Power Management"
1364 depends on CPU_V7 && SMP
1365 help
1366 This option provides the common power management infrastructure
1367 for (multi-)cluster based systems, such as big.LITTLE based
1368 systems.
1369
ebf4a5c5
HZ
1370config MCPM_QUAD_CLUSTER
1371 bool
1372 depends on MCPM
1373 help
1374 To avoid wasting resources unnecessarily, MCPM only supports up
1375 to 2 clusters by default.
1376 Platforms with 3 or 4 clusters that use MCPM must select this
1377 option to allow the additional clusters to be managed.
1378
1c33be57
NP
1379config BIG_LITTLE
1380 bool "big.LITTLE support (Experimental)"
1381 depends on CPU_V7 && SMP
1382 select MCPM
1383 help
1384 This option enables support selections for the big.LITTLE
1385 system architecture.
1386
1387config BL_SWITCHER
1388 bool "big.LITTLE switcher support"
6c044fec 1389 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
51aaf81f 1390 select CPU_PM
1c33be57
NP
1391 help
1392 The big.LITTLE "switcher" provides the core functionality to
1393 transparently handle transition between a cluster of A15's
1394 and a cluster of A7's in a big.LITTLE system.
1395
b22537c6
NP
1396config BL_SWITCHER_DUMMY_IF
1397 tristate "Simple big.LITTLE switcher user interface"
1398 depends on BL_SWITCHER && DEBUG_KERNEL
1399 help
1400 This is a simple and dummy char dev interface to control
1401 the big.LITTLE switcher core code. It is meant for
1402 debugging purposes only.
1403
8d5796d2
LB
1404choice
1405 prompt "Memory split"
006fa259 1406 depends on MMU
8d5796d2
LB
1407 default VMSPLIT_3G
1408 help
1409 Select the desired split between kernel and user memory.
1410
1411 If you are not absolutely sure what you are doing, leave this
1412 option alone!
1413
1414 config VMSPLIT_3G
1415 bool "3G/1G user/kernel split"
63ce446c 1416 config VMSPLIT_3G_OPT
bbeedfda 1417 depends on !ARM_LPAE
63ce446c 1418 bool "3G/1G user/kernel split (for full 1G low memory)"
8d5796d2
LB
1419 config VMSPLIT_2G
1420 bool "2G/2G user/kernel split"
1421 config VMSPLIT_1G
1422 bool "1G/3G user/kernel split"
1423endchoice
1424
1425config PAGE_OFFSET
1426 hex
006fa259 1427 default PHYS_OFFSET if !MMU
8d5796d2
LB
1428 default 0x40000000 if VMSPLIT_1G
1429 default 0x80000000 if VMSPLIT_2G
63ce446c 1430 default 0xB0000000 if VMSPLIT_3G_OPT
8d5796d2
LB
1431 default 0xC0000000
1432
1da177e4
LT
1433config NR_CPUS
1434 int "Maximum number of CPUs (2-32)"
1435 range 2 32
1436 depends on SMP
1437 default "4"
1438
a054a811 1439config HOTPLUG_CPU
00b7dede 1440 bool "Support for hot-pluggable CPUs"
40b31360 1441 depends on SMP
6e77f633 1442 select GENERIC_IRQ_MIGRATION
a054a811
RK
1443 help
1444 Say Y here to experiment with turning CPUs off and on. CPUs
1445 can be controlled through /sys/devices/system/cpu.
1446
2bdd424f
WD
1447config ARM_PSCI
1448 bool "Support for the ARM Power State Coordination Interface (PSCI)"
e679660d 1449 depends on HAVE_ARM_SMCCC
be120397 1450 select ARM_PSCI_FW
2bdd424f
WD
1451 help
1452 Say Y here if you want Linux to communicate with system firmware
1453 implementing the PSCI specification for CPU-centric power
1454 management operations described in ARM document number ARM DEN
1455 0022A ("Power State Coordination Interface System Software on
1456 ARM processors").
1457
2a6ad871
MR
1458# The GPIO number here must be sorted by descending number. In case of
1459# a multiplatform kernel, we just want the highest value required by the
1460# selected platforms.
44986ab0
PDSN
1461config ARCH_NR_GPIO
1462 int
139358be 1463 default 2048 if ARCH_SOCFPGA
b35d2e56
GF
1464 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1465 ARCH_ZYNQ
aa42587a
TF
1466 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1467 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
eb171a99 1468 default 416 if ARCH_SUNXI
06b851e5 1469 default 392 if ARCH_U8500
01bb914c 1470 default 352 if ARCH_VT8500
7b5da4c3 1471 default 288 if ARCH_ROCKCHIP
2a6ad871 1472 default 264 if MACH_H4700
44986ab0
PDSN
1473 default 0
1474 help
1475 Maximum number of GPIOs in the system.
1476
1477 If unsure, leave the default value.
1478
d45a398f 1479source kernel/Kconfig.preempt
1da177e4 1480
c9218b16 1481config HZ_FIXED
f8065813 1482 int
da6b21e9 1483 default 200 if ARCH_EBSA110
1164f672 1484 default 128 if SOC_AT91RM9200
47d84682 1485 default 0
c9218b16
RK
1486
1487choice
47d84682 1488 depends on HZ_FIXED = 0
c9218b16
RK
1489 prompt "Timer frequency"
1490
1491config HZ_100
1492 bool "100 Hz"
1493
1494config HZ_200
1495 bool "200 Hz"
1496
1497config HZ_250
1498 bool "250 Hz"
1499
1500config HZ_300
1501 bool "300 Hz"
1502
1503config HZ_500
1504 bool "500 Hz"
1505
1506config HZ_1000
1507 bool "1000 Hz"
1508
1509endchoice
1510
1511config HZ
1512 int
47d84682 1513 default HZ_FIXED if HZ_FIXED != 0
c9218b16
RK
1514 default 100 if HZ_100
1515 default 200 if HZ_200
1516 default 250 if HZ_250
1517 default 300 if HZ_300
1518 default 500 if HZ_500
1519 default 1000
1520
1521config SCHED_HRTICK
1522 def_bool HIGH_RES_TIMERS
f8065813 1523
16c79651 1524config THUMB2_KERNEL
bc7dea00 1525 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
4477ca45 1526 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
bc7dea00 1527 default y if CPU_THUMBONLY
16c79651 1528 select ARM_ASM_UNIFIED
89bace65 1529 select ARM_UNWIND
16c79651
CM
1530 help
1531 By enabling this option, the kernel will be compiled in
1532 Thumb-2 mode. A compiler/assembler that understand the unified
1533 ARM-Thumb syntax is needed.
1534
1535 If unsure, say N.
1536
6f685c5c
DM
1537config THUMB2_AVOID_R_ARM_THM_JUMP11
1538 bool "Work around buggy Thumb-2 short branch relocations in gas"
1539 depends on THUMB2_KERNEL && MODULES
1540 default y
1541 help
1542 Various binutils versions can resolve Thumb-2 branches to
1543 locally-defined, preemptible global symbols as short-range "b.n"
1544 branch instructions.
1545
1546 This is a problem, because there's no guarantee the final
1547 destination of the symbol, or any candidate locations for a
1548 trampoline, are within range of the branch. For this reason, the
1549 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1550 relocation in modules at all, and it makes little sense to add
1551 support.
1552
1553 The symptom is that the kernel fails with an "unsupported
1554 relocation" error when loading some modules.
1555
1556 Until fixed tools are available, passing
1557 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1558 code which hits this problem, at the cost of a bit of extra runtime
1559 stack usage in some cases.
1560
1561 The problem is described in more detail at:
1562 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1563
1564 Only Thumb-2 kernels are affected.
1565
1566 Unless you are sure your tools don't have this problem, say Y.
1567
0becb088
CM
1568config ARM_ASM_UNIFIED
1569 bool
1570
42f25bdd
NP
1571config ARM_PATCH_IDIV
1572 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1573 depends on CPU_32v7 && !XIP_KERNEL
1574 default y
1575 help
1576 The ARM compiler inserts calls to __aeabi_idiv() and
1577 __aeabi_uidiv() when it needs to perform division on signed
1578 and unsigned integers. Some v7 CPUs have support for the sdiv
1579 and udiv instructions that can be used to implement those
1580 functions.
1581
1582 Enabling this option allows the kernel to modify itself to
1583 replace the first two instructions of these library functions
1584 with the sdiv or udiv plus "bx lr" instructions when the CPU
1585 it is running on supports them. Typically this will be faster
1586 and less power intensive than running the original library
1587 code to do integer division.
1588
704bdda0 1589config AEABI
ebdb2e36
ND
1590 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1591 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1592 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
704bdda0
NP
1593 help
1594 This option allows for the kernel to be compiled using the latest
1595 ARM ABI (aka EABI). This is only useful if you are using a user
1596 space environment that is also compiled with EABI.
1597
1598 Since there are major incompatibilities between the legacy ABI and
1599 EABI, especially with regard to structure member alignment, this
1600 option also changes the kernel syscall calling convention to
1601 disambiguate both ABIs and allow for backward compatibility support
1602 (selected with CONFIG_OABI_COMPAT).
1603
1604 To use this you need GCC version 4.0.0 or later.
1605
6c90c872 1606config OABI_COMPAT
a73a3ff1 1607 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
d6f94fa0 1608 depends on AEABI && !THUMB2_KERNEL
6c90c872
NP
1609 help
1610 This option preserves the old syscall interface along with the
1611 new (ARM EABI) one. It also provides a compatibility layer to
1612 intercept syscalls that have structure arguments which layout
1613 in memory differs between the legacy ABI and the new ARM EABI
1614 (only for non "thumb" binaries). This option adds a tiny
1615 overhead to all syscalls and produces a slightly larger kernel.
91702175
KC
1616
1617 The seccomp filter system will not be available when this is
1618 selected, since there is no way yet to sensibly distinguish
1619 between calling conventions during filtering.
1620
6c90c872
NP
1621 If you know you'll be using only pure EABI user space then you
1622 can say N here. If this option is not selected and you attempt
1623 to execute a legacy ABI binary then the result will be
1624 UNPREDICTABLE (in fact it can be predicted that it won't work
b02f8467 1625 at all). If in doubt say N.
6c90c872 1626
eb33575c 1627config ARCH_HAS_HOLES_MEMORYMODEL
e80d6a24 1628 bool
e80d6a24 1629
05944d74
RK
1630config ARCH_SPARSEMEM_ENABLE
1631 bool
1632
07a2f737
RK
1633config ARCH_SPARSEMEM_DEFAULT
1634 def_bool ARCH_SPARSEMEM_ENABLE
1635
05944d74 1636config ARCH_SELECT_MEMORY_MODEL
be370302 1637 def_bool ARCH_SPARSEMEM_ENABLE
c80d79d7 1638
7b7bf499
WD
1639config HAVE_ARCH_PFN_VALID
1640 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1641
e585513b 1642config HAVE_GENERIC_GUP
b8cd51af
SC
1643 def_bool y
1644 depends on ARM_LPAE
1645
053a96ca 1646config HIGHMEM
e8db89a2
RK
1647 bool "High Memory Support"
1648 depends on MMU
053a96ca
NP
1649 help
1650 The address space of ARM processors is only 4 Gigabytes large
1651 and it has to accommodate user address space, kernel address
1652 space as well as some memory mapped IO. That means that, if you
1653 have a large amount of physical memory and/or IO, not all of the
1654 memory can be "permanently mapped" by the kernel. The physical
1655 memory that is not permanently mapped is called "high memory".
1656
1657 Depending on the selected kernel/user memory split, minimum
1658 vmalloc space and actual amount of RAM, you may not need this
1659 option which should result in a slightly faster kernel.
1660
1661 If unsure, say n.
1662
65cec8e3 1663config HIGHPTE
9a431bd5 1664 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
65cec8e3 1665 depends on HIGHMEM
9a431bd5 1666 default y
b4d103d1
RK
1667 help
1668 The VM uses one page of physical memory for each page table.
1669 For systems with a lot of processes, this can use a lot of
1670 precious low memory, eventually leading to low memory being
1671 consumed by page tables. Setting this option will allow
1672 user-space 2nd level page tables to reside in high memory.
65cec8e3 1673
a5e090ac
RK
1674config CPU_SW_DOMAIN_PAN
1675 bool "Enable use of CPU domains to implement privileged no-access"
1676 depends on MMU && !ARM_LPAE
1b8873a0
JI
1677 default y
1678 help
a5e090ac
RK
1679 Increase kernel security by ensuring that normal kernel accesses
1680 are unable to access userspace addresses. This can help prevent
1681 use-after-free bugs becoming an exploitable privilege escalation
1682 by ensuring that magic values (such as LIST_POISON) will always
1683 fault when dereferenced.
1684
1685 CPUs with low-vector mappings use a best-efforts implementation.
1686 Their lower 1MB needs to remain accessible for the vectors, but
1687 the remainder of userspace will become appropriately inaccessible.
65cec8e3 1688
1b8873a0 1689config HW_PERF_EVENTS
fa8ad788
MR
1690 def_bool y
1691 depends on ARM_PMU
1b8873a0 1692
1355e2a6
CM
1693config SYS_SUPPORTS_HUGETLBFS
1694 def_bool y
1695 depends on ARM_LPAE
1696
8d962507
CM
1697config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1698 def_bool y
1699 depends on ARM_LPAE
1700
4bfab203
SC
1701config ARCH_WANT_GENERAL_HUGETLB
1702 def_bool y
1703
7d485f64
AB
1704config ARM_MODULE_PLTS
1705 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1706 depends on MODULES
1707 help
1708 Allocate PLTs when loading modules so that jumps and calls whose
1709 targets are too far away for their relative offsets to be encoded
1710 in the instructions themselves can be bounced via veneers in the
1711 module's PLT. This allows modules to be allocated in the generic
1712 vmalloc area after the dedicated module memory area has been
1713 exhausted. The modules will use slightly more memory, but after
1714 rounding up to page size, the actual memory footprint is usually
1715 the same.
1716
1717 Say y if you are getting out of memory errors while loading modules
1718
3f22ab27
DH
1719source "mm/Kconfig"
1720
c1b2d970 1721config FORCE_MAX_ZONEORDER
36d6c928 1722 int "Maximum zone order"
898f08e1 1723 default "12" if SOC_AM33XX
6d85e2b0 1724 default "9" if SA1111 || ARCH_EFM32
c1b2d970
MD
1725 default "11"
1726 help
1727 The kernel memory allocator divides physically contiguous memory
1728 blocks into "zones", where each zone is a power of two number of
1729 pages. This option selects the largest power of two that the kernel
1730 keeps in the memory allocator. If you need to allocate very large
1731 blocks of physically contiguous memory, then you may need to
1732 increase this value.
1733
1734 This config option is actually maximum order plus one. For example,
1735 a value of 11 means that the largest free memory block is 2^10 pages.
1736
1da177e4
LT
1737config ALIGNMENT_TRAP
1738 bool
f12d0d7c 1739 depends on CPU_CP15_MMU
1da177e4 1740 default y if !ARCH_EBSA110
e119bfff 1741 select HAVE_PROC_CPU if PROC_FS
1da177e4 1742 help
84eb8d06 1743 ARM processors cannot fetch/store information which is not
1da177e4
LT
1744 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1745 address divisible by 4. On 32-bit ARM processors, these non-aligned
1746 fetch/store instructions will be emulated in software if you say
1747 here, which has a severe performance impact. This is necessary for
1748 correct operation of some network protocols. With an IP-only
1749 configuration it is safe to say N, otherwise say Y.
1750
39ec58f3 1751config UACCESS_WITH_MEMCPY
38ef2ad5
LW
1752 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1753 depends on MMU
39ec58f3
LB
1754 default y if CPU_FEROCEON
1755 help
1756 Implement faster copy_to_user and clear_user methods for CPU
1757 cores where a 8-word STM instruction give significantly higher
1758 memory write throughput than a sequence of individual 32bit stores.
1759
1760 A possible side effect is a slight increase in scheduling latency
1761 between threads sharing the same address space if they invoke
1762 such copy operations with large buffers.
1763
1764 However, if the CPU data cache is using a write-allocate mode,
1765 this option is unlikely to provide any performance gain.
1766
70c70d97
NP
1767config SECCOMP
1768 bool
1769 prompt "Enable seccomp to safely compute untrusted bytecode"
1770 ---help---
1771 This kernel feature is useful for number crunching applications
1772 that may need to compute untrusted bytecode during their
1773 execution. By using pipes or other transports made available to
1774 the process as file descriptors supporting the read/write
1775 syscalls, it's possible to isolate those applications in
1776 their own address space using seccomp. Once seccomp is
1777 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1778 and the task is only allowed to execute a few safe syscalls
1779 defined by each seccomp mode.
1780
06e6295b
SS
1781config SWIOTLB
1782 def_bool y
1783
1784config IOMMU_HELPER
1785 def_bool SWIOTLB
1786
02c2433b
SS
1787config PARAVIRT
1788 bool "Enable paravirtualization code"
1789 help
1790 This changes the kernel so it can modify itself when it is run
1791 under a hypervisor, potentially improving performance significantly
1792 over full virtualization.
1793
1794config PARAVIRT_TIME_ACCOUNTING
1795 bool "Paravirtual steal time accounting"
1796 select PARAVIRT
1797 default n
1798 help
1799 Select this option to enable fine granularity task steal time
1800 accounting. Time spent executing other tasks in parallel with
1801 the current vCPU is discounted from the vCPU power. To account for
1802 that, there can be a small performance impact.
1803
1804 If in doubt, say N here.
1805
eff8d644
SS
1806config XEN_DOM0
1807 def_bool y
1808 depends on XEN
1809
1810config XEN
c2ba1f7d 1811 bool "Xen guest support on ARM"
85323a99 1812 depends on ARM && AEABI && OF
f880b67d 1813 depends on CPU_V7 && !CPU_V6
85323a99 1814 depends on !GENERIC_ATOMIC64
7693decc 1815 depends on MMU
51aaf81f 1816 select ARCH_DMA_ADDR_T_64BIT
17b7ab80 1817 select ARM_PSCI
83862ccf 1818 select SWIOTLB_XEN
02c2433b 1819 select PARAVIRT
eff8d644
SS
1820 help
1821 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1822
1da177e4
LT
1823endmenu
1824
1825menu "Boot options"
1826
9eb8f674
GL
1827config USE_OF
1828 bool "Flattened Device Tree support"
b1b3f49c 1829 select IRQ_DOMAIN
9eb8f674 1830 select OF
9eb8f674
GL
1831 help
1832 Include support for flattened device tree machine descriptions.
1833
bd51e2f5
NP
1834config ATAGS
1835 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1836 default y
1837 help
1838 This is the traditional way of passing data to the kernel at boot
1839 time. If you are solely relying on the flattened device tree (or
1840 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1841 to remove ATAGS support from your kernel binary. If unsure,
1842 leave this to y.
1843
1844config DEPRECATED_PARAM_STRUCT
1845 bool "Provide old way to pass kernel parameters"
1846 depends on ATAGS
1847 help
1848 This was deprecated in 2001 and announced to live on for 5 years.
1849 Some old boot loaders still use this way.
1850
1da177e4
LT
1851# Compressed boot loader in ROM. Yes, we really want to ask about
1852# TEXT and BSS so we preserve their values in the config files.
1853config ZBOOT_ROM_TEXT
1854 hex "Compressed ROM boot loader base address"
1855 default "0"
1856 help
1857 The physical address at which the ROM-able zImage is to be
1858 placed in the target. Platforms which normally make use of
1859 ROM-able zImage formats normally set this to a suitable
1860 value in their defconfig file.
1861
1862 If ZBOOT_ROM is not enabled, this has no effect.
1863
1864config ZBOOT_ROM_BSS
1865 hex "Compressed ROM boot loader BSS address"
1866 default "0"
1867 help
f8c440b2
DF
1868 The base address of an area of read/write memory in the target
1869 for the ROM-able zImage which must be available while the
1870 decompressor is running. It must be large enough to hold the
1871 entire decompressed kernel plus an additional 128 KiB.
1872 Platforms which normally make use of ROM-able zImage formats
1873 normally set this to a suitable value in their defconfig file.
1da177e4
LT
1874
1875 If ZBOOT_ROM is not enabled, this has no effect.
1876
1877config ZBOOT_ROM
1878 bool "Compressed boot loader in ROM/flash"
1879 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
10968131 1880 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1da177e4
LT
1881 help
1882 Say Y here if you intend to execute your compressed kernel image
1883 (zImage) directly from ROM or flash. If unsure, say N.
1884
e2a6a3aa
JB
1885config ARM_APPENDED_DTB
1886 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
10968131 1887 depends on OF
e2a6a3aa
JB
1888 help
1889 With this option, the boot code will look for a device tree binary
1890 (DTB) appended to zImage
1891 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1892
1893 This is meant as a backward compatibility convenience for those
1894 systems with a bootloader that can't be upgraded to accommodate
1895 the documented boot protocol using a device tree.
1896
1897 Beware that there is very little in terms of protection against
1898 this option being confused by leftover garbage in memory that might
1899 look like a DTB header after a reboot if no actual DTB is appended
1900 to zImage. Do not leave this option active in a production kernel
1901 if you don't intend to always append a DTB. Proper passing of the
1902 location into r2 of a bootloader provided DTB is always preferable
1903 to this option.
1904
b90b9a38
NP
1905config ARM_ATAG_DTB_COMPAT
1906 bool "Supplement the appended DTB with traditional ATAG information"
1907 depends on ARM_APPENDED_DTB
1908 help
1909 Some old bootloaders can't be updated to a DTB capable one, yet
1910 they provide ATAGs with memory configuration, the ramdisk address,
1911 the kernel cmdline string, etc. Such information is dynamically
1912 provided by the bootloader and can't always be stored in a static
1913 DTB. To allow a device tree enabled kernel to be used with such
1914 bootloaders, this option allows zImage to extract the information
1915 from the ATAG list and store it at run time into the appended DTB.
1916
d0f34a11
GR
1917choice
1918 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1919 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1920
1921config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1922 bool "Use bootloader kernel arguments if available"
1923 help
1924 Uses the command-line options passed by the boot loader instead of
1925 the device tree bootargs property. If the boot loader doesn't provide
1926 any, the device tree bootargs property will be used.
1927
1928config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1929 bool "Extend with bootloader kernel arguments"
1930 help
1931 The command-line arguments provided by the boot loader will be
1932 appended to the the device tree bootargs property.
1933
1934endchoice
1935
1da177e4
LT
1936config CMDLINE
1937 string "Default kernel command string"
1938 default ""
1939 help
1940 On some architectures (EBSA110 and CATS), there is currently no way
1941 for the boot loader to pass arguments to the kernel. For these
1942 architectures, you should supply some command-line options at build
1943 time by entering them here. As a minimum, you should specify the
1944 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1945
4394c124
VB
1946choice
1947 prompt "Kernel command line type" if CMDLINE != ""
1948 default CMDLINE_FROM_BOOTLOADER
bd51e2f5 1949 depends on ATAGS
4394c124
VB
1950
1951config CMDLINE_FROM_BOOTLOADER
1952 bool "Use bootloader kernel arguments if available"
1953 help
1954 Uses the command-line options passed by the boot loader. If
1955 the boot loader doesn't provide any, the default kernel command
1956 string provided in CMDLINE will be used.
1957
1958config CMDLINE_EXTEND
1959 bool "Extend bootloader kernel arguments"
1960 help
1961 The command-line arguments provided by the boot loader will be
1962 appended to the default kernel command string.
1963
92d2040d
AH
1964config CMDLINE_FORCE
1965 bool "Always use the default kernel command string"
92d2040d
AH
1966 help
1967 Always use the default kernel command string, even if the boot
1968 loader passes other arguments to the kernel.
1969 This is useful if you cannot or don't want to change the
1970 command-line options your boot loader passes to the kernel.
4394c124 1971endchoice
92d2040d 1972
1da177e4
LT
1973config XIP_KERNEL
1974 bool "Kernel Execute-In-Place from ROM"
10968131 1975 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1da177e4
LT
1976 help
1977 Execute-In-Place allows the kernel to run from non-volatile storage
1978 directly addressable by the CPU, such as NOR flash. This saves RAM
1979 space since the text section of the kernel is not loaded from flash
1980 to RAM. Read-write sections, such as the data section and stack,
1981 are still copied to RAM. The XIP kernel is not compressed since
1982 it has to run directly from flash, so it will take more space to
1983 store it. The flash address used to link the kernel object files,
1984 and for storing it, is configuration dependent. Therefore, if you
1985 say Y here, you must know the proper physical address where to
1986 store the kernel image depending on your own flash memory usage.
1987
1988 Also note that the make target becomes "make xipImage" rather than
1989 "make zImage" or "make Image". The final kernel binary to put in
1990 ROM memory will be arch/arm/boot/xipImage.
1991
1992 If unsure, say N.
1993
1994config XIP_PHYS_ADDR
1995 hex "XIP Kernel Physical Location"
1996 depends on XIP_KERNEL
1997 default "0x00080000"
1998 help
1999 This is the physical address in your flash memory the kernel will
2000 be linked for and stored to. This address is dependent on your
2001 own flash usage.
2002
ca8b5d97
NP
2003config XIP_DEFLATED_DATA
2004 bool "Store kernel .data section compressed in ROM"
2005 depends on XIP_KERNEL
2006 select ZLIB_INFLATE
2007 help
2008 Before the kernel is actually executed, its .data section has to be
2009 copied to RAM from ROM. This option allows for storing that data
2010 in compressed form and decompressed to RAM rather than merely being
2011 copied, saving some precious ROM space. A possible drawback is a
2012 slightly longer boot delay.
2013
c587e4a6
RP
2014config KEXEC
2015 bool "Kexec system call (EXPERIMENTAL)"
19ab428f 2016 depends on (!SMP || PM_SLEEP_SMP)
cb1293e2 2017 depends on !CPU_V7M
2965faa5 2018 select KEXEC_CORE
c587e4a6
RP
2019 help
2020 kexec is a system call that implements the ability to shutdown your
2021 current kernel, and to start another kernel. It is like a reboot
01dd2fbf 2022 but it is independent of the system firmware. And like a reboot
c587e4a6
RP
2023 you can start any kernel with it, not just Linux.
2024
2025 It is an ongoing process to be certain the hardware in a machine
2026 is properly shutdown, so do not be surprised if this code does not
bf220695 2027 initially work for you.
c587e4a6 2028
4cd9d6f7
RP
2029config ATAGS_PROC
2030 bool "Export atags in procfs"
bd51e2f5 2031 depends on ATAGS && KEXEC
b98d7291 2032 default y
4cd9d6f7
RP
2033 help
2034 Should the atags used to boot the kernel be exported in an "atags"
2035 file in procfs. Useful with kexec.
2036
cb5d39b3
MW
2037config CRASH_DUMP
2038 bool "Build kdump crash kernel (EXPERIMENTAL)"
cb5d39b3
MW
2039 help
2040 Generate crash dump after being started by kexec. This should
2041 be normally only set in special crash dump kernels which are
2042 loaded in the main kernel with kexec-tools into a specially
2043 reserved region and then later executed after a crash by
2044 kdump/kexec. The crash dump kernel must be compiled to a
2045 memory address not used by the main kernel
2046
2047 For more details see Documentation/kdump/kdump.txt
2048
e69edc79
EM
2049config AUTO_ZRELADDR
2050 bool "Auto calculation of the decompressed kernel image address"
e69edc79
EM
2051 help
2052 ZRELADDR is the physical address where the decompressed kernel
2053 image will be placed. If AUTO_ZRELADDR is selected, the address
2054 will be determined at run-time by masking the current IP with
2055 0xf8000000. This assumes the zImage being placed in the first 128MB
2056 from start of memory.
2057
81a0bc39
RF
2058config EFI_STUB
2059 bool
2060
2061config EFI
2062 bool "UEFI runtime support"
2063 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2064 select UCS2_STRING
2065 select EFI_PARAMS_FROM_FDT
2066 select EFI_STUB
2067 select EFI_ARMSTUB
2068 select EFI_RUNTIME_WRAPPERS
2069 ---help---
2070 This option provides support for runtime services provided
2071 by UEFI firmware (such as non-volatile variables, realtime
2072 clock, and platform reset). A UEFI stub is also provided to
2073 allow the kernel to be booted as an EFI application. This
2074 is only useful for kernels that may run on systems that have
2075 UEFI firmware.
2076
bb817bef
AB
2077config DMI
2078 bool "Enable support for SMBIOS (DMI) tables"
2079 depends on EFI
2080 default y
2081 help
2082 This enables SMBIOS/DMI feature for systems.
2083
2084 This option is only useful on systems that have UEFI firmware.
2085 However, even with this option, the resultant kernel should
2086 continue to boot on existing non-UEFI platforms.
2087
2088 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2089 i.e., the the practice of identifying the platform via DMI to
2090 decide whether certain workarounds for buggy hardware and/or
2091 firmware need to be enabled. This would require the DMI subsystem
2092 to be enabled much earlier than we do on ARM, which is non-trivial.
2093
1da177e4
LT
2094endmenu
2095
ac9d7efc 2096menu "CPU Power Management"
1da177e4 2097
1da177e4 2098source "drivers/cpufreq/Kconfig"
1da177e4 2099
ac9d7efc
RK
2100source "drivers/cpuidle/Kconfig"
2101
2102endmenu
2103
1da177e4
LT
2104menu "Floating point emulation"
2105
2106comment "At least one emulation must be selected"
2107
2108config FPE_NWFPE
2109 bool "NWFPE math emulation"
593c252a 2110 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1da177e4
LT
2111 ---help---
2112 Say Y to include the NWFPE floating point emulator in the kernel.
2113 This is necessary to run most binaries. Linux does not currently
2114 support floating point hardware so you need to say Y here even if
2115 your machine has an FPA or floating point co-processor podule.
2116
2117 You may say N here if you are going to load the Acorn FPEmulator
2118 early in the bootup.
2119
2120config FPE_NWFPE_XP
2121 bool "Support extended precision"
bedf142b 2122 depends on FPE_NWFPE
1da177e4
LT
2123 help
2124 Say Y to include 80-bit support in the kernel floating-point
2125 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2126 Note that gcc does not generate 80-bit operations by default,
2127 so in most cases this option only enlarges the size of the
2128 floating point emulator without any good reason.
2129
2130 You almost surely want to say N here.
2131
2132config FPE_FASTFPE
2133 bool "FastFPE math emulation (EXPERIMENTAL)"
d6f94fa0 2134 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1da177e4
LT
2135 ---help---
2136 Say Y here to include the FAST floating point emulator in the kernel.
2137 This is an experimental much faster emulator which now also has full
2138 precision for the mantissa. It does not support any exceptions.
2139 It is very simple, and approximately 3-6 times faster than NWFPE.
2140
2141 It should be sufficient for most programs. It may be not suitable
2142 for scientific calculations, but you have to check this for yourself.
2143 If you do not feel you need a faster FP emulation you should better
2144 choose NWFPE.
2145
2146config VFP
2147 bool "VFP-format floating point maths"
e399b1a4 2148 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1da177e4
LT
2149 help
2150 Say Y to include VFP support code in the kernel. This is needed
2151 if your hardware includes a VFP unit.
2152
2153 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2154 release notes and additional status information.
2155
2156 Say N if your target does not have VFP hardware.
2157
25ebee02
CM
2158config VFPv3
2159 bool
2160 depends on VFP
2161 default y if CPU_V7
2162
b5872db4
CM
2163config NEON
2164 bool "Advanced SIMD (NEON) Extension support"
2165 depends on VFPv3 && CPU_V7
2166 help
2167 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2168 Extension.
2169
73c132c1
AB
2170config KERNEL_MODE_NEON
2171 bool "Support for NEON in kernel mode"
c4a30c3b 2172 depends on NEON && AEABI
73c132c1
AB
2173 help
2174 Say Y to include support for NEON in kernel mode.
2175
1da177e4
LT
2176endmenu
2177
2178menu "Userspace binary formats"
2179
2180source "fs/Kconfig.binfmt"
2181
1da177e4
LT
2182endmenu
2183
2184menu "Power management options"
2185
eceab4ac 2186source "kernel/power/Kconfig"
1da177e4 2187
f4cb5700 2188config ARCH_SUSPEND_POSSIBLE
19a0519d 2189 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
f0d75153 2190 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
f4cb5700
JB
2191 def_bool y
2192
15e0d9e3 2193config ARM_CPU_SUSPEND
8b6f2499 2194 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1b9bdf5c 2195 depends on ARCH_SUSPEND_POSSIBLE
15e0d9e3 2196
603fb42a
SC
2197config ARCH_HIBERNATION_POSSIBLE
2198 bool
2199 depends on MMU
2200 default y if ARCH_SUSPEND_POSSIBLE
2201
1da177e4
LT
2202endmenu
2203
d5950b43
SR
2204source "net/Kconfig"
2205
ac25150f 2206source "drivers/Kconfig"
1da177e4 2207
916f743d 2208source "drivers/firmware/Kconfig"
0d34a427 2209source "ubuntu/Kconfig"
916f743d 2210
1da177e4
LT
2211source "fs/Kconfig"
2212
1da177e4
LT
2213source "arch/arm/Kconfig.debug"
2214
2215source "security/Kconfig"
2216
2217source "crypto/Kconfig"
652ccae5
AB
2218if CRYPTO
2219source "arch/arm/crypto/Kconfig"
2220endif
1da177e4
LT
2221
2222source "lib/Kconfig"
749cf76c
CD
2223
2224source "arch/arm/kvm/Kconfig"