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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | config ARM |
2 | bool | |
3 | default y | |
1d8f51d4 | 4 | select ARCH_CLOCKSOURCE_DATA |
e377cd82 | 5 | select ARCH_HAS_DEBUG_VIRTUAL |
21266be9 | 6 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
2b68f6ca | 7 | select ARCH_HAS_ELF_RANDOMIZE |
d2852a22 | 8 | select ARCH_HAS_SET_MEMORY |
ad21fc4f LA |
9 | select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL |
10 | select ARCH_HAS_STRICT_MODULE_RWX if MMU | |
3d06770e | 11 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
171b3f0d | 12 | select ARCH_HAVE_CUSTOM_GPIO_H |
957e3fac | 13 | select ARCH_HAS_GCOV_PROFILE_ALL |
d7018848 | 14 | select ARCH_MIGHT_HAVE_PC_PARPORT |
ad21fc4f LA |
15 | select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX |
16 | select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 | |
4badad35 | 17 | select ARCH_SUPPORTS_ATOMIC_RMW |
017f161a | 18 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 19 | select ARCH_USE_CMPXCHG_LOCKREF |
b1b3f49c | 20 | select ARCH_WANT_IPC_PARSE_VERSION |
ee951c63 | 21 | select BUILDTIME_EXTABLE_SORT if MMU |
171b3f0d | 22 | select CLONE_BACKWARDS |
b1b3f49c | 23 | select CPU_PM if (SUSPEND || CPU_IDLE) |
dce5c9e3 | 24 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
1c51c429 | 25 | select DMA_NOOP_OPS if !MMU |
b01aec9b BP |
26 | select EDAC_SUPPORT |
27 | select EDAC_ATOMIC_SCRUB | |
36d0fd21 | 28 | select GENERIC_ALLOCATOR |
2ef7a295 | 29 | select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY |
4477ca45 | 30 | select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) |
b1b3f49c | 31 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
ea2d9a96 | 32 | select GENERIC_CPU_AUTOPROBE |
2937367b | 33 | select GENERIC_EARLY_IOREMAP |
171b3f0d | 34 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
35 | select GENERIC_IRQ_PROBE |
36 | select GENERIC_IRQ_SHOW | |
7c07005e | 37 | select GENERIC_IRQ_SHOW_LEVEL |
b1b3f49c | 38 | select GENERIC_PCI_IOMAP |
38ff87f7 | 39 | select GENERIC_SCHED_CLOCK |
b1b3f49c RK |
40 | select GENERIC_SMP_IDLE_THREAD |
41 | select GENERIC_STRNCPY_FROM_USER | |
42 | select GENERIC_STRNLEN_USER | |
a71b092a | 43 | select HANDLE_DOMAIN_IRQ |
b1b3f49c | 44 | select HARDIRQS_SW_RESEND |
7a017721 | 45 | select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) |
0b7857db | 46 | select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 |
437682ee AB |
47 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
48 | select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU | |
e0c25d95 | 49 | select HAVE_ARCH_MMAP_RND_BITS if MMU |
91702175 | 50 | select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) |
0693bf68 | 51 | select HAVE_ARCH_TRACEHOOK |
b329f95d | 52 | select HAVE_ARM_SMCCC if CPU_V7 |
6077776b | 53 | select HAVE_CBPF_JIT |
51aaf81f | 54 | select HAVE_CC_STACKPROTECTOR |
171b3f0d | 55 | select HAVE_CONTEXT_TRACKING |
b1b3f49c RK |
56 | select HAVE_C_RECORDMCOUNT |
57 | select HAVE_DEBUG_KMEMLEAK | |
58 | select HAVE_DMA_API_DEBUG | |
b1b3f49c | 59 | select HAVE_DMA_CONTIGUOUS if MMU |
437682ee | 60 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU |
620176f3 | 61 | select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE |
dce5c9e3 | 62 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
5f56a5df | 63 | select HAVE_EXIT_THREAD |
b1b3f49c | 64 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
0e341af8 | 65 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
b1b3f49c | 66 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
6b90bd4b | 67 | select HAVE_GCC_PLUGINS |
1fe53268 | 68 | select HAVE_GENERIC_DMA_COHERENT |
b1b3f49c RK |
69 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) |
70 | select HAVE_IDE if PCI || ISA || PCMCIA | |
87c46b6c | 71 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 72 | select HAVE_KERNEL_GZIP |
f9b493ac | 73 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 74 | select HAVE_KERNEL_LZMA |
b1b3f49c | 75 | select HAVE_KERNEL_LZO |
a7f464f3 | 76 | select HAVE_KERNEL_XZ |
cb1293e2 | 77 | select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M |
b1b3f49c RK |
78 | select HAVE_KRETPROBES if (HAVE_KPROBES) |
79 | select HAVE_MEMBLOCK | |
7d485f64 | 80 | select HAVE_MOD_ARCH_SPECIFIC |
42a0bb3f | 81 | select HAVE_NMI |
b1b3f49c | 82 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) |
0dc016db | 83 | select HAVE_OPTPROBES if !THUMB2_KERNEL |
7ada189f | 84 | select HAVE_PERF_EVENTS |
49863894 WD |
85 | select HAVE_PERF_REGS |
86 | select HAVE_PERF_USER_STACK_DUMP | |
a0ad5496 | 87 | select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) |
e513f8bf | 88 | select HAVE_REGS_AND_STACK_ACCESS_API |
b1b3f49c | 89 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 90 | select HAVE_UID16 |
31c1fc81 | 91 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
da0ec6f7 | 92 | select IRQ_FORCED_THREADING |
171b3f0d | 93 | select MODULES_USE_ELF_REL |
84f452b1 | 94 | select NO_BOOTMEM |
aa7d5f18 AB |
95 | select OF_EARLY_FLATTREE if OF |
96 | select OF_RESERVED_MEM if OF | |
171b3f0d RK |
97 | select OLD_SIGACTION |
98 | select OLD_SIGSUSPEND3 | |
b1b3f49c RK |
99 | select PERF_USE_VMALLOC |
100 | select RTC_LIB | |
101 | select SYS_SUPPORTS_APM_EMULATION | |
171b3f0d RK |
102 | # Above selects are sorted alphabetically; please add new ones |
103 | # according to that. Thanks. | |
1da177e4 LT |
104 | help |
105 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 106 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 107 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 108 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
109 | Europe. There is an ARM Linux project with a web page at |
110 | <http://www.arm.linux.org.uk/>. | |
111 | ||
74facffe | 112 | config ARM_HAS_SG_CHAIN |
308c09f1 | 113 | select ARCH_HAS_SG_CHAIN |
74facffe RK |
114 | bool |
115 | ||
4ce63fcd MS |
116 | config NEED_SG_DMA_LENGTH |
117 | bool | |
118 | ||
119 | config ARM_DMA_USE_IOMMU | |
4ce63fcd | 120 | bool |
b1b3f49c RK |
121 | select ARM_HAS_SG_CHAIN |
122 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 123 | |
60460abf SWK |
124 | if ARM_DMA_USE_IOMMU |
125 | ||
126 | config ARM_DMA_IOMMU_ALIGNMENT | |
127 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
128 | range 4 9 | |
129 | default 8 | |
130 | help | |
131 | DMA mapping framework by default aligns all buffers to the smallest | |
132 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
133 | size. This works well for buffers up to a few hundreds kilobytes, but | |
134 | for larger buffers it just a waste of address space. Drivers which has | |
135 | relatively small addressing window (like 64Mib) might run out of | |
136 | virtual space with just a few allocations. | |
137 | ||
138 | With this parameter you can specify the maximum PAGE_SIZE order for | |
139 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
140 | specified order. The order is expressed as a power of two multiplied | |
141 | by the PAGE_SIZE. | |
142 | ||
143 | endif | |
144 | ||
0b05da72 HUK |
145 | config MIGHT_HAVE_PCI |
146 | bool | |
147 | ||
75e7153a RB |
148 | config SYS_SUPPORTS_APM_EMULATION |
149 | bool | |
150 | ||
bc581770 LW |
151 | config HAVE_TCM |
152 | bool | |
153 | select GENERIC_ALLOCATOR | |
154 | ||
e119bfff RK |
155 | config HAVE_PROC_CPU |
156 | bool | |
157 | ||
ce816fa8 | 158 | config NO_IOPORT_MAP |
5ea81769 | 159 | bool |
5ea81769 | 160 | |
1da177e4 LT |
161 | config EISA |
162 | bool | |
163 | ---help--- | |
164 | The Extended Industry Standard Architecture (EISA) bus was | |
165 | developed as an open alternative to the IBM MicroChannel bus. | |
166 | ||
167 | The EISA bus provided some of the features of the IBM MicroChannel | |
168 | bus while maintaining backward compatibility with cards made for | |
169 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
170 | 1995 when it was made obsolete by the PCI bus. | |
171 | ||
172 | Say Y here if you are building a kernel for an EISA-based machine. | |
173 | ||
174 | Otherwise, say N. | |
175 | ||
176 | config SBUS | |
177 | bool | |
178 | ||
f16fb1ec RK |
179 | config STACKTRACE_SUPPORT |
180 | bool | |
181 | default y | |
182 | ||
183 | config LOCKDEP_SUPPORT | |
184 | bool | |
185 | default y | |
186 | ||
7ad1bcb2 RK |
187 | config TRACE_IRQFLAGS_SUPPORT |
188 | bool | |
cb1293e2 | 189 | default !CPU_V7M |
7ad1bcb2 | 190 | |
1da177e4 LT |
191 | config RWSEM_XCHGADD_ALGORITHM |
192 | bool | |
8a87411b | 193 | default y |
1da177e4 | 194 | |
f0d1b0b3 DH |
195 | config ARCH_HAS_ILOG2_U32 |
196 | bool | |
f0d1b0b3 DH |
197 | |
198 | config ARCH_HAS_ILOG2_U64 | |
199 | bool | |
f0d1b0b3 | 200 | |
4a1b5733 EV |
201 | config ARCH_HAS_BANDGAP |
202 | bool | |
203 | ||
a5f4c561 SA |
204 | config FIX_EARLYCON_MEM |
205 | def_bool y if MMU | |
206 | ||
b89c3b16 AM |
207 | config GENERIC_HWEIGHT |
208 | bool | |
209 | default y | |
210 | ||
1da177e4 LT |
211 | config GENERIC_CALIBRATE_DELAY |
212 | bool | |
213 | default y | |
214 | ||
a08b6b79 AV |
215 | config ARCH_MAY_HAVE_PC_FDC |
216 | bool | |
217 | ||
5ac6da66 CL |
218 | config ZONE_DMA |
219 | bool | |
5ac6da66 | 220 | |
ccd7ab7f FT |
221 | config NEED_DMA_MAP_STATE |
222 | def_bool y | |
223 | ||
c7edc9e3 DL |
224 | config ARCH_SUPPORTS_UPROBES |
225 | def_bool y | |
226 | ||
58af4a24 RH |
227 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
228 | bool | |
229 | ||
1da177e4 LT |
230 | config GENERIC_ISA_DMA |
231 | bool | |
232 | ||
1da177e4 LT |
233 | config FIQ |
234 | bool | |
235 | ||
13a5045d RH |
236 | config NEED_RET_TO_USER |
237 | bool | |
238 | ||
034d2f5a AV |
239 | config ARCH_MTD_XIP |
240 | bool | |
241 | ||
c760fc19 HC |
242 | config VECTORS_BASE |
243 | hex | |
6afd6fae | 244 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR |
c760fc19 HC |
245 | default DRAM_BASE if REMAP_VECTORS_TO_RAM |
246 | default 0x00000000 | |
247 | help | |
19accfd3 RK |
248 | The base address of exception vectors. This must be two pages |
249 | in size. | |
c760fc19 | 250 | |
dc21af99 | 251 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
252 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
253 | default y | |
b511d75d | 254 | depends on !XIP_KERNEL && MMU |
dc21af99 | 255 | help |
111e9a5c RK |
256 | Patch phys-to-virt and virt-to-phys translation functions at |
257 | boot and module load time according to the position of the | |
258 | kernel in system memory. | |
dc21af99 | 259 | |
111e9a5c | 260 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 261 | of physical memory is at a 16MB boundary. |
dc21af99 | 262 | |
c1becedc RK |
263 | Only disable this option if you know that you do not require |
264 | this feature (eg, building a kernel for a single machine) and | |
265 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 266 | |
c334bc15 RH |
267 | config NEED_MACH_IO_H |
268 | bool | |
269 | help | |
270 | Select this when mach/io.h is required to provide special | |
271 | definitions for this platform. The need for mach/io.h should | |
272 | be avoided when possible. | |
273 | ||
0cdc8b92 | 274 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
275 | bool |
276 | help | |
0cdc8b92 NP |
277 | Select this when mach/memory.h is required to provide special |
278 | definitions for this platform. The need for mach/memory.h should | |
279 | be avoided when possible. | |
dc21af99 | 280 | |
1b9f95f8 | 281 | config PHYS_OFFSET |
974c0724 | 282 | hex "Physical address of main memory" if MMU |
c6f54a9b | 283 | depends on !ARM_PATCH_PHYS_VIRT |
974c0724 | 284 | default DRAM_BASE if !MMU |
c6f54a9b | 285 | default 0x00000000 if ARCH_EBSA110 || \ |
c6f54a9b UKK |
286 | ARCH_FOOTBRIDGE || \ |
287 | ARCH_INTEGRATOR || \ | |
288 | ARCH_IOP13XX || \ | |
289 | ARCH_KS8695 || \ | |
8f2c0062 | 290 | ARCH_REALVIEW |
c6f54a9b UKK |
291 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC |
292 | default 0x20000000 if ARCH_S5PV210 | |
b8824c9a | 293 | default 0xc0000000 if ARCH_SA1100 |
111e9a5c | 294 | help |
1b9f95f8 NP |
295 | Please provide the physical address corresponding to the |
296 | location of main memory in your system. | |
cada3c08 | 297 | |
87e040b6 SG |
298 | config GENERIC_BUG |
299 | def_bool y | |
300 | depends on BUG | |
301 | ||
1bcad26e KS |
302 | config PGTABLE_LEVELS |
303 | int | |
304 | default 3 if ARM_LPAE | |
305 | default 2 | |
306 | ||
1da177e4 LT |
307 | source "init/Kconfig" |
308 | ||
dc52ddc0 MH |
309 | source "kernel/Kconfig.freezer" |
310 | ||
1da177e4 LT |
311 | menu "System Type" |
312 | ||
3c427975 HC |
313 | config MMU |
314 | bool "MMU-based Paged Memory Management Support" | |
315 | default y | |
316 | help | |
317 | Select if you want MMU-based virtualised addressing space | |
318 | support by paged memory management. If unsure, say 'Y'. | |
319 | ||
e0c25d95 DC |
320 | config ARCH_MMAP_RND_BITS_MIN |
321 | default 8 | |
322 | ||
323 | config ARCH_MMAP_RND_BITS_MAX | |
324 | default 14 if PAGE_OFFSET=0x40000000 | |
325 | default 15 if PAGE_OFFSET=0x80000000 | |
326 | default 16 | |
327 | ||
ccf50e23 RK |
328 | # |
329 | # The "ARM system type" choice list is ordered alphabetically by option | |
330 | # text. Please add new entries in the option alphabetic order. | |
331 | # | |
1da177e4 LT |
332 | choice |
333 | prompt "ARM system type" | |
70722803 | 334 | default ARM_SINGLE_ARMV7M if !MMU |
1420b22b | 335 | default ARCH_MULTIPLATFORM if MMU |
1da177e4 | 336 | |
387798b3 RH |
337 | config ARCH_MULTIPLATFORM |
338 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 339 | depends on MMU |
42dc836d | 340 | select ARM_HAS_SG_CHAIN |
387798b3 RH |
341 | select ARM_PATCH_PHYS_VIRT |
342 | select AUTO_ZRELADDR | |
bb0eb050 | 343 | select TIMER_OF |
66314223 | 344 | select COMMON_CLK |
ddb902cc | 345 | select GENERIC_CLOCKEVENTS |
08d38beb | 346 | select MIGHT_HAVE_PCI |
387798b3 | 347 | select MULTI_IRQ_HANDLER |
e13688fe | 348 | select PCI_DOMAINS if PCI |
66314223 DN |
349 | select SPARSE_IRQ |
350 | select USE_OF | |
66314223 | 351 | |
9c77bc43 SA |
352 | config ARM_SINGLE_ARMV7M |
353 | bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" | |
354 | depends on !MMU | |
9c77bc43 | 355 | select ARM_NVIC |
499f1640 | 356 | select AUTO_ZRELADDR |
bb0eb050 | 357 | select TIMER_OF |
9c77bc43 SA |
358 | select COMMON_CLK |
359 | select CPU_V7M | |
360 | select GENERIC_CLOCKEVENTS | |
361 | select NO_IOPORT_MAP | |
362 | select SPARSE_IRQ | |
363 | select USE_OF | |
364 | ||
1da177e4 LT |
365 | config ARCH_EBSA110 |
366 | bool "EBSA-110" | |
b1b3f49c | 367 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 368 | select CPU_SA110 |
f7e68bbf | 369 | select ISA |
c334bc15 | 370 | select NEED_MACH_IO_H |
0cdc8b92 | 371 | select NEED_MACH_MEMORY_H |
ce816fa8 | 372 | select NO_IOPORT_MAP |
1da177e4 LT |
373 | help |
374 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 375 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
376 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
377 | parallel port. | |
378 | ||
e7736d47 LB |
379 | config ARCH_EP93XX |
380 | bool "EP93xx-based" | |
b1b3f49c | 381 | select ARCH_HAS_HOLES_MEMORYMODEL |
e7736d47 | 382 | select ARM_AMBA |
b8824c9a | 383 | select ARM_PATCH_PHYS_VIRT |
e7736d47 | 384 | select ARM_VIC |
b8824c9a | 385 | select AUTO_ZRELADDR |
6d803ba7 | 386 | select CLKDEV_LOOKUP |
000bc178 | 387 | select CLKSRC_MMIO |
b1b3f49c | 388 | select CPU_ARM920T |
000bc178 | 389 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 390 | select GPIOLIB |
e7736d47 LB |
391 | help |
392 | This enables support for the Cirrus EP93xx series of CPUs. | |
393 | ||
1da177e4 LT |
394 | config ARCH_FOOTBRIDGE |
395 | bool "FootBridge" | |
c750815e | 396 | select CPU_SA110 |
1da177e4 | 397 | select FOOTBRIDGE |
4e8d7637 | 398 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 399 | select HAVE_IDE |
8ef6e620 | 400 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 401 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
402 | help |
403 | Support for systems based on the DC21285 companion chip | |
404 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 405 | |
4af6fee1 DS |
406 | config ARCH_NETX |
407 | bool "Hilscher NetX based" | |
b1b3f49c | 408 | select ARM_VIC |
234b6ced | 409 | select CLKSRC_MMIO |
c750815e | 410 | select CPU_ARM926T |
2fcfe6b8 | 411 | select GENERIC_CLOCKEVENTS |
f999b8bd | 412 | help |
4af6fee1 DS |
413 | This enables support for systems based on the Hilscher NetX Soc |
414 | ||
3b938be6 RK |
415 | config ARCH_IOP13XX |
416 | bool "IOP13xx-based" | |
417 | depends on MMU | |
b1b3f49c | 418 | select CPU_XSC3 |
0cdc8b92 | 419 | select NEED_MACH_MEMORY_H |
13a5045d | 420 | select NEED_RET_TO_USER |
b1b3f49c RK |
421 | select PCI |
422 | select PLAT_IOP | |
423 | select VMSPLIT_1G | |
37ebbcff | 424 | select SPARSE_IRQ |
3b938be6 RK |
425 | help |
426 | Support for Intel's IOP13XX (XScale) family of processors. | |
427 | ||
3f7e5815 LB |
428 | config ARCH_IOP32X |
429 | bool "IOP32x-based" | |
a4f7e763 | 430 | depends on MMU |
c750815e | 431 | select CPU_XSCALE |
e9004f50 | 432 | select GPIO_IOP |
5c34a4e8 | 433 | select GPIOLIB |
13a5045d | 434 | select NEED_RET_TO_USER |
f7e68bbf | 435 | select PCI |
b1b3f49c | 436 | select PLAT_IOP |
f999b8bd | 437 | help |
3f7e5815 LB |
438 | Support for Intel's 80219 and IOP32X (XScale) family of |
439 | processors. | |
440 | ||
441 | config ARCH_IOP33X | |
442 | bool "IOP33x-based" | |
443 | depends on MMU | |
c750815e | 444 | select CPU_XSCALE |
e9004f50 | 445 | select GPIO_IOP |
5c34a4e8 | 446 | select GPIOLIB |
13a5045d | 447 | select NEED_RET_TO_USER |
3f7e5815 | 448 | select PCI |
b1b3f49c | 449 | select PLAT_IOP |
3f7e5815 LB |
450 | help |
451 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 452 | |
3b938be6 RK |
453 | config ARCH_IXP4XX |
454 | bool "IXP4xx-based" | |
a4f7e763 | 455 | depends on MMU |
58af4a24 | 456 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
51aaf81f | 457 | select ARCH_SUPPORTS_BIG_ENDIAN |
234b6ced | 458 | select CLKSRC_MMIO |
c750815e | 459 | select CPU_XSCALE |
b1b3f49c | 460 | select DMABOUNCE if PCI |
3b938be6 | 461 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 462 | select GPIOLIB |
0b05da72 | 463 | select MIGHT_HAVE_PCI |
c334bc15 | 464 | select NEED_MACH_IO_H |
9296d94d | 465 | select USB_EHCI_BIG_ENDIAN_DESC |
171b3f0d | 466 | select USB_EHCI_BIG_ENDIAN_MMIO |
c4713074 | 467 | help |
3b938be6 | 468 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 469 | |
edabd38e SB |
470 | config ARCH_DOVE |
471 | bool "Marvell Dove" | |
756b2531 | 472 | select CPU_PJ4 |
edabd38e | 473 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 474 | select GPIOLIB |
0f81bd43 | 475 | select MIGHT_HAVE_PCI |
b8cd337c | 476 | select MULTI_IRQ_HANDLER |
171b3f0d | 477 | select MVEBU_MBUS |
9139acd1 SH |
478 | select PINCTRL |
479 | select PINCTRL_DOVE | |
abcda1dc | 480 | select PLAT_ORION_LEGACY |
0bd86961 | 481 | select SPARSE_IRQ |
c5d431e8 | 482 | select PM_GENERIC_DOMAINS if PM |
788c9700 | 483 | help |
edabd38e | 484 | Support for the Marvell Dove SoC 88AP510 |
788c9700 RK |
485 | |
486 | config ARCH_KS8695 | |
487 | bool "Micrel/Kendin KS8695" | |
c7e783d6 | 488 | select CLKSRC_MMIO |
b1b3f49c | 489 | select CPU_ARM922T |
c7e783d6 | 490 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 491 | select GPIOLIB |
b1b3f49c | 492 | select NEED_MACH_MEMORY_H |
788c9700 RK |
493 | help |
494 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
495 | System-on-Chip devices. | |
496 | ||
788c9700 RK |
497 | config ARCH_W90X900 |
498 | bool "Nuvoton W90X900 CPU" | |
6d803ba7 | 499 | select CLKDEV_LOOKUP |
6fa5d5f7 | 500 | select CLKSRC_MMIO |
b1b3f49c | 501 | select CPU_ARM926T |
58b5369e | 502 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 503 | select GPIOLIB |
788c9700 | 504 | help |
a8bc4ead | 505 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
506 | At present, the w90x900 has been renamed nuc900, regarding | |
507 | the ARM series product line, you can login the following | |
508 | link address to know more. | |
509 | ||
510 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
511 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 512 | |
93e22567 RK |
513 | config ARCH_LPC32XX |
514 | bool "NXP LPC32XX" | |
93e22567 RK |
515 | select ARM_AMBA |
516 | select CLKDEV_LOOKUP | |
c227f127 VZ |
517 | select CLKSRC_LPC32XX |
518 | select COMMON_CLK | |
93e22567 RK |
519 | select CPU_ARM926T |
520 | select GENERIC_CLOCKEVENTS | |
5c34a4e8 | 521 | select GPIOLIB |
8cb17b5e VZ |
522 | select MULTI_IRQ_HANDLER |
523 | select SPARSE_IRQ | |
93e22567 RK |
524 | select USE_OF |
525 | help | |
526 | Support for the NXP LPC32XX family of processors | |
527 | ||
1da177e4 | 528 | config ARCH_PXA |
2c8086a5 | 529 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 530 | depends on MMU |
b1b3f49c | 531 | select ARCH_MTD_XIP |
b1b3f49c RK |
532 | select ARM_CPU_SUSPEND if PM |
533 | select AUTO_ZRELADDR | |
a1c0a6ad | 534 | select COMMON_CLK |
6d803ba7 | 535 | select CLKDEV_LOOKUP |
389d9b58 | 536 | select CLKSRC_PXA |
234b6ced | 537 | select CLKSRC_MMIO |
bb0eb050 | 538 | select TIMER_OF |
2f202861 | 539 | select CPU_XSCALE if !CPU_XSC3 |
981d0f39 | 540 | select GENERIC_CLOCKEVENTS |
157d2644 | 541 | select GPIO_PXA |
5c34a4e8 | 542 | select GPIOLIB |
d0ee9f40 | 543 | select HAVE_IDE |
d6cf30ca | 544 | select IRQ_DOMAIN |
b1b3f49c | 545 | select MULTI_IRQ_HANDLER |
b1b3f49c RK |
546 | select PLAT_PXA |
547 | select SPARSE_IRQ | |
f999b8bd | 548 | help |
2c8086a5 | 549 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 LT |
550 | |
551 | config ARCH_RPC | |
552 | bool "RiscPC" | |
868e87cc | 553 | depends on MMU |
1da177e4 | 554 | select ARCH_ACORN |
a08b6b79 | 555 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 556 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 557 | select ARCH_USES_GETTIMEOFFSET |
fa04e209 | 558 | select CPU_SA110 |
b1b3f49c | 559 | select FIQ |
d0ee9f40 | 560 | select HAVE_IDE |
b1b3f49c RK |
561 | select HAVE_PATA_PLATFORM |
562 | select ISA_DMA_API | |
c334bc15 | 563 | select NEED_MACH_IO_H |
0cdc8b92 | 564 | select NEED_MACH_MEMORY_H |
ce816fa8 | 565 | select NO_IOPORT_MAP |
1da177e4 LT |
566 | help |
567 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
568 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
569 | ||
570 | config ARCH_SA1100 | |
571 | bool "SA1100-based" | |
b1b3f49c | 572 | select ARCH_MTD_XIP |
b1b3f49c RK |
573 | select ARCH_SPARSEMEM_ENABLE |
574 | select CLKDEV_LOOKUP | |
575 | select CLKSRC_MMIO | |
389d9b58 | 576 | select CLKSRC_PXA |
bb0eb050 | 577 | select TIMER_OF if OF |
1937f5b9 | 578 | select CPU_FREQ |
b1b3f49c | 579 | select CPU_SA1100 |
3e238be2 | 580 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 581 | select GPIOLIB |
d0ee9f40 | 582 | select HAVE_IDE |
1eca42b4 | 583 | select IRQ_DOMAIN |
b1b3f49c | 584 | select ISA |
affcab32 | 585 | select MULTI_IRQ_HANDLER |
0cdc8b92 | 586 | select NEED_MACH_MEMORY_H |
375dec92 | 587 | select SPARSE_IRQ |
f999b8bd MM |
588 | help |
589 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 590 | |
b130d5c2 KK |
591 | config ARCH_S3C24XX |
592 | bool "Samsung S3C24XX SoCs" | |
335cce74 | 593 | select ATAGS |
b1b3f49c | 594 | select CLKDEV_LOOKUP |
4280506a | 595 | select CLKSRC_SAMSUNG_PWM |
7f78b6eb | 596 | select GENERIC_CLOCKEVENTS |
880cf071 | 597 | select GPIO_SAMSUNG |
5c34a4e8 | 598 | select GPIOLIB |
20676c15 | 599 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 | 600 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 601 | select HAVE_S3C_RTC if RTC_CLASS |
17453dd2 | 602 | select MULTI_IRQ_HANDLER |
c334bc15 | 603 | select NEED_MACH_IO_H |
cd8dc7ae | 604 | select SAMSUNG_ATAGS |
1da177e4 | 605 | help |
b130d5c2 KK |
606 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
607 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
608 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
609 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 610 | |
7c6337e2 KH |
611 | config ARCH_DAVINCI |
612 | bool "TI DaVinci" | |
b1b3f49c | 613 | select ARCH_HAS_HOLES_MEMORYMODEL |
6d803ba7 | 614 | select CLKDEV_LOOKUP |
ce32c5c5 | 615 | select CPU_ARM926T |
20e9969b | 616 | select GENERIC_ALLOCATOR |
b1b3f49c | 617 | select GENERIC_CLOCKEVENTS |
dc7ad3b3 | 618 | select GENERIC_IRQ_CHIP |
5c34a4e8 | 619 | select GPIOLIB |
b1b3f49c | 620 | select HAVE_IDE |
689e331f | 621 | select USE_OF |
b1b3f49c | 622 | select ZONE_DMA |
7c6337e2 KH |
623 | help |
624 | Support for TI's DaVinci platform. | |
625 | ||
a0694861 TL |
626 | config ARCH_OMAP1 |
627 | bool "TI OMAP1" | |
00a36698 | 628 | depends on MMU |
9af915da | 629 | select ARCH_HAS_HOLES_MEMORYMODEL |
a0694861 | 630 | select ARCH_OMAP |
b1b3f49c | 631 | select CLKDEV_LOOKUP |
d6e15d78 | 632 | select CLKSRC_MMIO |
b1b3f49c | 633 | select GENERIC_CLOCKEVENTS |
a0694861 | 634 | select GENERIC_IRQ_CHIP |
5c34a4e8 | 635 | select GPIOLIB |
a0694861 TL |
636 | select HAVE_IDE |
637 | select IRQ_DOMAIN | |
b694331c | 638 | select MULTI_IRQ_HANDLER |
a0694861 TL |
639 | select NEED_MACH_IO_H if PCCARD |
640 | select NEED_MACH_MEMORY_H | |
685e2d08 | 641 | select SPARSE_IRQ |
21f47fbc | 642 | help |
a0694861 | 643 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 644 | |
1da177e4 LT |
645 | endchoice |
646 | ||
387798b3 RH |
647 | menu "Multiple platform selection" |
648 | depends on ARCH_MULTIPLATFORM | |
649 | ||
650 | comment "CPU Core family selection" | |
651 | ||
f8afae40 AB |
652 | config ARCH_MULTI_V4 |
653 | bool "ARMv4 based platforms (FA526)" | |
654 | depends on !ARCH_MULTI_V6_V7 | |
655 | select ARCH_MULTI_V4_V5 | |
656 | select CPU_FA526 | |
657 | ||
387798b3 RH |
658 | config ARCH_MULTI_V4T |
659 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 660 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 661 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
662 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
663 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
664 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
665 | |
666 | config ARCH_MULTI_V5 | |
667 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 668 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 669 | select ARCH_MULTI_V4_V5 |
12567bbd | 670 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
24e860fb AB |
671 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
672 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
673 | |
674 | config ARCH_MULTI_V4_V5 | |
675 | bool | |
676 | ||
677 | config ARCH_MULTI_V6 | |
8dda05cc | 678 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 679 | select ARCH_MULTI_V6_V7 |
42f4754a | 680 | select CPU_V6K |
387798b3 RH |
681 | |
682 | config ARCH_MULTI_V7 | |
8dda05cc | 683 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
684 | default y |
685 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 686 | select CPU_V7 |
90bc8ac7 | 687 | select HAVE_SMP |
387798b3 RH |
688 | |
689 | config ARCH_MULTI_V6_V7 | |
690 | bool | |
9352b05b | 691 | select MIGHT_HAVE_CACHE_L2X0 |
387798b3 RH |
692 | |
693 | config ARCH_MULTI_CPU_AUTO | |
694 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
695 | select ARCH_MULTI_V5 | |
696 | ||
697 | endmenu | |
698 | ||
05e2a3de | 699 | config ARCH_VIRT |
e3246542 MY |
700 | bool "Dummy Virtual Machine" |
701 | depends on ARCH_MULTI_V7 | |
4b8b5f25 | 702 | select ARM_AMBA |
05e2a3de | 703 | select ARM_GIC |
3ee80364 | 704 | select ARM_GIC_V2M if PCI |
0b28f1db | 705 | select ARM_GIC_V3 |
bb29cecb | 706 | select ARM_GIC_V3_ITS if PCI |
05e2a3de | 707 | select ARM_PSCI |
4b8b5f25 | 708 | select HAVE_ARM_ARCH_TIMER |
05e2a3de | 709 | |
ccf50e23 RK |
710 | # |
711 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
712 | # Kconfigs may be included either alphabetically (according to the | |
713 | # plat- suffix) or along side the corresponding mach-* source. | |
714 | # | |
3e93a22b GC |
715 | source "arch/arm/mach-mvebu/Kconfig" |
716 | ||
6bb8536c AF |
717 | source "arch/arm/mach-actions/Kconfig" |
718 | ||
445d9b30 TZ |
719 | source "arch/arm/mach-alpine/Kconfig" |
720 | ||
590b460c LP |
721 | source "arch/arm/mach-artpec/Kconfig" |
722 | ||
d9bfc86d OR |
723 | source "arch/arm/mach-asm9260/Kconfig" |
724 | ||
95b8f20f RK |
725 | source "arch/arm/mach-at91/Kconfig" |
726 | ||
1d22924e AB |
727 | source "arch/arm/mach-axxia/Kconfig" |
728 | ||
8ac49e04 CD |
729 | source "arch/arm/mach-bcm/Kconfig" |
730 | ||
1c37fa10 SH |
731 | source "arch/arm/mach-berlin/Kconfig" |
732 | ||
1da177e4 LT |
733 | source "arch/arm/mach-clps711x/Kconfig" |
734 | ||
d94f944e AV |
735 | source "arch/arm/mach-cns3xxx/Kconfig" |
736 | ||
95b8f20f RK |
737 | source "arch/arm/mach-davinci/Kconfig" |
738 | ||
df8d742e BS |
739 | source "arch/arm/mach-digicolor/Kconfig" |
740 | ||
95b8f20f RK |
741 | source "arch/arm/mach-dove/Kconfig" |
742 | ||
e7736d47 LB |
743 | source "arch/arm/mach-ep93xx/Kconfig" |
744 | ||
1da177e4 LT |
745 | source "arch/arm/mach-footbridge/Kconfig" |
746 | ||
59d3a193 PZ |
747 | source "arch/arm/mach-gemini/Kconfig" |
748 | ||
387798b3 RH |
749 | source "arch/arm/mach-highbank/Kconfig" |
750 | ||
389ee0c2 HZ |
751 | source "arch/arm/mach-hisi/Kconfig" |
752 | ||
1da177e4 LT |
753 | source "arch/arm/mach-integrator/Kconfig" |
754 | ||
3f7e5815 LB |
755 | source "arch/arm/mach-iop32x/Kconfig" |
756 | ||
757 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 | 758 | |
285f5fa7 DW |
759 | source "arch/arm/mach-iop13xx/Kconfig" |
760 | ||
1da177e4 LT |
761 | source "arch/arm/mach-ixp4xx/Kconfig" |
762 | ||
828989ad SS |
763 | source "arch/arm/mach-keystone/Kconfig" |
764 | ||
95b8f20f RK |
765 | source "arch/arm/mach-ks8695/Kconfig" |
766 | ||
3b8f5030 CC |
767 | source "arch/arm/mach-meson/Kconfig" |
768 | ||
17723fd3 JJ |
769 | source "arch/arm/mach-moxart/Kconfig" |
770 | ||
8c2ed9bc JS |
771 | source "arch/arm/mach-aspeed/Kconfig" |
772 | ||
794d15b2 SS |
773 | source "arch/arm/mach-mv78xx0/Kconfig" |
774 | ||
3995eb82 | 775 | source "arch/arm/mach-imx/Kconfig" |
1da177e4 | 776 | |
f682a218 MB |
777 | source "arch/arm/mach-mediatek/Kconfig" |
778 | ||
1d3f33d5 SG |
779 | source "arch/arm/mach-mxs/Kconfig" |
780 | ||
95b8f20f | 781 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 782 | |
95b8f20f | 783 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 784 | |
9851ca57 DT |
785 | source "arch/arm/mach-nspire/Kconfig" |
786 | ||
d48af15e TL |
787 | source "arch/arm/plat-omap/Kconfig" |
788 | ||
789 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 790 | |
1dbae815 TL |
791 | source "arch/arm/mach-omap2/Kconfig" |
792 | ||
9dd0b194 | 793 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 794 | |
387798b3 RH |
795 | source "arch/arm/mach-picoxcell/Kconfig" |
796 | ||
95b8f20f RK |
797 | source "arch/arm/mach-pxa/Kconfig" |
798 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 799 | |
95b8f20f RK |
800 | source "arch/arm/mach-mmp/Kconfig" |
801 | ||
8c9184b7 NA |
802 | source "arch/arm/mach-oxnas/Kconfig" |
803 | ||
8fc1b0f8 KG |
804 | source "arch/arm/mach-qcom/Kconfig" |
805 | ||
95b8f20f RK |
806 | source "arch/arm/mach-realview/Kconfig" |
807 | ||
d63dc051 HS |
808 | source "arch/arm/mach-rockchip/Kconfig" |
809 | ||
95b8f20f | 810 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 811 | |
387798b3 RH |
812 | source "arch/arm/mach-socfpga/Kconfig" |
813 | ||
a7ed099f | 814 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 815 | |
65ebcc11 SK |
816 | source "arch/arm/mach-sti/Kconfig" |
817 | ||
bcb84fb4 AT |
818 | source "arch/arm/mach-stm32/Kconfig" |
819 | ||
85fd6d63 | 820 | source "arch/arm/mach-s3c24xx/Kconfig" |
1da177e4 | 821 | |
431107ea | 822 | source "arch/arm/mach-s3c64xx/Kconfig" |
a08ab637 | 823 | |
170f4e42 KK |
824 | source "arch/arm/mach-s5pv210/Kconfig" |
825 | ||
83014579 | 826 | source "arch/arm/mach-exynos/Kconfig" |
e509b289 | 827 | source "arch/arm/plat-samsung/Kconfig" |
cc0e72b8 | 828 | |
882d01f9 | 829 | source "arch/arm/mach-shmobile/Kconfig" |
52c543f9 | 830 | |
3b52634f MR |
831 | source "arch/arm/mach-sunxi/Kconfig" |
832 | ||
156a0997 BS |
833 | source "arch/arm/mach-prima2/Kconfig" |
834 | ||
d6de5b02 MG |
835 | source "arch/arm/mach-tango/Kconfig" |
836 | ||
c5f80065 EG |
837 | source "arch/arm/mach-tegra/Kconfig" |
838 | ||
95b8f20f | 839 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 840 | |
ba56a987 MY |
841 | source "arch/arm/mach-uniphier/Kconfig" |
842 | ||
95b8f20f | 843 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
844 | |
845 | source "arch/arm/mach-versatile/Kconfig" | |
846 | ||
ceade897 | 847 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 848 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 849 | |
6f35f9a9 TP |
850 | source "arch/arm/mach-vt8500/Kconfig" |
851 | ||
7ec80ddf | 852 | source "arch/arm/mach-w90x900/Kconfig" |
853 | ||
acede515 JN |
854 | source "arch/arm/mach-zx/Kconfig" |
855 | ||
9a45eb69 JC |
856 | source "arch/arm/mach-zynq/Kconfig" |
857 | ||
499f1640 SA |
858 | # ARMv7-M architecture |
859 | config ARCH_EFM32 | |
860 | bool "Energy Micro efm32" | |
861 | depends on ARM_SINGLE_ARMV7M | |
5c34a4e8 | 862 | select GPIOLIB |
499f1640 SA |
863 | help |
864 | Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko | |
865 | processors. | |
866 | ||
867 | config ARCH_LPC18XX | |
868 | bool "NXP LPC18xx/LPC43xx" | |
869 | depends on ARM_SINGLE_ARMV7M | |
870 | select ARCH_HAS_RESET_CONTROLLER | |
871 | select ARM_AMBA | |
872 | select CLKSRC_LPC32XX | |
873 | select PINCTRL | |
874 | help | |
875 | Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 | |
876 | high performance microcontrollers. | |
877 | ||
1847119d | 878 | config ARCH_MPS2 |
17bd274e | 879 | bool "ARM MPS2 platform" |
1847119d VM |
880 | depends on ARM_SINGLE_ARMV7M |
881 | select ARM_AMBA | |
882 | select CLKSRC_MPS2 | |
883 | help | |
884 | Support for Cortex-M Prototyping System (or V2M-MPS2) which comes | |
885 | with a range of available cores like Cortex-M3/M4/M7. | |
886 | ||
887 | Please, note that depends which Application Note is used memory map | |
888 | for the platform may vary, so adjustment of RAM base might be needed. | |
889 | ||
1da177e4 LT |
890 | # Definitions to make life easier |
891 | config ARCH_ACORN | |
892 | bool | |
893 | ||
7ae1f7ec LB |
894 | config PLAT_IOP |
895 | bool | |
469d3044 | 896 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 897 | |
69b02f6a LB |
898 | config PLAT_ORION |
899 | bool | |
bfe45e0b | 900 | select CLKSRC_MMIO |
b1b3f49c | 901 | select COMMON_CLK |
dc7ad3b3 | 902 | select GENERIC_IRQ_CHIP |
278b45b0 | 903 | select IRQ_DOMAIN |
69b02f6a | 904 | |
abcda1dc TP |
905 | config PLAT_ORION_LEGACY |
906 | bool | |
907 | select PLAT_ORION | |
908 | ||
bd5ce433 EM |
909 | config PLAT_PXA |
910 | bool | |
911 | ||
f4b8b319 RK |
912 | config PLAT_VERSATILE |
913 | bool | |
914 | ||
d9a1beaa AC |
915 | source "arch/arm/firmware/Kconfig" |
916 | ||
1da177e4 LT |
917 | source arch/arm/mm/Kconfig |
918 | ||
afe4b25e | 919 | config IWMMXT |
d93003e8 SH |
920 | bool "Enable iWMMXt support" |
921 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B | |
922 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B | |
afe4b25e LB |
923 | help |
924 | Enable support for iWMMXt context switching at run time if | |
925 | running on a CPU that supports it. | |
926 | ||
52108641 | 927 | config MULTI_IRQ_HANDLER |
928 | bool | |
929 | help | |
930 | Allow each machine to specify it's own IRQ handler at run time. | |
931 | ||
3b93e7b0 HC |
932 | if !MMU |
933 | source "arch/arm/Kconfig-nommu" | |
934 | endif | |
935 | ||
3e0a07f8 GC |
936 | config PJ4B_ERRATA_4742 |
937 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
938 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
939 | default y | |
940 | help | |
941 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
942 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
943 | the retiring WFI/WFE instructions and the newly issued subsequent | |
944 | instructions. This sensitivity can result in a CPU hang scenario. | |
945 | Workaround: | |
946 | The software must insert either a Data Synchronization Barrier (DSB) | |
947 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
948 | instruction | |
949 | ||
f0c4b8d6 WD |
950 | config ARM_ERRATA_326103 |
951 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
952 | depends on CPU_V6 | |
953 | help | |
954 | Executing a SWP instruction to read-only memory does not set bit 11 | |
955 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
956 | treat the access as a read, preventing a COW from occurring and | |
957 | causing the faulting task to livelock. | |
958 | ||
9cba3ccc CM |
959 | config ARM_ERRATA_411920 |
960 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 961 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
962 | help |
963 | Invalidation of the Instruction Cache operation can | |
964 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
965 | It does not affect the MPCore. This option enables the ARM Ltd. | |
966 | recommended workaround. | |
967 | ||
7ce236fc CM |
968 | config ARM_ERRATA_430973 |
969 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
970 | depends on CPU_V7 | |
971 | help | |
972 | This option enables the workaround for the 430973 Cortex-A8 | |
79403cda | 973 | r1p* erratum. If a code sequence containing an ARM/Thumb |
7ce236fc CM |
974 | interworking branch is replaced with another code sequence at the |
975 | same virtual address, whether due to self-modifying code or virtual | |
976 | to physical address re-mapping, Cortex-A8 does not recover from the | |
977 | stale interworking branch prediction. This results in Cortex-A8 | |
978 | executing the new code sequence in the incorrect ARM or Thumb state. | |
979 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
980 | and also flushes the branch target cache at every context switch. | |
981 | Note that setting specific bits in the ACTLR register may not be | |
982 | available in non-secure mode. | |
983 | ||
855c551f CM |
984 | config ARM_ERRATA_458693 |
985 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
986 | depends on CPU_V7 | |
62e4d357 | 987 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
988 | help |
989 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
990 | erratum. For very specific sequences of memory operations, it is | |
991 | possible for a hazard condition intended for a cache line to instead | |
992 | be incorrectly associated with a different cache line. This false | |
993 | hazard might then cause a processor deadlock. The workaround enables | |
994 | the L1 caching of the NEON accesses and disables the PLD instruction | |
995 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
996 | register may not be available in non-secure mode. | |
997 | ||
0516e464 CM |
998 | config ARM_ERRATA_460075 |
999 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
1000 | depends on CPU_V7 | |
62e4d357 | 1001 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
1002 | help |
1003 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
1004 | erratum. Any asynchronous access to the L2 cache may encounter a | |
1005 | situation in which recent store transactions to the L2 cache are lost | |
1006 | and overwritten with stale memory contents from external memory. The | |
1007 | workaround disables the write-allocate mode for the L2 cache via the | |
1008 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1009 | may not be available in non-secure mode. | |
1010 | ||
9f05027c WD |
1011 | config ARM_ERRATA_742230 |
1012 | bool "ARM errata: DMB operation may be faulty" | |
1013 | depends on CPU_V7 && SMP | |
62e4d357 | 1014 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
1015 | help |
1016 | This option enables the workaround for the 742230 Cortex-A9 | |
1017 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1018 | between two write operations may not ensure the correct visibility | |
1019 | ordering of the two writes. This workaround sets a specific bit in | |
1020 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1021 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1022 | the two writes. | |
1023 | ||
a672e99b WD |
1024 | config ARM_ERRATA_742231 |
1025 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1026 | depends on CPU_V7 && SMP | |
62e4d357 | 1027 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
1028 | help |
1029 | This option enables the workaround for the 742231 Cortex-A9 | |
1030 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1031 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1032 | accessing some data located in the same cache line, may get corrupted | |
1033 | data due to bad handling of the address hazard when the line gets | |
1034 | replaced from one of the CPUs at the same time as another CPU is | |
1035 | accessing it. This workaround sets specific bits in the diagnostic | |
1036 | register of the Cortex-A9 which reduces the linefill issuing | |
1037 | capabilities of the processor. | |
1038 | ||
69155794 JM |
1039 | config ARM_ERRATA_643719 |
1040 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
1041 | depends on CPU_V7 && SMP | |
e5a5de44 | 1042 | default y |
69155794 JM |
1043 | help |
1044 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
1045 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
1046 | register returns zero when it should return one. The workaround | |
1047 | corrects this value, ensuring cache maintenance operations which use | |
1048 | it behave as intended and avoiding data corruption. | |
1049 | ||
cdf357f1 WD |
1050 | config ARM_ERRATA_720789 |
1051 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1052 | depends on CPU_V7 |
cdf357f1 WD |
1053 | help |
1054 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1055 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1056 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1057 | As a consequence of this erratum, some TLB entries which should be | |
1058 | invalidated are not, resulting in an incoherency in the system page | |
1059 | tables. The workaround changes the TLB flushing routines to invalidate | |
1060 | entries regardless of the ASID. | |
475d92fc WD |
1061 | |
1062 | config ARM_ERRATA_743622 | |
1063 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1064 | depends on CPU_V7 | |
62e4d357 | 1065 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
1066 | help |
1067 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1068 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1069 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1070 | corruption. This workaround sets a specific bit in the diagnostic | |
1071 | register of the Cortex-A9 which disables the Store Buffer | |
1072 | optimisation, preventing the defect from occurring. This has no | |
1073 | visible impact on the overall performance or power consumption of the | |
1074 | processor. | |
1075 | ||
9a27c27c WD |
1076 | config ARM_ERRATA_751472 |
1077 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1078 | depends on CPU_V7 |
62e4d357 | 1079 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
1080 | help |
1081 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1082 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1083 | completion of a following broadcasted operation if the second | |
1084 | operation is received by a CPU before the ICIALLUIS has completed, | |
1085 | potentially leading to corrupted entries in the cache or TLB. | |
1086 | ||
fcbdc5fe WD |
1087 | config ARM_ERRATA_754322 |
1088 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1089 | depends on CPU_V7 | |
1090 | help | |
1091 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1092 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1093 | which starts prior to an ASID switch but completes afterwards. This | |
1094 | can populate the micro-TLB with a stale entry which may be hit with | |
1095 | the new ASID. This workaround places two dsb instructions in the mm | |
1096 | switching code so that no page table walks can cross the ASID switch. | |
1097 | ||
5dab26af WD |
1098 | config ARM_ERRATA_754327 |
1099 | bool "ARM errata: no automatic Store Buffer drain" | |
1100 | depends on CPU_V7 && SMP | |
1101 | help | |
1102 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1103 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1104 | mechanism and therefore a livelock may occur if an external agent | |
1105 | continuously polls a memory location waiting to observe an update. | |
1106 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1107 | written polling loops from denying visibility of updates to memory. | |
1108 | ||
145e10e1 CM |
1109 | config ARM_ERRATA_364296 |
1110 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 1111 | depends on CPU_V6 |
145e10e1 CM |
1112 | help |
1113 | This options enables the workaround for the 364296 ARM1136 | |
1114 | r0p2 erratum (possible cache data corruption with | |
1115 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1116 | the auxiliary control register and the FI bit in the control | |
1117 | register, thus disabling hit-under-miss without putting the | |
1118 | processor into full low interrupt latency mode. ARM11MPCore | |
1119 | is not affected. | |
1120 | ||
f630c1bd WD |
1121 | config ARM_ERRATA_764369 |
1122 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1123 | depends on CPU_V7 && SMP | |
1124 | help | |
1125 | This option enables the workaround for erratum 764369 | |
1126 | affecting Cortex-A9 MPCore with two or more processors (all | |
1127 | current revisions). Under certain timing circumstances, a data | |
1128 | cache line maintenance operation by MVA targeting an Inner | |
1129 | Shareable memory region may fail to proceed up to either the | |
1130 | Point of Coherency or to the Point of Unification of the | |
1131 | system. This workaround adds a DSB instruction before the | |
1132 | relevant cache maintenance functions and sets a specific bit | |
1133 | in the diagnostic control register of the SCU. | |
1134 | ||
7253b85c SH |
1135 | config ARM_ERRATA_775420 |
1136 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1137 | depends on CPU_V7 | |
1138 | help | |
1139 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1140 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1141 | operation aborts with MMU exception, it might cause the processor | |
1142 | to deadlock. This workaround puts DSB before executing ISB if | |
1143 | an abort may occur on cache maintenance. | |
1144 | ||
93dc6887 CM |
1145 | config ARM_ERRATA_798181 |
1146 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1147 | depends on CPU_V7 && SMP | |
1148 | help | |
1149 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1150 | adequately shooting down all use of the old entries. This | |
1151 | option enables the Linux kernel workaround for this erratum | |
1152 | which sends an IPI to the CPUs that are running the same ASID | |
1153 | as the one being invalidated. | |
1154 | ||
84b6504f WD |
1155 | config ARM_ERRATA_773022 |
1156 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
1157 | depends on CPU_V7 | |
1158 | help | |
1159 | This option enables the workaround for the 773022 Cortex-A15 | |
1160 | (up to r0p4) erratum. In certain rare sequences of code, the | |
1161 | loop buffer may deliver incorrect instructions. This | |
1162 | workaround disables the loop buffer to avoid the erratum. | |
1163 | ||
62c0f4a5 DA |
1164 | config ARM_ERRATA_818325_852422 |
1165 | bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" | |
1166 | depends on CPU_V7 | |
1167 | help | |
1168 | This option enables the workaround for: | |
1169 | - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM | |
1170 | instruction might deadlock. Fixed in r0p1. | |
1171 | - Cortex-A12 852422: Execution of a sequence of instructions might | |
1172 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1173 | any Cortex-A12 cores yet. | |
1174 | This workaround for all both errata involves setting bit[12] of the | |
1175 | Feature Register. This bit disables an optimisation applied to a | |
1176 | sequence of 2 instructions that use opposing condition codes. | |
1177 | ||
416bcf21 DA |
1178 | config ARM_ERRATA_821420 |
1179 | bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" | |
1180 | depends on CPU_V7 | |
1181 | help | |
1182 | This option enables the workaround for the 821420 Cortex-A12 | |
1183 | (all revs) erratum. In very rare timing conditions, a sequence | |
1184 | of VMOV to Core registers instructions, for which the second | |
1185 | one is in the shadow of a branch or abort, can lead to a | |
1186 | deadlock when the VMOV instructions are issued out-of-order. | |
1187 | ||
9f6f9354 DA |
1188 | config ARM_ERRATA_825619 |
1189 | bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" | |
1190 | depends on CPU_V7 | |
1191 | help | |
1192 | This option enables the workaround for the 825619 Cortex-A12 | |
1193 | (all revs) erratum. Within rare timing constraints, executing a | |
1194 | DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable | |
1195 | and Device/Strongly-Ordered loads and stores might cause deadlock | |
1196 | ||
1197 | config ARM_ERRATA_852421 | |
1198 | bool "ARM errata: A17: DMB ST might fail to create order between stores" | |
1199 | depends on CPU_V7 | |
1200 | help | |
1201 | This option enables the workaround for the 852421 Cortex-A17 | |
1202 | (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, | |
1203 | execution of a DMB ST instruction might fail to properly order | |
1204 | stores from GroupA and stores from GroupB. | |
1205 | ||
62c0f4a5 DA |
1206 | config ARM_ERRATA_852423 |
1207 | bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" | |
1208 | depends on CPU_V7 | |
1209 | help | |
1210 | This option enables the workaround for: | |
1211 | - Cortex-A17 852423: Execution of a sequence of instructions might | |
1212 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1213 | any Cortex-A17 cores yet. | |
1214 | This is identical to Cortex-A12 erratum 852422. It is a separate | |
1215 | config option from the A12 erratum due to the way errata are checked | |
1216 | for and handled. | |
1217 | ||
1da177e4 LT |
1218 | endmenu |
1219 | ||
1220 | source "arch/arm/common/Kconfig" | |
1221 | ||
1da177e4 LT |
1222 | menu "Bus support" |
1223 | ||
1da177e4 LT |
1224 | config ISA |
1225 | bool | |
1da177e4 LT |
1226 | help |
1227 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1228 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1229 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1230 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1231 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1232 | ||
065909b9 | 1233 | # Select ISA DMA controller support |
1da177e4 LT |
1234 | config ISA_DMA |
1235 | bool | |
065909b9 | 1236 | select ISA_DMA_API |
1da177e4 | 1237 | |
065909b9 | 1238 | # Select ISA DMA interface |
5cae841b AV |
1239 | config ISA_DMA_API |
1240 | bool | |
5cae841b | 1241 | |
1da177e4 | 1242 | config PCI |
0b05da72 | 1243 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1244 | help |
1245 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1246 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1247 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1248 | VESA. If you have PCI, say Y, otherwise N. | |
1249 | ||
52882173 AV |
1250 | config PCI_DOMAINS |
1251 | bool | |
1252 | depends on PCI | |
1253 | ||
8c7d1474 LP |
1254 | config PCI_DOMAINS_GENERIC |
1255 | def_bool PCI_DOMAINS | |
1256 | ||
b080ac8a MRJ |
1257 | config PCI_NANOENGINE |
1258 | bool "BSE nanoEngine PCI support" | |
1259 | depends on SA1100_NANOENGINE | |
1260 | help | |
1261 | Enable PCI on the BSE nanoEngine board. | |
1262 | ||
36e23590 MW |
1263 | config PCI_SYSCALL |
1264 | def_bool PCI | |
1265 | ||
a0113a99 MR |
1266 | config PCI_HOST_ITE8152 |
1267 | bool | |
1268 | depends on PCI && MACH_ARMCORE | |
1269 | default y | |
1270 | select DMABOUNCE | |
1271 | ||
1da177e4 LT |
1272 | source "drivers/pci/Kconfig" |
1273 | ||
1274 | source "drivers/pcmcia/Kconfig" | |
1275 | ||
1276 | endmenu | |
1277 | ||
1278 | menu "Kernel Features" | |
1279 | ||
3b55658a DM |
1280 | config HAVE_SMP |
1281 | bool | |
1282 | help | |
1283 | This option should be selected by machines which have an SMP- | |
1284 | capable CPU. | |
1285 | ||
1286 | The only effect of this option is to make the SMP-related | |
1287 | options available to the user for configuration. | |
1288 | ||
1da177e4 | 1289 | config SMP |
bb2d8130 | 1290 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1291 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1292 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1293 | depends on HAVE_SMP |
801bb21c | 1294 | depends on MMU || ARM_MPU |
0361748f | 1295 | select IRQ_WORK |
1da177e4 LT |
1296 | help |
1297 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
1298 | a system with only one CPU, say N. If you have a system with more |
1299 | than one CPU, say Y. | |
1da177e4 | 1300 | |
4a474157 | 1301 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 1302 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
1303 | you say Y here, the kernel will run on many, but not all, |
1304 | uniprocessor machines. On a uniprocessor machine, the kernel | |
1305 | will run faster if you say N here. | |
1da177e4 | 1306 | |
395cf969 | 1307 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
1da177e4 | 1308 | <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at |
50a23e6e | 1309 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1310 | |
1311 | If you don't know what to do here, say N. | |
1312 | ||
f00ec48f | 1313 | config SMP_ON_UP |
5744ff43 | 1314 | bool "Allow booting SMP kernel on uniprocessor systems" |
801bb21c | 1315 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1316 | default y |
1317 | help | |
1318 | SMP kernels contain instructions which fail on non-SMP processors. | |
1319 | Enabling this option allows the kernel to modify itself to make | |
1320 | these instructions safe. Disabling it allows about 1K of space | |
1321 | savings. | |
1322 | ||
1323 | If you don't know what to do here, say Y. | |
1324 | ||
c9018aab VG |
1325 | config ARM_CPU_TOPOLOGY |
1326 | bool "Support cpu topology definition" | |
1327 | depends on SMP && CPU_V7 | |
1328 | default y | |
1329 | help | |
1330 | Support ARM cpu topology definition. The MPIDR register defines | |
1331 | affinity between processors which is then used to describe the cpu | |
1332 | topology of an ARM System. | |
1333 | ||
1334 | config SCHED_MC | |
1335 | bool "Multi-core scheduler support" | |
1336 | depends on ARM_CPU_TOPOLOGY | |
1337 | help | |
1338 | Multi-core scheduler support improves the CPU scheduler's decision | |
1339 | making when dealing with multi-core CPU chips at a cost of slightly | |
1340 | increased overhead in some places. If unsure say N here. | |
1341 | ||
1342 | config SCHED_SMT | |
1343 | bool "SMT scheduler support" | |
1344 | depends on ARM_CPU_TOPOLOGY | |
1345 | help | |
1346 | Improves the CPU scheduler's decision making when dealing with | |
1347 | MultiThreading at a cost of slightly increased overhead in some | |
1348 | places. If unsure say N here. | |
1349 | ||
a8cbcd92 RK |
1350 | config HAVE_ARM_SCU |
1351 | bool | |
a8cbcd92 RK |
1352 | help |
1353 | This option enables support for the ARM system coherency unit | |
1354 | ||
8a4da6e3 | 1355 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1356 | bool "Architected timer support" |
1357 | depends on CPU_V7 | |
8a4da6e3 | 1358 | select ARM_ARCH_TIMER |
0c403462 | 1359 | select GENERIC_CLOCKEVENTS |
022c03a2 MZ |
1360 | help |
1361 | This option enables support for the ARM architected timer | |
1362 | ||
f32f4ce2 RK |
1363 | config HAVE_ARM_TWD |
1364 | bool | |
bb0eb050 | 1365 | select TIMER_OF if OF |
f32f4ce2 RK |
1366 | help |
1367 | This options enables support for the ARM timer and watchdog unit | |
1368 | ||
e8db288e NP |
1369 | config MCPM |
1370 | bool "Multi-Cluster Power Management" | |
1371 | depends on CPU_V7 && SMP | |
1372 | help | |
1373 | This option provides the common power management infrastructure | |
1374 | for (multi-)cluster based systems, such as big.LITTLE based | |
1375 | systems. | |
1376 | ||
ebf4a5c5 HZ |
1377 | config MCPM_QUAD_CLUSTER |
1378 | bool | |
1379 | depends on MCPM | |
1380 | help | |
1381 | To avoid wasting resources unnecessarily, MCPM only supports up | |
1382 | to 2 clusters by default. | |
1383 | Platforms with 3 or 4 clusters that use MCPM must select this | |
1384 | option to allow the additional clusters to be managed. | |
1385 | ||
1c33be57 NP |
1386 | config BIG_LITTLE |
1387 | bool "big.LITTLE support (Experimental)" | |
1388 | depends on CPU_V7 && SMP | |
1389 | select MCPM | |
1390 | help | |
1391 | This option enables support selections for the big.LITTLE | |
1392 | system architecture. | |
1393 | ||
1394 | config BL_SWITCHER | |
1395 | bool "big.LITTLE switcher support" | |
6c044fec | 1396 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC |
51aaf81f | 1397 | select CPU_PM |
1c33be57 NP |
1398 | help |
1399 | The big.LITTLE "switcher" provides the core functionality to | |
1400 | transparently handle transition between a cluster of A15's | |
1401 | and a cluster of A7's in a big.LITTLE system. | |
1402 | ||
b22537c6 NP |
1403 | config BL_SWITCHER_DUMMY_IF |
1404 | tristate "Simple big.LITTLE switcher user interface" | |
1405 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1406 | help | |
1407 | This is a simple and dummy char dev interface to control | |
1408 | the big.LITTLE switcher core code. It is meant for | |
1409 | debugging purposes only. | |
1410 | ||
8d5796d2 LB |
1411 | choice |
1412 | prompt "Memory split" | |
006fa259 | 1413 | depends on MMU |
8d5796d2 LB |
1414 | default VMSPLIT_3G |
1415 | help | |
1416 | Select the desired split between kernel and user memory. | |
1417 | ||
1418 | If you are not absolutely sure what you are doing, leave this | |
1419 | option alone! | |
1420 | ||
1421 | config VMSPLIT_3G | |
1422 | bool "3G/1G user/kernel split" | |
63ce446c | 1423 | config VMSPLIT_3G_OPT |
bbeedfda | 1424 | depends on !ARM_LPAE |
63ce446c | 1425 | bool "3G/1G user/kernel split (for full 1G low memory)" |
8d5796d2 LB |
1426 | config VMSPLIT_2G |
1427 | bool "2G/2G user/kernel split" | |
1428 | config VMSPLIT_1G | |
1429 | bool "1G/3G user/kernel split" | |
1430 | endchoice | |
1431 | ||
1432 | config PAGE_OFFSET | |
1433 | hex | |
006fa259 | 1434 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1435 | default 0x40000000 if VMSPLIT_1G |
1436 | default 0x80000000 if VMSPLIT_2G | |
63ce446c | 1437 | default 0xB0000000 if VMSPLIT_3G_OPT |
8d5796d2 LB |
1438 | default 0xC0000000 |
1439 | ||
1da177e4 LT |
1440 | config NR_CPUS |
1441 | int "Maximum number of CPUs (2-32)" | |
1442 | range 2 32 | |
1443 | depends on SMP | |
1444 | default "4" | |
1445 | ||
a054a811 | 1446 | config HOTPLUG_CPU |
00b7dede | 1447 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1448 | depends on SMP |
a054a811 RK |
1449 | help |
1450 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1451 | can be controlled through /sys/devices/system/cpu. | |
1452 | ||
2bdd424f WD |
1453 | config ARM_PSCI |
1454 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
e679660d | 1455 | depends on HAVE_ARM_SMCCC |
be120397 | 1456 | select ARM_PSCI_FW |
2bdd424f WD |
1457 | help |
1458 | Say Y here if you want Linux to communicate with system firmware | |
1459 | implementing the PSCI specification for CPU-centric power | |
1460 | management operations described in ARM document number ARM DEN | |
1461 | 0022A ("Power State Coordination Interface System Software on | |
1462 | ARM processors"). | |
1463 | ||
2a6ad871 MR |
1464 | # The GPIO number here must be sorted by descending number. In case of |
1465 | # a multiplatform kernel, we just want the highest value required by the | |
1466 | # selected platforms. | |
44986ab0 PDSN |
1467 | config ARCH_NR_GPIO |
1468 | int | |
139358be | 1469 | default 2048 if ARCH_SOCFPGA |
b35d2e56 GF |
1470 | default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ |
1471 | ARCH_ZYNQ | |
aa42587a TF |
1472 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ |
1473 | SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 | |
eb171a99 | 1474 | default 416 if ARCH_SUNXI |
06b851e5 | 1475 | default 392 if ARCH_U8500 |
01bb914c | 1476 | default 352 if ARCH_VT8500 |
7b5da4c3 | 1477 | default 288 if ARCH_ROCKCHIP |
2a6ad871 | 1478 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1479 | default 0 |
1480 | help | |
1481 | Maximum number of GPIOs in the system. | |
1482 | ||
1483 | If unsure, leave the default value. | |
1484 | ||
d45a398f | 1485 | source kernel/Kconfig.preempt |
1da177e4 | 1486 | |
c9218b16 | 1487 | config HZ_FIXED |
f8065813 | 1488 | int |
da6b21e9 | 1489 | default 200 if ARCH_EBSA110 |
1164f672 | 1490 | default 128 if SOC_AT91RM9200 |
47d84682 | 1491 | default 0 |
c9218b16 RK |
1492 | |
1493 | choice | |
47d84682 | 1494 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1495 | prompt "Timer frequency" |
1496 | ||
1497 | config HZ_100 | |
1498 | bool "100 Hz" | |
1499 | ||
1500 | config HZ_200 | |
1501 | bool "200 Hz" | |
1502 | ||
1503 | config HZ_250 | |
1504 | bool "250 Hz" | |
1505 | ||
1506 | config HZ_300 | |
1507 | bool "300 Hz" | |
1508 | ||
1509 | config HZ_500 | |
1510 | bool "500 Hz" | |
1511 | ||
1512 | config HZ_1000 | |
1513 | bool "1000 Hz" | |
1514 | ||
1515 | endchoice | |
1516 | ||
1517 | config HZ | |
1518 | int | |
47d84682 | 1519 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1520 | default 100 if HZ_100 |
1521 | default 200 if HZ_200 | |
1522 | default 250 if HZ_250 | |
1523 | default 300 if HZ_300 | |
1524 | default 500 if HZ_500 | |
1525 | default 1000 | |
1526 | ||
1527 | config SCHED_HRTICK | |
1528 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1529 | |
16c79651 | 1530 | config THUMB2_KERNEL |
bc7dea00 | 1531 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1532 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1533 | default y if CPU_THUMBONLY |
16c79651 CM |
1534 | select AEABI |
1535 | select ARM_ASM_UNIFIED | |
89bace65 | 1536 | select ARM_UNWIND |
16c79651 CM |
1537 | help |
1538 | By enabling this option, the kernel will be compiled in | |
1539 | Thumb-2 mode. A compiler/assembler that understand the unified | |
1540 | ARM-Thumb syntax is needed. | |
1541 | ||
1542 | If unsure, say N. | |
1543 | ||
6f685c5c DM |
1544 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1545 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1546 | depends on THUMB2_KERNEL && MODULES | |
1547 | default y | |
1548 | help | |
1549 | Various binutils versions can resolve Thumb-2 branches to | |
1550 | locally-defined, preemptible global symbols as short-range "b.n" | |
1551 | branch instructions. | |
1552 | ||
1553 | This is a problem, because there's no guarantee the final | |
1554 | destination of the symbol, or any candidate locations for a | |
1555 | trampoline, are within range of the branch. For this reason, the | |
1556 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1557 | relocation in modules at all, and it makes little sense to add | |
1558 | support. | |
1559 | ||
1560 | The symptom is that the kernel fails with an "unsupported | |
1561 | relocation" error when loading some modules. | |
1562 | ||
1563 | Until fixed tools are available, passing | |
1564 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1565 | code which hits this problem, at the cost of a bit of extra runtime | |
1566 | stack usage in some cases. | |
1567 | ||
1568 | The problem is described in more detail at: | |
1569 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1570 | ||
1571 | Only Thumb-2 kernels are affected. | |
1572 | ||
1573 | Unless you are sure your tools don't have this problem, say Y. | |
1574 | ||
0becb088 CM |
1575 | config ARM_ASM_UNIFIED |
1576 | bool | |
1577 | ||
42f25bdd NP |
1578 | config ARM_PATCH_IDIV |
1579 | bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" | |
1580 | depends on CPU_32v7 && !XIP_KERNEL | |
1581 | default y | |
1582 | help | |
1583 | The ARM compiler inserts calls to __aeabi_idiv() and | |
1584 | __aeabi_uidiv() when it needs to perform division on signed | |
1585 | and unsigned integers. Some v7 CPUs have support for the sdiv | |
1586 | and udiv instructions that can be used to implement those | |
1587 | functions. | |
1588 | ||
1589 | Enabling this option allows the kernel to modify itself to | |
1590 | replace the first two instructions of these library functions | |
1591 | with the sdiv or udiv plus "bx lr" instructions when the CPU | |
1592 | it is running on supports them. Typically this will be faster | |
1593 | and less power intensive than running the original library | |
1594 | code to do integer division. | |
1595 | ||
704bdda0 NP |
1596 | config AEABI |
1597 | bool "Use the ARM EABI to compile the kernel" | |
1598 | help | |
1599 | This option allows for the kernel to be compiled using the latest | |
1600 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1601 | space environment that is also compiled with EABI. | |
1602 | ||
1603 | Since there are major incompatibilities between the legacy ABI and | |
1604 | EABI, especially with regard to structure member alignment, this | |
1605 | option also changes the kernel syscall calling convention to | |
1606 | disambiguate both ABIs and allow for backward compatibility support | |
1607 | (selected with CONFIG_OABI_COMPAT). | |
1608 | ||
1609 | To use this you need GCC version 4.0.0 or later. | |
1610 | ||
6c90c872 | 1611 | config OABI_COMPAT |
a73a3ff1 | 1612 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1613 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1614 | help |
1615 | This option preserves the old syscall interface along with the | |
1616 | new (ARM EABI) one. It also provides a compatibility layer to | |
1617 | intercept syscalls that have structure arguments which layout | |
1618 | in memory differs between the legacy ABI and the new ARM EABI | |
1619 | (only for non "thumb" binaries). This option adds a tiny | |
1620 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1621 | |
1622 | The seccomp filter system will not be available when this is | |
1623 | selected, since there is no way yet to sensibly distinguish | |
1624 | between calling conventions during filtering. | |
1625 | ||
6c90c872 NP |
1626 | If you know you'll be using only pure EABI user space then you |
1627 | can say N here. If this option is not selected and you attempt | |
1628 | to execute a legacy ABI binary then the result will be | |
1629 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1630 | at all). If in doubt say N. |
6c90c872 | 1631 | |
eb33575c | 1632 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1633 | bool |
e80d6a24 | 1634 | |
05944d74 RK |
1635 | config ARCH_SPARSEMEM_ENABLE |
1636 | bool | |
1637 | ||
07a2f737 RK |
1638 | config ARCH_SPARSEMEM_DEFAULT |
1639 | def_bool ARCH_SPARSEMEM_ENABLE | |
1640 | ||
05944d74 | 1641 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1642 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1643 | |
7b7bf499 WD |
1644 | config HAVE_ARCH_PFN_VALID |
1645 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1646 | ||
e585513b | 1647 | config HAVE_GENERIC_GUP |
b8cd51af SC |
1648 | def_bool y |
1649 | depends on ARM_LPAE | |
1650 | ||
053a96ca | 1651 | config HIGHMEM |
e8db89a2 RK |
1652 | bool "High Memory Support" |
1653 | depends on MMU | |
053a96ca NP |
1654 | help |
1655 | The address space of ARM processors is only 4 Gigabytes large | |
1656 | and it has to accommodate user address space, kernel address | |
1657 | space as well as some memory mapped IO. That means that, if you | |
1658 | have a large amount of physical memory and/or IO, not all of the | |
1659 | memory can be "permanently mapped" by the kernel. The physical | |
1660 | memory that is not permanently mapped is called "high memory". | |
1661 | ||
1662 | Depending on the selected kernel/user memory split, minimum | |
1663 | vmalloc space and actual amount of RAM, you may not need this | |
1664 | option which should result in a slightly faster kernel. | |
1665 | ||
1666 | If unsure, say n. | |
1667 | ||
65cec8e3 | 1668 | config HIGHPTE |
9a431bd5 | 1669 | bool "Allocate 2nd-level pagetables from highmem" if EXPERT |
65cec8e3 | 1670 | depends on HIGHMEM |
9a431bd5 | 1671 | default y |
b4d103d1 RK |
1672 | help |
1673 | The VM uses one page of physical memory for each page table. | |
1674 | For systems with a lot of processes, this can use a lot of | |
1675 | precious low memory, eventually leading to low memory being | |
1676 | consumed by page tables. Setting this option will allow | |
1677 | user-space 2nd level page tables to reside in high memory. | |
65cec8e3 | 1678 | |
a5e090ac RK |
1679 | config CPU_SW_DOMAIN_PAN |
1680 | bool "Enable use of CPU domains to implement privileged no-access" | |
1681 | depends on MMU && !ARM_LPAE | |
1b8873a0 JI |
1682 | default y |
1683 | help | |
a5e090ac RK |
1684 | Increase kernel security by ensuring that normal kernel accesses |
1685 | are unable to access userspace addresses. This can help prevent | |
1686 | use-after-free bugs becoming an exploitable privilege escalation | |
1687 | by ensuring that magic values (such as LIST_POISON) will always | |
1688 | fault when dereferenced. | |
1689 | ||
1690 | CPUs with low-vector mappings use a best-efforts implementation. | |
1691 | Their lower 1MB needs to remain accessible for the vectors, but | |
1692 | the remainder of userspace will become appropriately inaccessible. | |
65cec8e3 | 1693 | |
1b8873a0 | 1694 | config HW_PERF_EVENTS |
fa8ad788 MR |
1695 | def_bool y |
1696 | depends on ARM_PMU | |
1b8873a0 | 1697 | |
1355e2a6 CM |
1698 | config SYS_SUPPORTS_HUGETLBFS |
1699 | def_bool y | |
1700 | depends on ARM_LPAE | |
1701 | ||
8d962507 CM |
1702 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
1703 | def_bool y | |
1704 | depends on ARM_LPAE | |
1705 | ||
4bfab203 SC |
1706 | config ARCH_WANT_GENERAL_HUGETLB |
1707 | def_bool y | |
1708 | ||
7d485f64 AB |
1709 | config ARM_MODULE_PLTS |
1710 | bool "Use PLTs to allow module memory to spill over into vmalloc area" | |
1711 | depends on MODULES | |
1712 | help | |
1713 | Allocate PLTs when loading modules so that jumps and calls whose | |
1714 | targets are too far away for their relative offsets to be encoded | |
1715 | in the instructions themselves can be bounced via veneers in the | |
1716 | module's PLT. This allows modules to be allocated in the generic | |
1717 | vmalloc area after the dedicated module memory area has been | |
1718 | exhausted. The modules will use slightly more memory, but after | |
1719 | rounding up to page size, the actual memory footprint is usually | |
1720 | the same. | |
1721 | ||
1722 | Say y if you are getting out of memory errors while loading modules | |
1723 | ||
3f22ab27 DH |
1724 | source "mm/Kconfig" |
1725 | ||
c1b2d970 | 1726 | config FORCE_MAX_ZONEORDER |
36d6c928 | 1727 | int "Maximum zone order" |
898f08e1 | 1728 | default "12" if SOC_AM33XX |
6d85e2b0 | 1729 | default "9" if SA1111 || ARCH_EFM32 |
c1b2d970 MD |
1730 | default "11" |
1731 | help | |
1732 | The kernel memory allocator divides physically contiguous memory | |
1733 | blocks into "zones", where each zone is a power of two number of | |
1734 | pages. This option selects the largest power of two that the kernel | |
1735 | keeps in the memory allocator. If you need to allocate very large | |
1736 | blocks of physically contiguous memory, then you may need to | |
1737 | increase this value. | |
1738 | ||
1739 | This config option is actually maximum order plus one. For example, | |
1740 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1741 | ||
1da177e4 LT |
1742 | config ALIGNMENT_TRAP |
1743 | bool | |
f12d0d7c | 1744 | depends on CPU_CP15_MMU |
1da177e4 | 1745 | default y if !ARCH_EBSA110 |
e119bfff | 1746 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1747 | help |
84eb8d06 | 1748 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1749 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1750 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1751 | fetch/store instructions will be emulated in software if you say | |
1752 | here, which has a severe performance impact. This is necessary for | |
1753 | correct operation of some network protocols. With an IP-only | |
1754 | configuration it is safe to say N, otherwise say Y. | |
1755 | ||
39ec58f3 | 1756 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1757 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1758 | depends on MMU | |
39ec58f3 LB |
1759 | default y if CPU_FEROCEON |
1760 | help | |
1761 | Implement faster copy_to_user and clear_user methods for CPU | |
1762 | cores where a 8-word STM instruction give significantly higher | |
1763 | memory write throughput than a sequence of individual 32bit stores. | |
1764 | ||
1765 | A possible side effect is a slight increase in scheduling latency | |
1766 | between threads sharing the same address space if they invoke | |
1767 | such copy operations with large buffers. | |
1768 | ||
1769 | However, if the CPU data cache is using a write-allocate mode, | |
1770 | this option is unlikely to provide any performance gain. | |
1771 | ||
70c70d97 NP |
1772 | config SECCOMP |
1773 | bool | |
1774 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1775 | ---help--- | |
1776 | This kernel feature is useful for number crunching applications | |
1777 | that may need to compute untrusted bytecode during their | |
1778 | execution. By using pipes or other transports made available to | |
1779 | the process as file descriptors supporting the read/write | |
1780 | syscalls, it's possible to isolate those applications in | |
1781 | their own address space using seccomp. Once seccomp is | |
1782 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1783 | and the task is only allowed to execute a few safe syscalls | |
1784 | defined by each seccomp mode. | |
1785 | ||
06e6295b SS |
1786 | config SWIOTLB |
1787 | def_bool y | |
1788 | ||
1789 | config IOMMU_HELPER | |
1790 | def_bool SWIOTLB | |
1791 | ||
02c2433b SS |
1792 | config PARAVIRT |
1793 | bool "Enable paravirtualization code" | |
1794 | help | |
1795 | This changes the kernel so it can modify itself when it is run | |
1796 | under a hypervisor, potentially improving performance significantly | |
1797 | over full virtualization. | |
1798 | ||
1799 | config PARAVIRT_TIME_ACCOUNTING | |
1800 | bool "Paravirtual steal time accounting" | |
1801 | select PARAVIRT | |
1802 | default n | |
1803 | help | |
1804 | Select this option to enable fine granularity task steal time | |
1805 | accounting. Time spent executing other tasks in parallel with | |
1806 | the current vCPU is discounted from the vCPU power. To account for | |
1807 | that, there can be a small performance impact. | |
1808 | ||
1809 | If in doubt, say N here. | |
1810 | ||
eff8d644 SS |
1811 | config XEN_DOM0 |
1812 | def_bool y | |
1813 | depends on XEN | |
1814 | ||
1815 | config XEN | |
c2ba1f7d | 1816 | bool "Xen guest support on ARM" |
85323a99 | 1817 | depends on ARM && AEABI && OF |
f880b67d | 1818 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1819 | depends on !GENERIC_ATOMIC64 |
7693decc | 1820 | depends on MMU |
51aaf81f | 1821 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1822 | select ARM_PSCI |
83862ccf | 1823 | select SWIOTLB_XEN |
02c2433b | 1824 | select PARAVIRT |
eff8d644 SS |
1825 | help |
1826 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1827 | ||
1da177e4 LT |
1828 | endmenu |
1829 | ||
1830 | menu "Boot options" | |
1831 | ||
9eb8f674 GL |
1832 | config USE_OF |
1833 | bool "Flattened Device Tree support" | |
b1b3f49c | 1834 | select IRQ_DOMAIN |
9eb8f674 | 1835 | select OF |
9eb8f674 GL |
1836 | help |
1837 | Include support for flattened device tree machine descriptions. | |
1838 | ||
bd51e2f5 NP |
1839 | config ATAGS |
1840 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1841 | default y | |
1842 | help | |
1843 | This is the traditional way of passing data to the kernel at boot | |
1844 | time. If you are solely relying on the flattened device tree (or | |
1845 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1846 | to remove ATAGS support from your kernel binary. If unsure, | |
1847 | leave this to y. | |
1848 | ||
1849 | config DEPRECATED_PARAM_STRUCT | |
1850 | bool "Provide old way to pass kernel parameters" | |
1851 | depends on ATAGS | |
1852 | help | |
1853 | This was deprecated in 2001 and announced to live on for 5 years. | |
1854 | Some old boot loaders still use this way. | |
1855 | ||
1da177e4 LT |
1856 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1857 | # TEXT and BSS so we preserve their values in the config files. | |
1858 | config ZBOOT_ROM_TEXT | |
1859 | hex "Compressed ROM boot loader base address" | |
1860 | default "0" | |
1861 | help | |
1862 | The physical address at which the ROM-able zImage is to be | |
1863 | placed in the target. Platforms which normally make use of | |
1864 | ROM-able zImage formats normally set this to a suitable | |
1865 | value in their defconfig file. | |
1866 | ||
1867 | If ZBOOT_ROM is not enabled, this has no effect. | |
1868 | ||
1869 | config ZBOOT_ROM_BSS | |
1870 | hex "Compressed ROM boot loader BSS address" | |
1871 | default "0" | |
1872 | help | |
f8c440b2 DF |
1873 | The base address of an area of read/write memory in the target |
1874 | for the ROM-able zImage which must be available while the | |
1875 | decompressor is running. It must be large enough to hold the | |
1876 | entire decompressed kernel plus an additional 128 KiB. | |
1877 | Platforms which normally make use of ROM-able zImage formats | |
1878 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1879 | |
1880 | If ZBOOT_ROM is not enabled, this has no effect. | |
1881 | ||
1882 | config ZBOOT_ROM | |
1883 | bool "Compressed boot loader in ROM/flash" | |
1884 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1885 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1886 | help |
1887 | Say Y here if you intend to execute your compressed kernel image | |
1888 | (zImage) directly from ROM or flash. If unsure, say N. | |
1889 | ||
e2a6a3aa JB |
1890 | config ARM_APPENDED_DTB |
1891 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1892 | depends on OF |
e2a6a3aa JB |
1893 | help |
1894 | With this option, the boot code will look for a device tree binary | |
1895 | (DTB) appended to zImage | |
1896 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1897 | ||
1898 | This is meant as a backward compatibility convenience for those | |
1899 | systems with a bootloader that can't be upgraded to accommodate | |
1900 | the documented boot protocol using a device tree. | |
1901 | ||
1902 | Beware that there is very little in terms of protection against | |
1903 | this option being confused by leftover garbage in memory that might | |
1904 | look like a DTB header after a reboot if no actual DTB is appended | |
1905 | to zImage. Do not leave this option active in a production kernel | |
1906 | if you don't intend to always append a DTB. Proper passing of the | |
1907 | location into r2 of a bootloader provided DTB is always preferable | |
1908 | to this option. | |
1909 | ||
b90b9a38 NP |
1910 | config ARM_ATAG_DTB_COMPAT |
1911 | bool "Supplement the appended DTB with traditional ATAG information" | |
1912 | depends on ARM_APPENDED_DTB | |
1913 | help | |
1914 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1915 | they provide ATAGs with memory configuration, the ramdisk address, | |
1916 | the kernel cmdline string, etc. Such information is dynamically | |
1917 | provided by the bootloader and can't always be stored in a static | |
1918 | DTB. To allow a device tree enabled kernel to be used with such | |
1919 | bootloaders, this option allows zImage to extract the information | |
1920 | from the ATAG list and store it at run time into the appended DTB. | |
1921 | ||
d0f34a11 GR |
1922 | choice |
1923 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1924 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1925 | ||
1926 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1927 | bool "Use bootloader kernel arguments if available" | |
1928 | help | |
1929 | Uses the command-line options passed by the boot loader instead of | |
1930 | the device tree bootargs property. If the boot loader doesn't provide | |
1931 | any, the device tree bootargs property will be used. | |
1932 | ||
1933 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1934 | bool "Extend with bootloader kernel arguments" | |
1935 | help | |
1936 | The command-line arguments provided by the boot loader will be | |
1937 | appended to the the device tree bootargs property. | |
1938 | ||
1939 | endchoice | |
1940 | ||
1da177e4 LT |
1941 | config CMDLINE |
1942 | string "Default kernel command string" | |
1943 | default "" | |
1944 | help | |
1945 | On some architectures (EBSA110 and CATS), there is currently no way | |
1946 | for the boot loader to pass arguments to the kernel. For these | |
1947 | architectures, you should supply some command-line options at build | |
1948 | time by entering them here. As a minimum, you should specify the | |
1949 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1950 | ||
4394c124 VB |
1951 | choice |
1952 | prompt "Kernel command line type" if CMDLINE != "" | |
1953 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 1954 | depends on ATAGS |
4394c124 VB |
1955 | |
1956 | config CMDLINE_FROM_BOOTLOADER | |
1957 | bool "Use bootloader kernel arguments if available" | |
1958 | help | |
1959 | Uses the command-line options passed by the boot loader. If | |
1960 | the boot loader doesn't provide any, the default kernel command | |
1961 | string provided in CMDLINE will be used. | |
1962 | ||
1963 | config CMDLINE_EXTEND | |
1964 | bool "Extend bootloader kernel arguments" | |
1965 | help | |
1966 | The command-line arguments provided by the boot loader will be | |
1967 | appended to the default kernel command string. | |
1968 | ||
92d2040d AH |
1969 | config CMDLINE_FORCE |
1970 | bool "Always use the default kernel command string" | |
92d2040d AH |
1971 | help |
1972 | Always use the default kernel command string, even if the boot | |
1973 | loader passes other arguments to the kernel. | |
1974 | This is useful if you cannot or don't want to change the | |
1975 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1976 | endchoice |
92d2040d | 1977 | |
1da177e4 LT |
1978 | config XIP_KERNEL |
1979 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1980 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
1981 | help |
1982 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1983 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1984 | space since the text section of the kernel is not loaded from flash | |
1985 | to RAM. Read-write sections, such as the data section and stack, | |
1986 | are still copied to RAM. The XIP kernel is not compressed since | |
1987 | it has to run directly from flash, so it will take more space to | |
1988 | store it. The flash address used to link the kernel object files, | |
1989 | and for storing it, is configuration dependent. Therefore, if you | |
1990 | say Y here, you must know the proper physical address where to | |
1991 | store the kernel image depending on your own flash memory usage. | |
1992 | ||
1993 | Also note that the make target becomes "make xipImage" rather than | |
1994 | "make zImage" or "make Image". The final kernel binary to put in | |
1995 | ROM memory will be arch/arm/boot/xipImage. | |
1996 | ||
1997 | If unsure, say N. | |
1998 | ||
1999 | config XIP_PHYS_ADDR | |
2000 | hex "XIP Kernel Physical Location" | |
2001 | depends on XIP_KERNEL | |
2002 | default "0x00080000" | |
2003 | help | |
2004 | This is the physical address in your flash memory the kernel will | |
2005 | be linked for and stored to. This address is dependent on your | |
2006 | own flash usage. | |
2007 | ||
c587e4a6 RP |
2008 | config KEXEC |
2009 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 2010 | depends on (!SMP || PM_SLEEP_SMP) |
cb1293e2 | 2011 | depends on !CPU_V7M |
2965faa5 | 2012 | select KEXEC_CORE |
c587e4a6 RP |
2013 | help |
2014 | kexec is a system call that implements the ability to shutdown your | |
2015 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 2016 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
2017 | you can start any kernel with it, not just Linux. |
2018 | ||
2019 | It is an ongoing process to be certain the hardware in a machine | |
2020 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 2021 | initially work for you. |
c587e4a6 | 2022 | |
4cd9d6f7 RP |
2023 | config ATAGS_PROC |
2024 | bool "Export atags in procfs" | |
bd51e2f5 | 2025 | depends on ATAGS && KEXEC |
b98d7291 | 2026 | default y |
4cd9d6f7 RP |
2027 | help |
2028 | Should the atags used to boot the kernel be exported in an "atags" | |
2029 | file in procfs. Useful with kexec. | |
2030 | ||
cb5d39b3 MW |
2031 | config CRASH_DUMP |
2032 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
2033 | help |
2034 | Generate crash dump after being started by kexec. This should | |
2035 | be normally only set in special crash dump kernels which are | |
2036 | loaded in the main kernel with kexec-tools into a specially | |
2037 | reserved region and then later executed after a crash by | |
2038 | kdump/kexec. The crash dump kernel must be compiled to a | |
2039 | memory address not used by the main kernel | |
2040 | ||
2041 | For more details see Documentation/kdump/kdump.txt | |
2042 | ||
e69edc79 EM |
2043 | config AUTO_ZRELADDR |
2044 | bool "Auto calculation of the decompressed kernel image address" | |
e69edc79 EM |
2045 | help |
2046 | ZRELADDR is the physical address where the decompressed kernel | |
2047 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2048 | will be determined at run-time by masking the current IP with | |
2049 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2050 | from start of memory. | |
2051 | ||
81a0bc39 RF |
2052 | config EFI_STUB |
2053 | bool | |
2054 | ||
2055 | config EFI | |
2056 | bool "UEFI runtime support" | |
2057 | depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL | |
2058 | select UCS2_STRING | |
2059 | select EFI_PARAMS_FROM_FDT | |
2060 | select EFI_STUB | |
2061 | select EFI_ARMSTUB | |
2062 | select EFI_RUNTIME_WRAPPERS | |
2063 | ---help--- | |
2064 | This option provides support for runtime services provided | |
2065 | by UEFI firmware (such as non-volatile variables, realtime | |
2066 | clock, and platform reset). A UEFI stub is also provided to | |
2067 | allow the kernel to be booted as an EFI application. This | |
2068 | is only useful for kernels that may run on systems that have | |
2069 | UEFI firmware. | |
2070 | ||
bb817bef AB |
2071 | config DMI |
2072 | bool "Enable support for SMBIOS (DMI) tables" | |
2073 | depends on EFI | |
2074 | default y | |
2075 | help | |
2076 | This enables SMBIOS/DMI feature for systems. | |
2077 | ||
2078 | This option is only useful on systems that have UEFI firmware. | |
2079 | However, even with this option, the resultant kernel should | |
2080 | continue to boot on existing non-UEFI platforms. | |
2081 | ||
2082 | NOTE: This does *NOT* enable or encourage the use of DMI quirks, | |
2083 | i.e., the the practice of identifying the platform via DMI to | |
2084 | decide whether certain workarounds for buggy hardware and/or | |
2085 | firmware need to be enabled. This would require the DMI subsystem | |
2086 | to be enabled much earlier than we do on ARM, which is non-trivial. | |
2087 | ||
1da177e4 LT |
2088 | endmenu |
2089 | ||
ac9d7efc | 2090 | menu "CPU Power Management" |
1da177e4 | 2091 | |
1da177e4 | 2092 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 2093 | |
ac9d7efc RK |
2094 | source "drivers/cpuidle/Kconfig" |
2095 | ||
2096 | endmenu | |
2097 | ||
1da177e4 LT |
2098 | menu "Floating point emulation" |
2099 | ||
2100 | comment "At least one emulation must be selected" | |
2101 | ||
2102 | config FPE_NWFPE | |
2103 | bool "NWFPE math emulation" | |
593c252a | 2104 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2105 | ---help--- |
2106 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2107 | This is necessary to run most binaries. Linux does not currently | |
2108 | support floating point hardware so you need to say Y here even if | |
2109 | your machine has an FPA or floating point co-processor podule. | |
2110 | ||
2111 | You may say N here if you are going to load the Acorn FPEmulator | |
2112 | early in the bootup. | |
2113 | ||
2114 | config FPE_NWFPE_XP | |
2115 | bool "Support extended precision" | |
bedf142b | 2116 | depends on FPE_NWFPE |
1da177e4 LT |
2117 | help |
2118 | Say Y to include 80-bit support in the kernel floating-point | |
2119 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2120 | Note that gcc does not generate 80-bit operations by default, | |
2121 | so in most cases this option only enlarges the size of the | |
2122 | floating point emulator without any good reason. | |
2123 | ||
2124 | You almost surely want to say N here. | |
2125 | ||
2126 | config FPE_FASTFPE | |
2127 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 2128 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
1da177e4 LT |
2129 | ---help--- |
2130 | Say Y here to include the FAST floating point emulator in the kernel. | |
2131 | This is an experimental much faster emulator which now also has full | |
2132 | precision for the mantissa. It does not support any exceptions. | |
2133 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2134 | ||
2135 | It should be sufficient for most programs. It may be not suitable | |
2136 | for scientific calculations, but you have to check this for yourself. | |
2137 | If you do not feel you need a faster FP emulation you should better | |
2138 | choose NWFPE. | |
2139 | ||
2140 | config VFP | |
2141 | bool "VFP-format floating point maths" | |
e399b1a4 | 2142 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2143 | help |
2144 | Say Y to include VFP support code in the kernel. This is needed | |
2145 | if your hardware includes a VFP unit. | |
2146 | ||
2147 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2148 | release notes and additional status information. | |
2149 | ||
2150 | Say N if your target does not have VFP hardware. | |
2151 | ||
25ebee02 CM |
2152 | config VFPv3 |
2153 | bool | |
2154 | depends on VFP | |
2155 | default y if CPU_V7 | |
2156 | ||
b5872db4 CM |
2157 | config NEON |
2158 | bool "Advanced SIMD (NEON) Extension support" | |
2159 | depends on VFPv3 && CPU_V7 | |
2160 | help | |
2161 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2162 | Extension. | |
2163 | ||
73c132c1 AB |
2164 | config KERNEL_MODE_NEON |
2165 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 2166 | depends on NEON && AEABI |
73c132c1 AB |
2167 | help |
2168 | Say Y to include support for NEON in kernel mode. | |
2169 | ||
1da177e4 LT |
2170 | endmenu |
2171 | ||
2172 | menu "Userspace binary formats" | |
2173 | ||
2174 | source "fs/Kconfig.binfmt" | |
2175 | ||
1da177e4 LT |
2176 | endmenu |
2177 | ||
2178 | menu "Power management options" | |
2179 | ||
eceab4ac | 2180 | source "kernel/power/Kconfig" |
1da177e4 | 2181 | |
f4cb5700 | 2182 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 2183 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 2184 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2185 | def_bool y |
2186 | ||
15e0d9e3 | 2187 | config ARM_CPU_SUSPEND |
8b6f2499 | 2188 | def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW |
1b9bdf5c | 2189 | depends on ARCH_SUSPEND_POSSIBLE |
15e0d9e3 | 2190 | |
603fb42a SC |
2191 | config ARCH_HIBERNATION_POSSIBLE |
2192 | bool | |
2193 | depends on MMU | |
2194 | default y if ARCH_SUSPEND_POSSIBLE | |
2195 | ||
1da177e4 LT |
2196 | endmenu |
2197 | ||
d5950b43 SR |
2198 | source "net/Kconfig" |
2199 | ||
ac25150f | 2200 | source "drivers/Kconfig" |
1da177e4 | 2201 | |
916f743d KG |
2202 | source "drivers/firmware/Kconfig" |
2203 | ||
1da177e4 LT |
2204 | source "fs/Kconfig" |
2205 | ||
1da177e4 LT |
2206 | source "arch/arm/Kconfig.debug" |
2207 | ||
2208 | source "security/Kconfig" | |
2209 | ||
2210 | source "crypto/Kconfig" | |
652ccae5 AB |
2211 | if CRYPTO |
2212 | source "arch/arm/crypto/Kconfig" | |
2213 | endif | |
1da177e4 LT |
2214 | |
2215 | source "lib/Kconfig" | |
749cf76c CD |
2216 | |
2217 | source "arch/arm/kvm/Kconfig" |