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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | config ARM |
2 | bool | |
3 | default y | |
b1b3f49c RK |
4 | select ARCH_BINFMT_ELF_RANDOMIZE_PIE |
5 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE | |
7563bbf8 | 6 | select ARCH_HAVE_CUSTOM_GPIO_H |
3d06770e | 7 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
b1b3f49c | 8 | select ARCH_WANT_IPC_PARSE_VERSION |
ee951c63 | 9 | select BUILDTIME_EXTABLE_SORT if MMU |
b1b3f49c | 10 | select CPU_PM if (SUSPEND || CPU_IDLE) |
39b175a0 | 11 | select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU |
a41297a0 | 12 | select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) |
b1b3f49c RK |
13 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
14 | select GENERIC_IRQ_PROBE | |
15 | select GENERIC_IRQ_SHOW | |
b1b3f49c RK |
16 | select GENERIC_PCI_IOMAP |
17 | select GENERIC_SMP_IDLE_THREAD | |
f7b861b7 | 18 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
19 | select GENERIC_STRNCPY_FROM_USER |
20 | select GENERIC_STRNLEN_USER | |
21 | select HARDIRQS_SW_RESEND | |
22 | select HAVE_AOUT | |
09f05d85 | 23 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL |
5cbad0eb | 24 | select HAVE_ARCH_KGDB |
4095ccc3 | 25 | select HAVE_ARCH_SECCOMP_FILTER |
0693bf68 | 26 | select HAVE_ARCH_TRACEHOOK |
b1b3f49c RK |
27 | select HAVE_BPF_JIT |
28 | select HAVE_C_RECORDMCOUNT | |
29 | select HAVE_DEBUG_KMEMLEAK | |
30 | select HAVE_DMA_API_DEBUG | |
31 | select HAVE_DMA_ATTRS | |
32 | select HAVE_DMA_CONTIGUOUS if MMU | |
80be7a7f | 33 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) |
b1b3f49c | 34 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
0e341af8 | 35 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
b1b3f49c | 36 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
1fe53268 | 37 | select HAVE_GENERIC_DMA_COHERENT |
b1b3f49c RK |
38 | select HAVE_GENERIC_HARDIRQS |
39 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) | |
40 | select HAVE_IDE if PCI || ISA || PCMCIA | |
87c46b6c | 41 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 42 | select HAVE_KERNEL_GZIP |
6e8699f7 | 43 | select HAVE_KERNEL_LZMA |
b1b3f49c | 44 | select HAVE_KERNEL_LZO |
a7f464f3 | 45 | select HAVE_KERNEL_XZ |
b1b3f49c RK |
46 | select HAVE_KPROBES if !XIP_KERNEL |
47 | select HAVE_KRETPROBES if (HAVE_KPROBES) | |
48 | select HAVE_MEMBLOCK | |
49 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) | |
7ada189f | 50 | select HAVE_PERF_EVENTS |
e513f8bf | 51 | select HAVE_REGS_AND_STACK_ACCESS_API |
b1b3f49c | 52 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 53 | select HAVE_UID16 |
3d92a71a | 54 | select KTIME_SCALAR |
b1b3f49c RK |
55 | select PERF_USE_VMALLOC |
56 | select RTC_LIB | |
57 | select SYS_SUPPORTS_APM_EMULATION | |
786d35d4 DH |
58 | select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND |
59 | select MODULES_USE_ELF_REL | |
38a61b6b | 60 | select CLONE_BACKWARDS |
b68fec24 | 61 | select OLD_SIGSUSPEND3 |
50bcb7e4 | 62 | select OLD_SIGACTION |
b0088480 | 63 | select HAVE_CONTEXT_TRACKING |
1da177e4 LT |
64 | help |
65 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 66 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 67 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 68 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
69 | Europe. There is an ARM Linux project with a web page at |
70 | <http://www.arm.linux.org.uk/>. | |
71 | ||
74facffe RK |
72 | config ARM_HAS_SG_CHAIN |
73 | bool | |
74 | ||
4ce63fcd MS |
75 | config NEED_SG_DMA_LENGTH |
76 | bool | |
77 | ||
78 | config ARM_DMA_USE_IOMMU | |
4ce63fcd | 79 | bool |
b1b3f49c RK |
80 | select ARM_HAS_SG_CHAIN |
81 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 82 | |
60460abf SWK |
83 | if ARM_DMA_USE_IOMMU |
84 | ||
85 | config ARM_DMA_IOMMU_ALIGNMENT | |
86 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
87 | range 4 9 | |
88 | default 8 | |
89 | help | |
90 | DMA mapping framework by default aligns all buffers to the smallest | |
91 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
92 | size. This works well for buffers up to a few hundreds kilobytes, but | |
93 | for larger buffers it just a waste of address space. Drivers which has | |
94 | relatively small addressing window (like 64Mib) might run out of | |
95 | virtual space with just a few allocations. | |
96 | ||
97 | With this parameter you can specify the maximum PAGE_SIZE order for | |
98 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
99 | specified order. The order is expressed as a power of two multiplied | |
100 | by the PAGE_SIZE. | |
101 | ||
102 | endif | |
103 | ||
1a189b97 RK |
104 | config HAVE_PWM |
105 | bool | |
106 | ||
0b05da72 HUK |
107 | config MIGHT_HAVE_PCI |
108 | bool | |
109 | ||
75e7153a RB |
110 | config SYS_SUPPORTS_APM_EMULATION |
111 | bool | |
112 | ||
bc581770 LW |
113 | config HAVE_TCM |
114 | bool | |
115 | select GENERIC_ALLOCATOR | |
116 | ||
e119bfff RK |
117 | config HAVE_PROC_CPU |
118 | bool | |
119 | ||
5ea81769 AV |
120 | config NO_IOPORT |
121 | bool | |
5ea81769 | 122 | |
1da177e4 LT |
123 | config EISA |
124 | bool | |
125 | ---help--- | |
126 | The Extended Industry Standard Architecture (EISA) bus was | |
127 | developed as an open alternative to the IBM MicroChannel bus. | |
128 | ||
129 | The EISA bus provided some of the features of the IBM MicroChannel | |
130 | bus while maintaining backward compatibility with cards made for | |
131 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
132 | 1995 when it was made obsolete by the PCI bus. | |
133 | ||
134 | Say Y here if you are building a kernel for an EISA-based machine. | |
135 | ||
136 | Otherwise, say N. | |
137 | ||
138 | config SBUS | |
139 | bool | |
140 | ||
f16fb1ec RK |
141 | config STACKTRACE_SUPPORT |
142 | bool | |
143 | default y | |
144 | ||
f76e9154 NP |
145 | config HAVE_LATENCYTOP_SUPPORT |
146 | bool | |
147 | depends on !SMP | |
148 | default y | |
149 | ||
f16fb1ec RK |
150 | config LOCKDEP_SUPPORT |
151 | bool | |
152 | default y | |
153 | ||
7ad1bcb2 RK |
154 | config TRACE_IRQFLAGS_SUPPORT |
155 | bool | |
156 | default y | |
157 | ||
1da177e4 LT |
158 | config RWSEM_GENERIC_SPINLOCK |
159 | bool | |
160 | default y | |
161 | ||
162 | config RWSEM_XCHGADD_ALGORITHM | |
163 | bool | |
164 | ||
f0d1b0b3 DH |
165 | config ARCH_HAS_ILOG2_U32 |
166 | bool | |
f0d1b0b3 DH |
167 | |
168 | config ARCH_HAS_ILOG2_U64 | |
169 | bool | |
f0d1b0b3 | 170 | |
89c52ed4 BD |
171 | config ARCH_HAS_CPUFREQ |
172 | bool | |
173 | help | |
174 | Internal node to signify that the ARCH has CPUFREQ support | |
175 | and that the relevant menu configurations are displayed for | |
176 | it. | |
177 | ||
b89c3b16 AM |
178 | config GENERIC_HWEIGHT |
179 | bool | |
180 | default y | |
181 | ||
1da177e4 LT |
182 | config GENERIC_CALIBRATE_DELAY |
183 | bool | |
184 | default y | |
185 | ||
a08b6b79 AV |
186 | config ARCH_MAY_HAVE_PC_FDC |
187 | bool | |
188 | ||
5ac6da66 CL |
189 | config ZONE_DMA |
190 | bool | |
5ac6da66 | 191 | |
ccd7ab7f FT |
192 | config NEED_DMA_MAP_STATE |
193 | def_bool y | |
194 | ||
58af4a24 RH |
195 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
196 | bool | |
197 | ||
1da177e4 LT |
198 | config GENERIC_ISA_DMA |
199 | bool | |
200 | ||
1da177e4 LT |
201 | config FIQ |
202 | bool | |
203 | ||
13a5045d RH |
204 | config NEED_RET_TO_USER |
205 | bool | |
206 | ||
034d2f5a AV |
207 | config ARCH_MTD_XIP |
208 | bool | |
209 | ||
c760fc19 HC |
210 | config VECTORS_BASE |
211 | hex | |
6afd6fae | 212 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR |
c760fc19 HC |
213 | default DRAM_BASE if REMAP_VECTORS_TO_RAM |
214 | default 0x00000000 | |
215 | help | |
216 | The base address of exception vectors. | |
217 | ||
dc21af99 | 218 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
219 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
220 | default y | |
b511d75d | 221 | depends on !XIP_KERNEL && MMU |
dc21af99 RK |
222 | depends on !ARCH_REALVIEW || !SPARSEMEM |
223 | help | |
111e9a5c RK |
224 | Patch phys-to-virt and virt-to-phys translation functions at |
225 | boot and module load time according to the position of the | |
226 | kernel in system memory. | |
dc21af99 | 227 | |
111e9a5c | 228 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 229 | of physical memory is at a 16MB boundary. |
dc21af99 | 230 | |
c1becedc RK |
231 | Only disable this option if you know that you do not require |
232 | this feature (eg, building a kernel for a single machine) and | |
233 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 234 | |
01464226 RH |
235 | config NEED_MACH_GPIO_H |
236 | bool | |
237 | help | |
238 | Select this when mach/gpio.h is required to provide special | |
239 | definitions for this platform. The need for mach/gpio.h should | |
240 | be avoided when possible. | |
241 | ||
c334bc15 RH |
242 | config NEED_MACH_IO_H |
243 | bool | |
244 | help | |
245 | Select this when mach/io.h is required to provide special | |
246 | definitions for this platform. The need for mach/io.h should | |
247 | be avoided when possible. | |
248 | ||
0cdc8b92 | 249 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
250 | bool |
251 | help | |
0cdc8b92 NP |
252 | Select this when mach/memory.h is required to provide special |
253 | definitions for this platform. The need for mach/memory.h should | |
254 | be avoided when possible. | |
dc21af99 | 255 | |
1b9f95f8 | 256 | config PHYS_OFFSET |
974c0724 | 257 | hex "Physical address of main memory" if MMU |
0cdc8b92 | 258 | depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H |
974c0724 | 259 | default DRAM_BASE if !MMU |
111e9a5c | 260 | help |
1b9f95f8 NP |
261 | Please provide the physical address corresponding to the |
262 | location of main memory in your system. | |
cada3c08 | 263 | |
87e040b6 SG |
264 | config GENERIC_BUG |
265 | def_bool y | |
266 | depends on BUG | |
267 | ||
1da177e4 LT |
268 | source "init/Kconfig" |
269 | ||
dc52ddc0 MH |
270 | source "kernel/Kconfig.freezer" |
271 | ||
1da177e4 LT |
272 | menu "System Type" |
273 | ||
3c427975 HC |
274 | config MMU |
275 | bool "MMU-based Paged Memory Management Support" | |
276 | default y | |
277 | help | |
278 | Select if you want MMU-based virtualised addressing space | |
279 | support by paged memory management. If unsure, say 'Y'. | |
280 | ||
ccf50e23 RK |
281 | # |
282 | # The "ARM system type" choice list is ordered alphabetically by option | |
283 | # text. Please add new entries in the option alphabetic order. | |
284 | # | |
1da177e4 LT |
285 | choice |
286 | prompt "ARM system type" | |
1420b22b AB |
287 | default ARCH_VERSATILE if !MMU |
288 | default ARCH_MULTIPLATFORM if MMU | |
1da177e4 | 289 | |
387798b3 RH |
290 | config ARCH_MULTIPLATFORM |
291 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 292 | depends on MMU |
387798b3 RH |
293 | select ARM_PATCH_PHYS_VIRT |
294 | select AUTO_ZRELADDR | |
66314223 | 295 | select COMMON_CLK |
387798b3 | 296 | select MULTI_IRQ_HANDLER |
66314223 DN |
297 | select SPARSE_IRQ |
298 | select USE_OF | |
66314223 | 299 | |
4af6fee1 DS |
300 | config ARCH_INTEGRATOR |
301 | bool "ARM Ltd. Integrator family" | |
89c52ed4 | 302 | select ARCH_HAS_CPUFREQ |
b1b3f49c | 303 | select ARM_AMBA |
a613163d | 304 | select COMMON_CLK |
f9a6aa43 | 305 | select COMMON_CLK_VERSATILE |
b1b3f49c | 306 | select GENERIC_CLOCKEVENTS |
9904f793 | 307 | select HAVE_TCM |
c5a0adb5 | 308 | select ICST |
b1b3f49c RK |
309 | select MULTI_IRQ_HANDLER |
310 | select NEED_MACH_MEMORY_H | |
f4b8b319 | 311 | select PLAT_VERSATILE |
695436e3 | 312 | select SPARSE_IRQ |
2389d501 | 313 | select VERSATILE_FPGA_IRQ |
4af6fee1 DS |
314 | help |
315 | Support for ARM's Integrator platform. | |
316 | ||
317 | config ARCH_REALVIEW | |
318 | bool "ARM Ltd. RealView family" | |
b1b3f49c | 319 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 320 | select ARM_AMBA |
b1b3f49c | 321 | select ARM_TIMER_SP804 |
f9a6aa43 LW |
322 | select COMMON_CLK |
323 | select COMMON_CLK_VERSATILE | |
ae30ceac | 324 | select GENERIC_CLOCKEVENTS |
b56ba8aa | 325 | select GPIO_PL061 if GPIOLIB |
b1b3f49c | 326 | select ICST |
0cdc8b92 | 327 | select NEED_MACH_MEMORY_H |
b1b3f49c RK |
328 | select PLAT_VERSATILE |
329 | select PLAT_VERSATILE_CLCD | |
4af6fee1 DS |
330 | help |
331 | This enables support for ARM Ltd RealView boards. | |
332 | ||
333 | config ARCH_VERSATILE | |
334 | bool "ARM Ltd. Versatile family" | |
b1b3f49c | 335 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 336 | select ARM_AMBA |
b1b3f49c | 337 | select ARM_TIMER_SP804 |
4af6fee1 | 338 | select ARM_VIC |
6d803ba7 | 339 | select CLKDEV_LOOKUP |
b1b3f49c | 340 | select GENERIC_CLOCKEVENTS |
aa3831cf | 341 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 342 | select ICST |
f4b8b319 | 343 | select PLAT_VERSATILE |
3414ba8c | 344 | select PLAT_VERSATILE_CLCD |
b1b3f49c | 345 | select PLAT_VERSATILE_CLOCK |
2389d501 | 346 | select VERSATILE_FPGA_IRQ |
4af6fee1 DS |
347 | help |
348 | This enables support for ARM Ltd Versatile board. | |
349 | ||
8fc5ffa0 AV |
350 | config ARCH_AT91 |
351 | bool "Atmel AT91" | |
f373e8c0 | 352 | select ARCH_REQUIRE_GPIOLIB |
bd602995 | 353 | select CLKDEV_LOOKUP |
b1b3f49c | 354 | select HAVE_CLK |
e261501d | 355 | select IRQ_DOMAIN |
01464226 | 356 | select NEED_MACH_GPIO_H |
1ac02d79 | 357 | select NEED_MACH_IO_H if PCCARD |
6732ae5c JCPV |
358 | select PINCTRL |
359 | select PINCTRL_AT91 if USE_OF | |
4af6fee1 | 360 | help |
929e994f NF |
361 | This enables support for systems based on Atmel |
362 | AT91RM9200 and AT91SAM9* processors. | |
4af6fee1 | 363 | |
93e22567 RK |
364 | config ARCH_CLPS711X |
365 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" | |
a3b8d4a5 | 366 | select ARCH_REQUIRE_GPIOLIB |
ea7d1bc9 | 367 | select AUTO_ZRELADDR |
93e22567 RK |
368 | select CLKDEV_LOOKUP |
369 | select COMMON_CLK | |
370 | select CPU_ARM720T | |
4a8355c4 | 371 | select GENERIC_CLOCKEVENTS |
99f04c8f | 372 | select MULTI_IRQ_HANDLER |
93e22567 | 373 | select NEED_MACH_MEMORY_H |
0d8be81c | 374 | select SPARSE_IRQ |
93e22567 RK |
375 | help |
376 | Support for Cirrus Logic 711x/721x/731x based boards. | |
377 | ||
788c9700 RK |
378 | config ARCH_GEMINI |
379 | bool "Cortina Systems Gemini" | |
788c9700 | 380 | select ARCH_REQUIRE_GPIOLIB |
5cfc8ee0 | 381 | select ARCH_USES_GETTIMEOFFSET |
662146b1 | 382 | select NEED_MACH_GPIO_H |
b1b3f49c | 383 | select CPU_FA526 |
788c9700 RK |
384 | help |
385 | Support for the Cortina Systems Gemini family SoCs | |
386 | ||
1da177e4 LT |
387 | config ARCH_EBSA110 |
388 | bool "EBSA-110" | |
b1b3f49c | 389 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 390 | select CPU_SA110 |
f7e68bbf | 391 | select ISA |
c334bc15 | 392 | select NEED_MACH_IO_H |
0cdc8b92 | 393 | select NEED_MACH_MEMORY_H |
b1b3f49c | 394 | select NO_IOPORT |
1da177e4 LT |
395 | help |
396 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 397 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
398 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
399 | parallel port. | |
400 | ||
e7736d47 LB |
401 | config ARCH_EP93XX |
402 | bool "EP93xx-based" | |
b1b3f49c RK |
403 | select ARCH_HAS_HOLES_MEMORYMODEL |
404 | select ARCH_REQUIRE_GPIOLIB | |
405 | select ARCH_USES_GETTIMEOFFSET | |
e7736d47 LB |
406 | select ARM_AMBA |
407 | select ARM_VIC | |
6d803ba7 | 408 | select CLKDEV_LOOKUP |
b1b3f49c | 409 | select CPU_ARM920T |
5725aeae | 410 | select NEED_MACH_MEMORY_H |
e7736d47 LB |
411 | help |
412 | This enables support for the Cirrus EP93xx series of CPUs. | |
413 | ||
1da177e4 LT |
414 | config ARCH_FOOTBRIDGE |
415 | bool "FootBridge" | |
c750815e | 416 | select CPU_SA110 |
1da177e4 | 417 | select FOOTBRIDGE |
4e8d7637 | 418 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 419 | select HAVE_IDE |
8ef6e620 | 420 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 421 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
422 | help |
423 | Support for systems based on the DC21285 companion chip | |
424 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 425 | |
4af6fee1 DS |
426 | config ARCH_NETX |
427 | bool "Hilscher NetX based" | |
b1b3f49c | 428 | select ARM_VIC |
234b6ced | 429 | select CLKSRC_MMIO |
c750815e | 430 | select CPU_ARM926T |
2fcfe6b8 | 431 | select GENERIC_CLOCKEVENTS |
f999b8bd | 432 | help |
4af6fee1 DS |
433 | This enables support for systems based on the Hilscher NetX Soc |
434 | ||
3b938be6 RK |
435 | config ARCH_IOP13XX |
436 | bool "IOP13xx-based" | |
437 | depends on MMU | |
3b938be6 | 438 | select ARCH_SUPPORTS_MSI |
b1b3f49c | 439 | select CPU_XSC3 |
0cdc8b92 | 440 | select NEED_MACH_MEMORY_H |
13a5045d | 441 | select NEED_RET_TO_USER |
b1b3f49c RK |
442 | select PCI |
443 | select PLAT_IOP | |
444 | select VMSPLIT_1G | |
3b938be6 RK |
445 | help |
446 | Support for Intel's IOP13XX (XScale) family of processors. | |
447 | ||
3f7e5815 LB |
448 | config ARCH_IOP32X |
449 | bool "IOP32x-based" | |
a4f7e763 | 450 | depends on MMU |
b1b3f49c | 451 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 452 | select CPU_XSCALE |
01464226 | 453 | select NEED_MACH_GPIO_H |
13a5045d | 454 | select NEED_RET_TO_USER |
f7e68bbf | 455 | select PCI |
b1b3f49c | 456 | select PLAT_IOP |
f999b8bd | 457 | help |
3f7e5815 LB |
458 | Support for Intel's 80219 and IOP32X (XScale) family of |
459 | processors. | |
460 | ||
461 | config ARCH_IOP33X | |
462 | bool "IOP33x-based" | |
463 | depends on MMU | |
b1b3f49c | 464 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 465 | select CPU_XSCALE |
01464226 | 466 | select NEED_MACH_GPIO_H |
13a5045d | 467 | select NEED_RET_TO_USER |
3f7e5815 | 468 | select PCI |
b1b3f49c | 469 | select PLAT_IOP |
3f7e5815 LB |
470 | help |
471 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 472 | |
3b938be6 RK |
473 | config ARCH_IXP4XX |
474 | bool "IXP4xx-based" | |
a4f7e763 | 475 | depends on MMU |
58af4a24 | 476 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
b1b3f49c | 477 | select ARCH_REQUIRE_GPIOLIB |
234b6ced | 478 | select CLKSRC_MMIO |
c750815e | 479 | select CPU_XSCALE |
b1b3f49c | 480 | select DMABOUNCE if PCI |
3b938be6 | 481 | select GENERIC_CLOCKEVENTS |
0b05da72 | 482 | select MIGHT_HAVE_PCI |
c334bc15 | 483 | select NEED_MACH_IO_H |
9296d94d FF |
484 | select USB_EHCI_BIG_ENDIAN_MMIO |
485 | select USB_EHCI_BIG_ENDIAN_DESC | |
c4713074 | 486 | help |
3b938be6 | 487 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 488 | |
edabd38e SB |
489 | config ARCH_DOVE |
490 | bool "Marvell Dove" | |
edabd38e | 491 | select ARCH_REQUIRE_GPIOLIB |
756b2531 | 492 | select CPU_PJ4 |
edabd38e | 493 | select GENERIC_CLOCKEVENTS |
0f81bd43 | 494 | select MIGHT_HAVE_PCI |
9139acd1 SH |
495 | select PINCTRL |
496 | select PINCTRL_DOVE | |
abcda1dc | 497 | select PLAT_ORION_LEGACY |
0f81bd43 | 498 | select USB_ARCH_HAS_EHCI |
7d554902 | 499 | select MVEBU_MBUS |
edabd38e SB |
500 | help |
501 | Support for the Marvell Dove SoC 88AP510 | |
502 | ||
651c74c7 SB |
503 | config ARCH_KIRKWOOD |
504 | bool "Marvell Kirkwood" | |
a8865655 | 505 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 506 | select CPU_FEROCEON |
651c74c7 | 507 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 508 | select PCI |
1dc831bf | 509 | select PCI_QUIRKS |
f9e75922 AL |
510 | select PINCTRL |
511 | select PINCTRL_KIRKWOOD | |
abcda1dc | 512 | select PLAT_ORION_LEGACY |
5cc0673a | 513 | select MVEBU_MBUS |
651c74c7 SB |
514 | help |
515 | Support for the following Marvell Kirkwood series SoCs: | |
516 | 88F6180, 88F6192 and 88F6281. | |
517 | ||
794d15b2 SS |
518 | config ARCH_MV78XX0 |
519 | bool "Marvell MV78xx0" | |
a8865655 | 520 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 521 | select CPU_FEROCEON |
794d15b2 | 522 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 523 | select PCI |
abcda1dc | 524 | select PLAT_ORION_LEGACY |
95b80e0a | 525 | select MVEBU_MBUS |
794d15b2 SS |
526 | help |
527 | Support for the following Marvell MV78xx0 series SoCs: | |
528 | MV781x0, MV782x0. | |
529 | ||
9dd0b194 | 530 | config ARCH_ORION5X |
585cf175 TP |
531 | bool "Marvell Orion" |
532 | depends on MMU | |
a8865655 | 533 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 534 | select CPU_FEROCEON |
51cbff1d | 535 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 536 | select PCI |
abcda1dc | 537 | select PLAT_ORION_LEGACY |
5d1190ea | 538 | select MVEBU_MBUS |
585cf175 | 539 | help |
9dd0b194 | 540 | Support for the following Marvell Orion 5x series SoCs: |
d2b2a6bb | 541 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), |
d323ade1 | 542 | Orion-2 (5281), Orion-1-90 (6183). |
585cf175 | 543 | |
788c9700 | 544 | config ARCH_MMP |
2f7e8fae | 545 | bool "Marvell PXA168/910/MMP2" |
788c9700 | 546 | depends on MMU |
788c9700 | 547 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 548 | select CLKDEV_LOOKUP |
b1b3f49c | 549 | select GENERIC_ALLOCATOR |
788c9700 | 550 | select GENERIC_CLOCKEVENTS |
157d2644 | 551 | select GPIO_PXA |
c24b3114 | 552 | select IRQ_DOMAIN |
b1b3f49c | 553 | select NEED_MACH_GPIO_H |
7c8f86a4 | 554 | select PINCTRL |
788c9700 | 555 | select PLAT_PXA |
0bd86961 | 556 | select SPARSE_IRQ |
788c9700 | 557 | help |
2f7e8fae | 558 | Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. |
788c9700 RK |
559 | |
560 | config ARCH_KS8695 | |
561 | bool "Micrel/Kendin KS8695" | |
98830bc9 | 562 | select ARCH_REQUIRE_GPIOLIB |
c7e783d6 | 563 | select CLKSRC_MMIO |
b1b3f49c | 564 | select CPU_ARM922T |
c7e783d6 | 565 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 566 | select NEED_MACH_MEMORY_H |
788c9700 RK |
567 | help |
568 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
569 | System-on-Chip devices. | |
570 | ||
788c9700 RK |
571 | config ARCH_W90X900 |
572 | bool "Nuvoton W90X900 CPU" | |
c52d3d68 | 573 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 574 | select CLKDEV_LOOKUP |
6fa5d5f7 | 575 | select CLKSRC_MMIO |
b1b3f49c | 576 | select CPU_ARM926T |
58b5369e | 577 | select GENERIC_CLOCKEVENTS |
788c9700 | 578 | help |
a8bc4ead | 579 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
580 | At present, the w90x900 has been renamed nuc900, regarding | |
581 | the ARM series product line, you can login the following | |
582 | link address to know more. | |
583 | ||
584 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
585 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 586 | |
93e22567 RK |
587 | config ARCH_LPC32XX |
588 | bool "NXP LPC32XX" | |
589 | select ARCH_REQUIRE_GPIOLIB | |
590 | select ARM_AMBA | |
591 | select CLKDEV_LOOKUP | |
592 | select CLKSRC_MMIO | |
593 | select CPU_ARM926T | |
594 | select GENERIC_CLOCKEVENTS | |
595 | select HAVE_IDE | |
596 | select HAVE_PWM | |
597 | select USB_ARCH_HAS_OHCI | |
598 | select USE_OF | |
599 | help | |
600 | Support for the NXP LPC32XX family of processors | |
601 | ||
1da177e4 | 602 | config ARCH_PXA |
2c8086a5 | 603 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 604 | depends on MMU |
89c52ed4 | 605 | select ARCH_HAS_CPUFREQ |
b1b3f49c RK |
606 | select ARCH_MTD_XIP |
607 | select ARCH_REQUIRE_GPIOLIB | |
608 | select ARM_CPU_SUSPEND if PM | |
609 | select AUTO_ZRELADDR | |
6d803ba7 | 610 | select CLKDEV_LOOKUP |
234b6ced | 611 | select CLKSRC_MMIO |
981d0f39 | 612 | select GENERIC_CLOCKEVENTS |
157d2644 | 613 | select GPIO_PXA |
d0ee9f40 | 614 | select HAVE_IDE |
b1b3f49c | 615 | select MULTI_IRQ_HANDLER |
01464226 | 616 | select NEED_MACH_GPIO_H |
b1b3f49c RK |
617 | select PLAT_PXA |
618 | select SPARSE_IRQ | |
f999b8bd | 619 | help |
2c8086a5 | 620 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 | 621 | |
788c9700 RK |
622 | config ARCH_MSM |
623 | bool "Qualcomm MSM" | |
923a081c | 624 | select ARCH_REQUIRE_GPIOLIB |
bd32344a | 625 | select CLKDEV_LOOKUP |
b1b3f49c RK |
626 | select GENERIC_CLOCKEVENTS |
627 | select HAVE_CLK | |
49cbe786 | 628 | help |
4b53eb4f DW |
629 | Support for Qualcomm MSM/QSD based systems. This runs on the |
630 | apps processor of the MSM/QSD and depends on a shared memory | |
631 | interface to the modem processor which runs the baseband | |
632 | stack and controls some vital subsystems | |
633 | (clock and power control, etc). | |
49cbe786 | 634 | |
c793c1b0 | 635 | config ARCH_SHMOBILE |
6d72ad35 | 636 | bool "Renesas SH-Mobile / R-Mobile" |
5e93c6b4 | 637 | select CLKDEV_LOOKUP |
b1b3f49c | 638 | select GENERIC_CLOCKEVENTS |
4c3ffffd SB |
639 | select HAVE_ARM_SCU if SMP |
640 | select HAVE_ARM_TWD if LOCAL_TIMERS | |
b1b3f49c | 641 | select HAVE_CLK |
aa3831cf | 642 | select HAVE_MACH_CLKDEV |
3b55658a | 643 | select HAVE_SMP |
ce5ea9f3 | 644 | select MIGHT_HAVE_CACHE_L2X0 |
60f1435c | 645 | select MULTI_IRQ_HANDLER |
0cdc8b92 | 646 | select NEED_MACH_MEMORY_H |
b1b3f49c | 647 | select NO_IOPORT |
6722f6cb | 648 | select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB |
b1b3f49c RK |
649 | select PM_GENERIC_DOMAINS if PM |
650 | select SPARSE_IRQ | |
c793c1b0 | 651 | help |
6d72ad35 | 652 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms. |
c793c1b0 | 653 | |
1da177e4 LT |
654 | config ARCH_RPC |
655 | bool "RiscPC" | |
656 | select ARCH_ACORN | |
a08b6b79 | 657 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 658 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 659 | select ARCH_USES_GETTIMEOFFSET |
b1b3f49c | 660 | select FIQ |
d0ee9f40 | 661 | select HAVE_IDE |
b1b3f49c RK |
662 | select HAVE_PATA_PLATFORM |
663 | select ISA_DMA_API | |
c334bc15 | 664 | select NEED_MACH_IO_H |
0cdc8b92 | 665 | select NEED_MACH_MEMORY_H |
b1b3f49c | 666 | select NO_IOPORT |
b4811bac | 667 | select VIRT_TO_BUS |
1da177e4 LT |
668 | help |
669 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
670 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
671 | ||
672 | config ARCH_SA1100 | |
673 | bool "SA1100-based" | |
89c52ed4 | 674 | select ARCH_HAS_CPUFREQ |
b1b3f49c RK |
675 | select ARCH_MTD_XIP |
676 | select ARCH_REQUIRE_GPIOLIB | |
677 | select ARCH_SPARSEMEM_ENABLE | |
678 | select CLKDEV_LOOKUP | |
679 | select CLKSRC_MMIO | |
1937f5b9 | 680 | select CPU_FREQ |
b1b3f49c | 681 | select CPU_SA1100 |
3e238be2 | 682 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 683 | select HAVE_IDE |
b1b3f49c | 684 | select ISA |
01464226 | 685 | select NEED_MACH_GPIO_H |
0cdc8b92 | 686 | select NEED_MACH_MEMORY_H |
375dec92 | 687 | select SPARSE_IRQ |
f999b8bd MM |
688 | help |
689 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 690 | |
b130d5c2 KK |
691 | config ARCH_S3C24XX |
692 | bool "Samsung S3C24XX SoCs" | |
9d56c02a | 693 | select ARCH_HAS_CPUFREQ |
53650430 | 694 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 695 | select CLKDEV_LOOKUP |
7f78b6eb RN |
696 | select CLKSRC_MMIO |
697 | select GENERIC_CLOCKEVENTS | |
b1b3f49c | 698 | select HAVE_CLK |
20676c15 | 699 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 | 700 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 701 | select HAVE_S3C_RTC if RTC_CLASS |
17453dd2 | 702 | select MULTI_IRQ_HANDLER |
01464226 | 703 | select NEED_MACH_GPIO_H |
c334bc15 | 704 | select NEED_MACH_IO_H |
cd8dc7ae | 705 | select SAMSUNG_ATAGS |
1da177e4 | 706 | help |
b130d5c2 KK |
707 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
708 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
709 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
710 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 711 | |
a08ab637 BD |
712 | config ARCH_S3C64XX |
713 | bool "Samsung S3C64XX" | |
b1b3f49c RK |
714 | select ARCH_HAS_CPUFREQ |
715 | select ARCH_REQUIRE_GPIOLIB | |
89f0ce72 | 716 | select ARM_VIC |
b1b3f49c | 717 | select CLKDEV_LOOKUP |
04a49b71 | 718 | select CLKSRC_MMIO |
b1b3f49c | 719 | select CPU_V6 |
04a49b71 | 720 | select GENERIC_CLOCKEVENTS |
a08ab637 | 721 | select HAVE_CLK |
b1b3f49c RK |
722 | select HAVE_S3C2410_I2C if I2C |
723 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
6700397a | 724 | select HAVE_TCM |
b1b3f49c | 725 | select NEED_MACH_GPIO_H |
89f0ce72 | 726 | select NO_IOPORT |
b1b3f49c RK |
727 | select PLAT_SAMSUNG |
728 | select S3C_DEV_NAND | |
729 | select S3C_GPIO_TRACK | |
cd8dc7ae | 730 | select SAMSUNG_ATAGS |
89f0ce72 | 731 | select SAMSUNG_CLKSRC |
b1b3f49c | 732 | select SAMSUNG_GPIOLIB_4BIT |
89f0ce72 | 733 | select SAMSUNG_IRQ_VIC_TIMER |
89f0ce72 | 734 | select USB_ARCH_HAS_OHCI |
a08ab637 BD |
735 | help |
736 | Samsung S3C64XX series based systems | |
737 | ||
49b7a491 KK |
738 | config ARCH_S5P64X0 |
739 | bool "Samsung S5P6440 S5P6450" | |
d8b22d25 | 740 | select CLKDEV_LOOKUP |
0665ccc4 | 741 | select CLKSRC_MMIO |
b1b3f49c | 742 | select CPU_V6 |
9e65bbf2 | 743 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 744 | select HAVE_CLK |
20676c15 | 745 | select HAVE_S3C2410_I2C if I2C |
b1b3f49c | 746 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
754961a8 | 747 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 748 | select NEED_MACH_GPIO_H |
cd8dc7ae | 749 | select SAMSUNG_ATAGS |
c4ffccdd | 750 | help |
49b7a491 KK |
751 | Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, |
752 | SMDK6450. | |
c4ffccdd | 753 | |
acc84707 MS |
754 | config ARCH_S5PC100 |
755 | bool "Samsung S5PC100" | |
53650430 | 756 | select ARCH_REQUIRE_GPIOLIB |
29e8eb0f | 757 | select CLKDEV_LOOKUP |
6a5a2e3b | 758 | select CLKSRC_MMIO |
5a7652f2 | 759 | select CPU_V7 |
6a5a2e3b | 760 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 761 | select HAVE_CLK |
20676c15 | 762 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 763 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 764 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 765 | select NEED_MACH_GPIO_H |
cd8dc7ae | 766 | select SAMSUNG_ATAGS |
5a7652f2 | 767 | help |
acc84707 | 768 | Samsung S5PC100 series based systems |
5a7652f2 | 769 | |
170f4e42 KK |
770 | config ARCH_S5PV210 |
771 | bool "Samsung S5PV210/S5PC110" | |
b1b3f49c | 772 | select ARCH_HAS_CPUFREQ |
0f75a96b | 773 | select ARCH_HAS_HOLES_MEMORYMODEL |
b1b3f49c | 774 | select ARCH_SPARSEMEM_ENABLE |
b2a9dd46 | 775 | select CLKDEV_LOOKUP |
0665ccc4 | 776 | select CLKSRC_MMIO |
b1b3f49c | 777 | select CPU_V7 |
9e65bbf2 | 778 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 779 | select HAVE_CLK |
20676c15 | 780 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 781 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 782 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 783 | select NEED_MACH_GPIO_H |
0cdc8b92 | 784 | select NEED_MACH_MEMORY_H |
cd8dc7ae | 785 | select SAMSUNG_ATAGS |
170f4e42 KK |
786 | help |
787 | Samsung S5PV210/S5PC110 series based systems | |
788 | ||
83014579 | 789 | config ARCH_EXYNOS |
93e22567 | 790 | bool "Samsung EXYNOS" |
b1b3f49c | 791 | select ARCH_HAS_CPUFREQ |
0f75a96b | 792 | select ARCH_HAS_HOLES_MEMORYMODEL |
b1b3f49c | 793 | select ARCH_SPARSEMEM_ENABLE |
badc4f2d | 794 | select CLKDEV_LOOKUP |
340fcb5c | 795 | select COMMON_CLK |
b1b3f49c | 796 | select CPU_V7 |
cc0e72b8 | 797 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 798 | select HAVE_CLK |
20676c15 | 799 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 800 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 801 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 802 | select NEED_MACH_GPIO_H |
0cdc8b92 | 803 | select NEED_MACH_MEMORY_H |
cd8dc7ae | 804 | select SAMSUNG_ATAGS |
f8b1ac01 | 805 | select USE_OF |
cc0e72b8 | 806 | help |
83014579 | 807 | Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) |
cc0e72b8 | 808 | |
1da177e4 LT |
809 | config ARCH_SHARK |
810 | bool "Shark" | |
b1b3f49c | 811 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 812 | select CPU_SA110 |
f7e68bbf RK |
813 | select ISA |
814 | select ISA_DMA | |
0cdc8b92 | 815 | select NEED_MACH_MEMORY_H |
b1b3f49c | 816 | select PCI |
b4811bac | 817 | select VIRT_TO_BUS |
b1b3f49c | 818 | select ZONE_DMA |
f999b8bd MM |
819 | help |
820 | Support for the StrongARM based Digital DNARD machine, also known | |
821 | as "Shark" (<http://www.shark-linux.de/shark.html>). | |
1da177e4 | 822 | |
d98aac75 LW |
823 | config ARCH_U300 |
824 | bool "ST-Ericsson U300 Series" | |
825 | depends on MMU | |
b1b3f49c | 826 | select ARCH_REQUIRE_GPIOLIB |
d98aac75 | 827 | select ARM_AMBA |
5485c1e0 | 828 | select ARM_PATCH_PHYS_VIRT |
d98aac75 | 829 | select ARM_VIC |
6d803ba7 | 830 | select CLKDEV_LOOKUP |
b1b3f49c | 831 | select CLKSRC_MMIO |
50667d63 | 832 | select COMMON_CLK |
b1b3f49c RK |
833 | select CPU_ARM926T |
834 | select GENERIC_CLOCKEVENTS | |
b1b3f49c | 835 | select HAVE_TCM |
a4fe292f | 836 | select SPARSE_IRQ |
d98aac75 LW |
837 | help |
838 | Support for ST-Ericsson U300 series mobile platforms. | |
839 | ||
7c6337e2 KH |
840 | config ARCH_DAVINCI |
841 | bool "TI DaVinci" | |
b1b3f49c | 842 | select ARCH_HAS_HOLES_MEMORYMODEL |
dce1115b | 843 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 844 | select CLKDEV_LOOKUP |
20e9969b | 845 | select GENERIC_ALLOCATOR |
b1b3f49c | 846 | select GENERIC_CLOCKEVENTS |
dc7ad3b3 | 847 | select GENERIC_IRQ_CHIP |
b1b3f49c | 848 | select HAVE_IDE |
01464226 | 849 | select NEED_MACH_GPIO_H |
689e331f | 850 | select USE_OF |
b1b3f49c | 851 | select ZONE_DMA |
7c6337e2 KH |
852 | help |
853 | Support for TI's DaVinci platform. | |
854 | ||
a0694861 TL |
855 | config ARCH_OMAP1 |
856 | bool "TI OMAP1" | |
00a36698 | 857 | depends on MMU |
89c52ed4 | 858 | select ARCH_HAS_CPUFREQ |
9af915da | 859 | select ARCH_HAS_HOLES_MEMORYMODEL |
a0694861 | 860 | select ARCH_OMAP |
21f47fbc | 861 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 862 | select CLKDEV_LOOKUP |
d6e15d78 | 863 | select CLKSRC_MMIO |
b1b3f49c | 864 | select GENERIC_CLOCKEVENTS |
a0694861 | 865 | select GENERIC_IRQ_CHIP |
e9a91de7 | 866 | select HAVE_CLK |
a0694861 TL |
867 | select HAVE_IDE |
868 | select IRQ_DOMAIN | |
869 | select NEED_MACH_IO_H if PCCARD | |
870 | select NEED_MACH_MEMORY_H | |
21f47fbc | 871 | help |
a0694861 | 872 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 873 | |
1da177e4 LT |
874 | endchoice |
875 | ||
387798b3 RH |
876 | menu "Multiple platform selection" |
877 | depends on ARCH_MULTIPLATFORM | |
878 | ||
879 | comment "CPU Core family selection" | |
880 | ||
881 | config ARCH_MULTI_V4 | |
882 | bool "ARMv4 based platforms (FA526, StrongARM)" | |
387798b3 | 883 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 884 | select ARCH_MULTI_V4_V5 |
387798b3 RH |
885 | |
886 | config ARCH_MULTI_V4T | |
887 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 888 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 889 | select ARCH_MULTI_V4_V5 |
387798b3 RH |
890 | |
891 | config ARCH_MULTI_V5 | |
892 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 893 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 894 | select ARCH_MULTI_V4_V5 |
387798b3 RH |
895 | |
896 | config ARCH_MULTI_V4_V5 | |
897 | bool | |
898 | ||
899 | config ARCH_MULTI_V6 | |
8dda05cc | 900 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 901 | select ARCH_MULTI_V6_V7 |
b1b3f49c | 902 | select CPU_V6 |
387798b3 RH |
903 | |
904 | config ARCH_MULTI_V7 | |
8dda05cc | 905 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
906 | default y |
907 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 908 | select CPU_V7 |
387798b3 RH |
909 | |
910 | config ARCH_MULTI_V6_V7 | |
911 | bool | |
912 | ||
913 | config ARCH_MULTI_CPU_AUTO | |
914 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
915 | select ARCH_MULTI_V5 | |
916 | ||
917 | endmenu | |
918 | ||
ccf50e23 RK |
919 | # |
920 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
921 | # Kconfigs may be included either alphabetically (according to the | |
922 | # plat- suffix) or along side the corresponding mach-* source. | |
923 | # | |
3e93a22b GC |
924 | source "arch/arm/mach-mvebu/Kconfig" |
925 | ||
95b8f20f RK |
926 | source "arch/arm/mach-at91/Kconfig" |
927 | ||
8ac49e04 CD |
928 | source "arch/arm/mach-bcm/Kconfig" |
929 | ||
f1ac922d SW |
930 | source "arch/arm/mach-bcm2835/Kconfig" |
931 | ||
1da177e4 LT |
932 | source "arch/arm/mach-clps711x/Kconfig" |
933 | ||
d94f944e AV |
934 | source "arch/arm/mach-cns3xxx/Kconfig" |
935 | ||
95b8f20f RK |
936 | source "arch/arm/mach-davinci/Kconfig" |
937 | ||
938 | source "arch/arm/mach-dove/Kconfig" | |
939 | ||
e7736d47 LB |
940 | source "arch/arm/mach-ep93xx/Kconfig" |
941 | ||
1da177e4 LT |
942 | source "arch/arm/mach-footbridge/Kconfig" |
943 | ||
59d3a193 PZ |
944 | source "arch/arm/mach-gemini/Kconfig" |
945 | ||
387798b3 RH |
946 | source "arch/arm/mach-highbank/Kconfig" |
947 | ||
1da177e4 LT |
948 | source "arch/arm/mach-integrator/Kconfig" |
949 | ||
3f7e5815 LB |
950 | source "arch/arm/mach-iop32x/Kconfig" |
951 | ||
952 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 | 953 | |
285f5fa7 DW |
954 | source "arch/arm/mach-iop13xx/Kconfig" |
955 | ||
1da177e4 LT |
956 | source "arch/arm/mach-ixp4xx/Kconfig" |
957 | ||
95b8f20f RK |
958 | source "arch/arm/mach-kirkwood/Kconfig" |
959 | ||
960 | source "arch/arm/mach-ks8695/Kconfig" | |
961 | ||
95b8f20f RK |
962 | source "arch/arm/mach-msm/Kconfig" |
963 | ||
794d15b2 SS |
964 | source "arch/arm/mach-mv78xx0/Kconfig" |
965 | ||
3995eb82 | 966 | source "arch/arm/mach-imx/Kconfig" |
1da177e4 | 967 | |
1d3f33d5 SG |
968 | source "arch/arm/mach-mxs/Kconfig" |
969 | ||
95b8f20f | 970 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 971 | |
95b8f20f | 972 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 973 | |
d48af15e TL |
974 | source "arch/arm/plat-omap/Kconfig" |
975 | ||
976 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 977 | |
1dbae815 TL |
978 | source "arch/arm/mach-omap2/Kconfig" |
979 | ||
9dd0b194 | 980 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 981 | |
387798b3 RH |
982 | source "arch/arm/mach-picoxcell/Kconfig" |
983 | ||
95b8f20f RK |
984 | source "arch/arm/mach-pxa/Kconfig" |
985 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 986 | |
95b8f20f RK |
987 | source "arch/arm/mach-mmp/Kconfig" |
988 | ||
989 | source "arch/arm/mach-realview/Kconfig" | |
990 | ||
991 | source "arch/arm/mach-sa1100/Kconfig" | |
edabd38e | 992 | |
cf383678 | 993 | source "arch/arm/plat-samsung/Kconfig" |
a21765a7 | 994 | |
387798b3 RH |
995 | source "arch/arm/mach-socfpga/Kconfig" |
996 | ||
a7ed099f | 997 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 998 | |
85fd6d63 | 999 | source "arch/arm/mach-s3c24xx/Kconfig" |
1da177e4 | 1000 | |
a08ab637 | 1001 | if ARCH_S3C64XX |
431107ea | 1002 | source "arch/arm/mach-s3c64xx/Kconfig" |
a08ab637 BD |
1003 | endif |
1004 | ||
49b7a491 | 1005 | source "arch/arm/mach-s5p64x0/Kconfig" |
c4ffccdd | 1006 | |
5a7652f2 | 1007 | source "arch/arm/mach-s5pc100/Kconfig" |
5a7652f2 | 1008 | |
170f4e42 KK |
1009 | source "arch/arm/mach-s5pv210/Kconfig" |
1010 | ||
83014579 | 1011 | source "arch/arm/mach-exynos/Kconfig" |
cc0e72b8 | 1012 | |
882d01f9 | 1013 | source "arch/arm/mach-shmobile/Kconfig" |
52c543f9 | 1014 | |
3b52634f MR |
1015 | source "arch/arm/mach-sunxi/Kconfig" |
1016 | ||
156a0997 BS |
1017 | source "arch/arm/mach-prima2/Kconfig" |
1018 | ||
c5f80065 EG |
1019 | source "arch/arm/mach-tegra/Kconfig" |
1020 | ||
95b8f20f | 1021 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 1022 | |
95b8f20f | 1023 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
1024 | |
1025 | source "arch/arm/mach-versatile/Kconfig" | |
1026 | ||
ceade897 | 1027 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 1028 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 1029 | |
2a0ba738 MZ |
1030 | source "arch/arm/mach-virt/Kconfig" |
1031 | ||
6f35f9a9 TP |
1032 | source "arch/arm/mach-vt8500/Kconfig" |
1033 | ||
7ec80ddf | 1034 | source "arch/arm/mach-w90x900/Kconfig" |
1035 | ||
9a45eb69 JC |
1036 | source "arch/arm/mach-zynq/Kconfig" |
1037 | ||
1da177e4 LT |
1038 | # Definitions to make life easier |
1039 | config ARCH_ACORN | |
1040 | bool | |
1041 | ||
7ae1f7ec LB |
1042 | config PLAT_IOP |
1043 | bool | |
469d3044 | 1044 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 1045 | |
69b02f6a LB |
1046 | config PLAT_ORION |
1047 | bool | |
bfe45e0b | 1048 | select CLKSRC_MMIO |
b1b3f49c | 1049 | select COMMON_CLK |
dc7ad3b3 | 1050 | select GENERIC_IRQ_CHIP |
278b45b0 | 1051 | select IRQ_DOMAIN |
69b02f6a | 1052 | |
abcda1dc TP |
1053 | config PLAT_ORION_LEGACY |
1054 | bool | |
1055 | select PLAT_ORION | |
1056 | ||
bd5ce433 EM |
1057 | config PLAT_PXA |
1058 | bool | |
1059 | ||
f4b8b319 RK |
1060 | config PLAT_VERSATILE |
1061 | bool | |
1062 | ||
e3887714 RK |
1063 | config ARM_TIMER_SP804 |
1064 | bool | |
bfe45e0b | 1065 | select CLKSRC_MMIO |
7a0eca71 | 1066 | select CLKSRC_OF if OF |
e3887714 | 1067 | |
1da177e4 LT |
1068 | source arch/arm/mm/Kconfig |
1069 | ||
958cab0f RK |
1070 | config ARM_NR_BANKS |
1071 | int | |
1072 | default 16 if ARCH_EP93XX | |
1073 | default 8 | |
1074 | ||
afe4b25e | 1075 | config IWMMXT |
698613b6 | 1076 | bool "Enable iWMMXt support" if !CPU_PJ4 |
ef6c8445 | 1077 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 |
698613b6 | 1078 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 |
afe4b25e LB |
1079 | help |
1080 | Enable support for iWMMXt context switching at run time if | |
1081 | running on a CPU that supports it. | |
1082 | ||
1da177e4 LT |
1083 | config XSCALE_PMU |
1084 | bool | |
bfc994b5 | 1085 | depends on CPU_XSCALE |
1da177e4 LT |
1086 | default y |
1087 | ||
52108641 | 1088 | config MULTI_IRQ_HANDLER |
1089 | bool | |
1090 | help | |
1091 | Allow each machine to specify it's own IRQ handler at run time. | |
1092 | ||
3b93e7b0 HC |
1093 | if !MMU |
1094 | source "arch/arm/Kconfig-nommu" | |
1095 | endif | |
1096 | ||
f0c4b8d6 WD |
1097 | config ARM_ERRATA_326103 |
1098 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
1099 | depends on CPU_V6 | |
1100 | help | |
1101 | Executing a SWP instruction to read-only memory does not set bit 11 | |
1102 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
1103 | treat the access as a read, preventing a COW from occurring and | |
1104 | causing the faulting task to livelock. | |
1105 | ||
9cba3ccc CM |
1106 | config ARM_ERRATA_411920 |
1107 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 1108 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
1109 | help |
1110 | Invalidation of the Instruction Cache operation can | |
1111 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
1112 | It does not affect the MPCore. This option enables the ARM Ltd. | |
1113 | recommended workaround. | |
1114 | ||
7ce236fc CM |
1115 | config ARM_ERRATA_430973 |
1116 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
1117 | depends on CPU_V7 | |
1118 | help | |
1119 | This option enables the workaround for the 430973 Cortex-A8 | |
1120 | (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb | |
1121 | interworking branch is replaced with another code sequence at the | |
1122 | same virtual address, whether due to self-modifying code or virtual | |
1123 | to physical address re-mapping, Cortex-A8 does not recover from the | |
1124 | stale interworking branch prediction. This results in Cortex-A8 | |
1125 | executing the new code sequence in the incorrect ARM or Thumb state. | |
1126 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
1127 | and also flushes the branch target cache at every context switch. | |
1128 | Note that setting specific bits in the ACTLR register may not be | |
1129 | available in non-secure mode. | |
1130 | ||
855c551f CM |
1131 | config ARM_ERRATA_458693 |
1132 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
1133 | depends on CPU_V7 | |
62e4d357 | 1134 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
1135 | help |
1136 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
1137 | erratum. For very specific sequences of memory operations, it is | |
1138 | possible for a hazard condition intended for a cache line to instead | |
1139 | be incorrectly associated with a different cache line. This false | |
1140 | hazard might then cause a processor deadlock. The workaround enables | |
1141 | the L1 caching of the NEON accesses and disables the PLD instruction | |
1142 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
1143 | register may not be available in non-secure mode. | |
1144 | ||
0516e464 CM |
1145 | config ARM_ERRATA_460075 |
1146 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
1147 | depends on CPU_V7 | |
62e4d357 | 1148 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
1149 | help |
1150 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
1151 | erratum. Any asynchronous access to the L2 cache may encounter a | |
1152 | situation in which recent store transactions to the L2 cache are lost | |
1153 | and overwritten with stale memory contents from external memory. The | |
1154 | workaround disables the write-allocate mode for the L2 cache via the | |
1155 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1156 | may not be available in non-secure mode. | |
1157 | ||
9f05027c WD |
1158 | config ARM_ERRATA_742230 |
1159 | bool "ARM errata: DMB operation may be faulty" | |
1160 | depends on CPU_V7 && SMP | |
62e4d357 | 1161 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
1162 | help |
1163 | This option enables the workaround for the 742230 Cortex-A9 | |
1164 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1165 | between two write operations may not ensure the correct visibility | |
1166 | ordering of the two writes. This workaround sets a specific bit in | |
1167 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1168 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1169 | the two writes. | |
1170 | ||
a672e99b WD |
1171 | config ARM_ERRATA_742231 |
1172 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1173 | depends on CPU_V7 && SMP | |
62e4d357 | 1174 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
1175 | help |
1176 | This option enables the workaround for the 742231 Cortex-A9 | |
1177 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1178 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1179 | accessing some data located in the same cache line, may get corrupted | |
1180 | data due to bad handling of the address hazard when the line gets | |
1181 | replaced from one of the CPUs at the same time as another CPU is | |
1182 | accessing it. This workaround sets specific bits in the diagnostic | |
1183 | register of the Cortex-A9 which reduces the linefill issuing | |
1184 | capabilities of the processor. | |
1185 | ||
9e65582a | 1186 | config PL310_ERRATA_588369 |
fa0ce403 | 1187 | bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" |
2839e06c | 1188 | depends on CACHE_L2X0 |
9e65582a SS |
1189 | help |
1190 | The PL310 L2 cache controller implements three types of Clean & | |
1191 | Invalidate maintenance operations: by Physical Address | |
1192 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | |
1193 | They are architecturally defined to behave as the execution of a | |
1194 | clean operation followed immediately by an invalidate operation, | |
1195 | both performing to the same memory location. This functionality | |
1196 | is not correctly implemented in PL310 as clean lines are not | |
2839e06c | 1197 | invalidated as a result of these operations. |
cdf357f1 WD |
1198 | |
1199 | config ARM_ERRATA_720789 | |
1200 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1201 | depends on CPU_V7 |
cdf357f1 WD |
1202 | help |
1203 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1204 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1205 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1206 | As a consequence of this erratum, some TLB entries which should be | |
1207 | invalidated are not, resulting in an incoherency in the system page | |
1208 | tables. The workaround changes the TLB flushing routines to invalidate | |
1209 | entries regardless of the ASID. | |
475d92fc | 1210 | |
1f0090a1 | 1211 | config PL310_ERRATA_727915 |
fa0ce403 | 1212 | bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" |
1f0090a1 RK |
1213 | depends on CACHE_L2X0 |
1214 | help | |
1215 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | |
1216 | operation (offset 0x7FC). This operation runs in background so that | |
1217 | PL310 can handle normal accesses while it is in progress. Under very | |
1218 | rare circumstances, due to this erratum, write data can be lost when | |
1219 | PL310 treats a cacheable write transaction during a Clean & | |
1220 | Invalidate by Way operation. | |
1221 | ||
475d92fc WD |
1222 | config ARM_ERRATA_743622 |
1223 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1224 | depends on CPU_V7 | |
62e4d357 | 1225 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
1226 | help |
1227 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1228 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1229 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1230 | corruption. This workaround sets a specific bit in the diagnostic | |
1231 | register of the Cortex-A9 which disables the Store Buffer | |
1232 | optimisation, preventing the defect from occurring. This has no | |
1233 | visible impact on the overall performance or power consumption of the | |
1234 | processor. | |
1235 | ||
9a27c27c WD |
1236 | config ARM_ERRATA_751472 |
1237 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1238 | depends on CPU_V7 |
62e4d357 | 1239 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
1240 | help |
1241 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1242 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1243 | completion of a following broadcasted operation if the second | |
1244 | operation is received by a CPU before the ICIALLUIS has completed, | |
1245 | potentially leading to corrupted entries in the cache or TLB. | |
1246 | ||
fa0ce403 WD |
1247 | config PL310_ERRATA_753970 |
1248 | bool "PL310 errata: cache sync operation may be faulty" | |
885028e4 SK |
1249 | depends on CACHE_PL310 |
1250 | help | |
1251 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. | |
1252 | ||
1253 | Under some condition the effect of cache sync operation on | |
1254 | the store buffer still remains when the operation completes. | |
1255 | This means that the store buffer is always asked to drain and | |
1256 | this prevents it from merging any further writes. The workaround | |
1257 | is to replace the normal offset of cache sync operation (0x730) | |
1258 | by another offset targeting an unmapped PL310 register 0x740. | |
1259 | This has the same effect as the cache sync operation: store buffer | |
1260 | drain and waiting for all buffers empty. | |
1261 | ||
fcbdc5fe WD |
1262 | config ARM_ERRATA_754322 |
1263 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1264 | depends on CPU_V7 | |
1265 | help | |
1266 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1267 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1268 | which starts prior to an ASID switch but completes afterwards. This | |
1269 | can populate the micro-TLB with a stale entry which may be hit with | |
1270 | the new ASID. This workaround places two dsb instructions in the mm | |
1271 | switching code so that no page table walks can cross the ASID switch. | |
1272 | ||
5dab26af WD |
1273 | config ARM_ERRATA_754327 |
1274 | bool "ARM errata: no automatic Store Buffer drain" | |
1275 | depends on CPU_V7 && SMP | |
1276 | help | |
1277 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1278 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1279 | mechanism and therefore a livelock may occur if an external agent | |
1280 | continuously polls a memory location waiting to observe an update. | |
1281 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1282 | written polling loops from denying visibility of updates to memory. | |
1283 | ||
145e10e1 CM |
1284 | config ARM_ERRATA_364296 |
1285 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
1286 | depends on CPU_V6 && !SMP | |
1287 | help | |
1288 | This options enables the workaround for the 364296 ARM1136 | |
1289 | r0p2 erratum (possible cache data corruption with | |
1290 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1291 | the auxiliary control register and the FI bit in the control | |
1292 | register, thus disabling hit-under-miss without putting the | |
1293 | processor into full low interrupt latency mode. ARM11MPCore | |
1294 | is not affected. | |
1295 | ||
f630c1bd WD |
1296 | config ARM_ERRATA_764369 |
1297 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1298 | depends on CPU_V7 && SMP | |
1299 | help | |
1300 | This option enables the workaround for erratum 764369 | |
1301 | affecting Cortex-A9 MPCore with two or more processors (all | |
1302 | current revisions). Under certain timing circumstances, a data | |
1303 | cache line maintenance operation by MVA targeting an Inner | |
1304 | Shareable memory region may fail to proceed up to either the | |
1305 | Point of Coherency or to the Point of Unification of the | |
1306 | system. This workaround adds a DSB instruction before the | |
1307 | relevant cache maintenance functions and sets a specific bit | |
1308 | in the diagnostic control register of the SCU. | |
1309 | ||
11ed0ba1 WD |
1310 | config PL310_ERRATA_769419 |
1311 | bool "PL310 errata: no automatic Store Buffer drain" | |
1312 | depends on CACHE_L2X0 | |
1313 | help | |
1314 | On revisions of the PL310 prior to r3p2, the Store Buffer does | |
1315 | not automatically drain. This can cause normal, non-cacheable | |
1316 | writes to be retained when the memory system is idle, leading | |
1317 | to suboptimal I/O performance for drivers using coherent DMA. | |
1318 | This option adds a write barrier to the cpu_idle loop so that, | |
1319 | on systems with an outer cache, the store buffer is drained | |
1320 | explicitly. | |
1321 | ||
7253b85c SH |
1322 | config ARM_ERRATA_775420 |
1323 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1324 | depends on CPU_V7 | |
1325 | help | |
1326 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1327 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1328 | operation aborts with MMU exception, it might cause the processor | |
1329 | to deadlock. This workaround puts DSB before executing ISB if | |
1330 | an abort may occur on cache maintenance. | |
1331 | ||
93dc6887 CM |
1332 | config ARM_ERRATA_798181 |
1333 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1334 | depends on CPU_V7 && SMP | |
1335 | help | |
1336 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1337 | adequately shooting down all use of the old entries. This | |
1338 | option enables the Linux kernel workaround for this erratum | |
1339 | which sends an IPI to the CPUs that are running the same ASID | |
1340 | as the one being invalidated. | |
1341 | ||
1da177e4 LT |
1342 | endmenu |
1343 | ||
1344 | source "arch/arm/common/Kconfig" | |
1345 | ||
1da177e4 LT |
1346 | menu "Bus support" |
1347 | ||
1348 | config ARM_AMBA | |
1349 | bool | |
1350 | ||
1351 | config ISA | |
1352 | bool | |
1da177e4 LT |
1353 | help |
1354 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1355 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1356 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1357 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1358 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1359 | ||
065909b9 | 1360 | # Select ISA DMA controller support |
1da177e4 LT |
1361 | config ISA_DMA |
1362 | bool | |
065909b9 | 1363 | select ISA_DMA_API |
1da177e4 | 1364 | |
065909b9 | 1365 | # Select ISA DMA interface |
5cae841b AV |
1366 | config ISA_DMA_API |
1367 | bool | |
5cae841b | 1368 | |
1da177e4 | 1369 | config PCI |
0b05da72 | 1370 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1371 | help |
1372 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1373 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1374 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1375 | VESA. If you have PCI, say Y, otherwise N. | |
1376 | ||
52882173 AV |
1377 | config PCI_DOMAINS |
1378 | bool | |
1379 | depends on PCI | |
1380 | ||
b080ac8a MRJ |
1381 | config PCI_NANOENGINE |
1382 | bool "BSE nanoEngine PCI support" | |
1383 | depends on SA1100_NANOENGINE | |
1384 | help | |
1385 | Enable PCI on the BSE nanoEngine board. | |
1386 | ||
36e23590 MW |
1387 | config PCI_SYSCALL |
1388 | def_bool PCI | |
1389 | ||
1da177e4 LT |
1390 | # Select the host bridge type |
1391 | config PCI_HOST_VIA82C505 | |
1392 | bool | |
1393 | depends on PCI && ARCH_SHARK | |
1394 | default y | |
1395 | ||
a0113a99 MR |
1396 | config PCI_HOST_ITE8152 |
1397 | bool | |
1398 | depends on PCI && MACH_ARMCORE | |
1399 | default y | |
1400 | select DMABOUNCE | |
1401 | ||
1da177e4 LT |
1402 | source "drivers/pci/Kconfig" |
1403 | ||
1404 | source "drivers/pcmcia/Kconfig" | |
1405 | ||
1406 | endmenu | |
1407 | ||
1408 | menu "Kernel Features" | |
1409 | ||
3b55658a DM |
1410 | config HAVE_SMP |
1411 | bool | |
1412 | help | |
1413 | This option should be selected by machines which have an SMP- | |
1414 | capable CPU. | |
1415 | ||
1416 | The only effect of this option is to make the SMP-related | |
1417 | options available to the user for configuration. | |
1418 | ||
1da177e4 | 1419 | config SMP |
bb2d8130 | 1420 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1421 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1422 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1423 | depends on HAVE_SMP |
9934ebb8 | 1424 | depends on MMU |
b1b3f49c | 1425 | select USE_GENERIC_SMP_HELPERS |
1da177e4 LT |
1426 | help |
1427 | This enables support for systems with more than one CPU. If you have | |
1428 | a system with only one CPU, like most personal computers, say N. If | |
1429 | you have a system with more than one CPU, say Y. | |
1430 | ||
1431 | If you say N here, the kernel will run on single and multiprocessor | |
1432 | machines, but will use only one CPU of a multiprocessor machine. If | |
1433 | you say Y here, the kernel will run on many, but not all, single | |
1434 | processor machines. On a single processor machine, the kernel will | |
1435 | run faster if you say N here. | |
1436 | ||
395cf969 | 1437 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
1da177e4 | 1438 | <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at |
50a23e6e | 1439 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1440 | |
1441 | If you don't know what to do here, say N. | |
1442 | ||
f00ec48f RK |
1443 | config SMP_ON_UP |
1444 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" | |
4d2692a7 | 1445 | depends on SMP && !XIP_KERNEL |
f00ec48f RK |
1446 | default y |
1447 | help | |
1448 | SMP kernels contain instructions which fail on non-SMP processors. | |
1449 | Enabling this option allows the kernel to modify itself to make | |
1450 | these instructions safe. Disabling it allows about 1K of space | |
1451 | savings. | |
1452 | ||
1453 | If you don't know what to do here, say Y. | |
1454 | ||
c9018aab VG |
1455 | config ARM_CPU_TOPOLOGY |
1456 | bool "Support cpu topology definition" | |
1457 | depends on SMP && CPU_V7 | |
1458 | default y | |
1459 | help | |
1460 | Support ARM cpu topology definition. The MPIDR register defines | |
1461 | affinity between processors which is then used to describe the cpu | |
1462 | topology of an ARM System. | |
1463 | ||
1464 | config SCHED_MC | |
1465 | bool "Multi-core scheduler support" | |
1466 | depends on ARM_CPU_TOPOLOGY | |
1467 | help | |
1468 | Multi-core scheduler support improves the CPU scheduler's decision | |
1469 | making when dealing with multi-core CPU chips at a cost of slightly | |
1470 | increased overhead in some places. If unsure say N here. | |
1471 | ||
1472 | config SCHED_SMT | |
1473 | bool "SMT scheduler support" | |
1474 | depends on ARM_CPU_TOPOLOGY | |
1475 | help | |
1476 | Improves the CPU scheduler's decision making when dealing with | |
1477 | MultiThreading at a cost of slightly increased overhead in some | |
1478 | places. If unsure say N here. | |
1479 | ||
a8cbcd92 RK |
1480 | config HAVE_ARM_SCU |
1481 | bool | |
a8cbcd92 RK |
1482 | help |
1483 | This option enables support for the ARM system coherency unit | |
1484 | ||
8a4da6e3 | 1485 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1486 | bool "Architected timer support" |
1487 | depends on CPU_V7 | |
8a4da6e3 | 1488 | select ARM_ARCH_TIMER |
022c03a2 MZ |
1489 | help |
1490 | This option enables support for the ARM architected timer | |
1491 | ||
f32f4ce2 RK |
1492 | config HAVE_ARM_TWD |
1493 | bool | |
1494 | depends on SMP | |
da4a686a | 1495 | select CLKSRC_OF if OF |
f32f4ce2 RK |
1496 | help |
1497 | This options enables support for the ARM timer and watchdog unit | |
1498 | ||
e8db288e NP |
1499 | config MCPM |
1500 | bool "Multi-Cluster Power Management" | |
1501 | depends on CPU_V7 && SMP | |
1502 | help | |
1503 | This option provides the common power management infrastructure | |
1504 | for (multi-)cluster based systems, such as big.LITTLE based | |
1505 | systems. | |
1506 | ||
8d5796d2 LB |
1507 | choice |
1508 | prompt "Memory split" | |
1509 | default VMSPLIT_3G | |
1510 | help | |
1511 | Select the desired split between kernel and user memory. | |
1512 | ||
1513 | If you are not absolutely sure what you are doing, leave this | |
1514 | option alone! | |
1515 | ||
1516 | config VMSPLIT_3G | |
1517 | bool "3G/1G user/kernel split" | |
1518 | config VMSPLIT_2G | |
1519 | bool "2G/2G user/kernel split" | |
1520 | config VMSPLIT_1G | |
1521 | bool "1G/3G user/kernel split" | |
1522 | endchoice | |
1523 | ||
1524 | config PAGE_OFFSET | |
1525 | hex | |
1526 | default 0x40000000 if VMSPLIT_1G | |
1527 | default 0x80000000 if VMSPLIT_2G | |
1528 | default 0xC0000000 | |
1529 | ||
1da177e4 LT |
1530 | config NR_CPUS |
1531 | int "Maximum number of CPUs (2-32)" | |
1532 | range 2 32 | |
1533 | depends on SMP | |
1534 | default "4" | |
1535 | ||
a054a811 | 1536 | config HOTPLUG_CPU |
00b7dede RK |
1537 | bool "Support for hot-pluggable CPUs" |
1538 | depends on SMP && HOTPLUG | |
a054a811 RK |
1539 | help |
1540 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1541 | can be controlled through /sys/devices/system/cpu. | |
1542 | ||
2bdd424f WD |
1543 | config ARM_PSCI |
1544 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
1545 | depends on CPU_V7 | |
1546 | help | |
1547 | Say Y here if you want Linux to communicate with system firmware | |
1548 | implementing the PSCI specification for CPU-centric power | |
1549 | management operations described in ARM document number ARM DEN | |
1550 | 0022A ("Power State Coordination Interface System Software on | |
1551 | ARM processors"). | |
1552 | ||
37ee16ae RK |
1553 | config LOCAL_TIMERS |
1554 | bool "Use local timer interrupts" | |
971acb9b | 1555 | depends on SMP |
37ee16ae RK |
1556 | default y |
1557 | help | |
1558 | Enable support for local timers on SMP platforms, rather then the | |
1559 | legacy IPI broadcast method. Local timers allows the system | |
1560 | accounting to be spread across the timer interval, preventing a | |
1561 | "thundering herd" at every timer tick. | |
1562 | ||
2a6ad871 MR |
1563 | # The GPIO number here must be sorted by descending number. In case of |
1564 | # a multiplatform kernel, we just want the highest value required by the | |
1565 | # selected platforms. | |
44986ab0 PDSN |
1566 | config ARCH_NR_GPIO |
1567 | int | |
3dea19e8 | 1568 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA |
39f47d9f | 1569 | default 512 if SOC_OMAP5 |
06b851e5 | 1570 | default 392 if ARCH_U8500 |
01bb914c TP |
1571 | default 352 if ARCH_VT8500 |
1572 | default 288 if ARCH_SUNXI | |
2a6ad871 | 1573 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1574 | default 0 |
1575 | help | |
1576 | Maximum number of GPIOs in the system. | |
1577 | ||
1578 | If unsure, leave the default value. | |
1579 | ||
d45a398f | 1580 | source kernel/Kconfig.preempt |
1da177e4 | 1581 | |
f8065813 RK |
1582 | config HZ |
1583 | int | |
b130d5c2 | 1584 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ |
a73ddc61 | 1585 | ARCH_S5PV210 || ARCH_EXYNOS4 |
5248c657 | 1586 | default AT91_TIMER_HZ if ARCH_AT91 |
5da3e714 | 1587 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE |
f8065813 RK |
1588 | default 100 |
1589 | ||
b28748fb RK |
1590 | config SCHED_HRTICK |
1591 | def_bool HIGH_RES_TIMERS | |
1592 | ||
16c79651 | 1593 | config THUMB2_KERNEL |
bc7dea00 | 1594 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
00b7dede | 1595 | depends on CPU_V7 && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1596 | default y if CPU_THUMBONLY |
16c79651 CM |
1597 | select AEABI |
1598 | select ARM_ASM_UNIFIED | |
89bace65 | 1599 | select ARM_UNWIND |
16c79651 CM |
1600 | help |
1601 | By enabling this option, the kernel will be compiled in | |
1602 | Thumb-2 mode. A compiler/assembler that understand the unified | |
1603 | ARM-Thumb syntax is needed. | |
1604 | ||
1605 | If unsure, say N. | |
1606 | ||
6f685c5c DM |
1607 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1608 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1609 | depends on THUMB2_KERNEL && MODULES | |
1610 | default y | |
1611 | help | |
1612 | Various binutils versions can resolve Thumb-2 branches to | |
1613 | locally-defined, preemptible global symbols as short-range "b.n" | |
1614 | branch instructions. | |
1615 | ||
1616 | This is a problem, because there's no guarantee the final | |
1617 | destination of the symbol, or any candidate locations for a | |
1618 | trampoline, are within range of the branch. For this reason, the | |
1619 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1620 | relocation in modules at all, and it makes little sense to add | |
1621 | support. | |
1622 | ||
1623 | The symptom is that the kernel fails with an "unsupported | |
1624 | relocation" error when loading some modules. | |
1625 | ||
1626 | Until fixed tools are available, passing | |
1627 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1628 | code which hits this problem, at the cost of a bit of extra runtime | |
1629 | stack usage in some cases. | |
1630 | ||
1631 | The problem is described in more detail at: | |
1632 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1633 | ||
1634 | Only Thumb-2 kernels are affected. | |
1635 | ||
1636 | Unless you are sure your tools don't have this problem, say Y. | |
1637 | ||
0becb088 CM |
1638 | config ARM_ASM_UNIFIED |
1639 | bool | |
1640 | ||
704bdda0 NP |
1641 | config AEABI |
1642 | bool "Use the ARM EABI to compile the kernel" | |
1643 | help | |
1644 | This option allows for the kernel to be compiled using the latest | |
1645 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1646 | space environment that is also compiled with EABI. | |
1647 | ||
1648 | Since there are major incompatibilities between the legacy ABI and | |
1649 | EABI, especially with regard to structure member alignment, this | |
1650 | option also changes the kernel syscall calling convention to | |
1651 | disambiguate both ABIs and allow for backward compatibility support | |
1652 | (selected with CONFIG_OABI_COMPAT). | |
1653 | ||
1654 | To use this you need GCC version 4.0.0 or later. | |
1655 | ||
6c90c872 | 1656 | config OABI_COMPAT |
a73a3ff1 | 1657 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1658 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1659 | default y |
1660 | help | |
1661 | This option preserves the old syscall interface along with the | |
1662 | new (ARM EABI) one. It also provides a compatibility layer to | |
1663 | intercept syscalls that have structure arguments which layout | |
1664 | in memory differs between the legacy ABI and the new ARM EABI | |
1665 | (only for non "thumb" binaries). This option adds a tiny | |
1666 | overhead to all syscalls and produces a slightly larger kernel. | |
1667 | If you know you'll be using only pure EABI user space then you | |
1668 | can say N here. If this option is not selected and you attempt | |
1669 | to execute a legacy ABI binary then the result will be | |
1670 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
1671 | at all). If in doubt say Y. | |
1672 | ||
eb33575c | 1673 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1674 | bool |
e80d6a24 | 1675 | |
05944d74 RK |
1676 | config ARCH_SPARSEMEM_ENABLE |
1677 | bool | |
1678 | ||
07a2f737 RK |
1679 | config ARCH_SPARSEMEM_DEFAULT |
1680 | def_bool ARCH_SPARSEMEM_ENABLE | |
1681 | ||
05944d74 | 1682 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1683 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1684 | |
7b7bf499 WD |
1685 | config HAVE_ARCH_PFN_VALID |
1686 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1687 | ||
053a96ca | 1688 | config HIGHMEM |
e8db89a2 RK |
1689 | bool "High Memory Support" |
1690 | depends on MMU | |
053a96ca NP |
1691 | help |
1692 | The address space of ARM processors is only 4 Gigabytes large | |
1693 | and it has to accommodate user address space, kernel address | |
1694 | space as well as some memory mapped IO. That means that, if you | |
1695 | have a large amount of physical memory and/or IO, not all of the | |
1696 | memory can be "permanently mapped" by the kernel. The physical | |
1697 | memory that is not permanently mapped is called "high memory". | |
1698 | ||
1699 | Depending on the selected kernel/user memory split, minimum | |
1700 | vmalloc space and actual amount of RAM, you may not need this | |
1701 | option which should result in a slightly faster kernel. | |
1702 | ||
1703 | If unsure, say n. | |
1704 | ||
65cec8e3 RK |
1705 | config HIGHPTE |
1706 | bool "Allocate 2nd-level pagetables from highmem" | |
1707 | depends on HIGHMEM | |
65cec8e3 | 1708 | |
1b8873a0 JI |
1709 | config HW_PERF_EVENTS |
1710 | bool "Enable hardware performance counter support for perf events" | |
f0d1bc47 | 1711 | depends on PERF_EVENTS |
1b8873a0 JI |
1712 | default y |
1713 | help | |
1714 | Enable hardware performance counter support for perf events. If | |
1715 | disabled, perf events will use software events only. | |
1716 | ||
3f22ab27 DH |
1717 | source "mm/Kconfig" |
1718 | ||
c1b2d970 MD |
1719 | config FORCE_MAX_ZONEORDER |
1720 | int "Maximum zone order" if ARCH_SHMOBILE | |
1721 | range 11 64 if ARCH_SHMOBILE | |
898f08e1 | 1722 | default "12" if SOC_AM33XX |
c1b2d970 MD |
1723 | default "9" if SA1111 |
1724 | default "11" | |
1725 | help | |
1726 | The kernel memory allocator divides physically contiguous memory | |
1727 | blocks into "zones", where each zone is a power of two number of | |
1728 | pages. This option selects the largest power of two that the kernel | |
1729 | keeps in the memory allocator. If you need to allocate very large | |
1730 | blocks of physically contiguous memory, then you may need to | |
1731 | increase this value. | |
1732 | ||
1733 | This config option is actually maximum order plus one. For example, | |
1734 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1735 | ||
1da177e4 LT |
1736 | config ALIGNMENT_TRAP |
1737 | bool | |
f12d0d7c | 1738 | depends on CPU_CP15_MMU |
1da177e4 | 1739 | default y if !ARCH_EBSA110 |
e119bfff | 1740 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1741 | help |
84eb8d06 | 1742 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1743 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1744 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1745 | fetch/store instructions will be emulated in software if you say | |
1746 | here, which has a severe performance impact. This is necessary for | |
1747 | correct operation of some network protocols. With an IP-only | |
1748 | configuration it is safe to say N, otherwise say Y. | |
1749 | ||
39ec58f3 | 1750 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1751 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1752 | depends on MMU | |
39ec58f3 LB |
1753 | default y if CPU_FEROCEON |
1754 | help | |
1755 | Implement faster copy_to_user and clear_user methods for CPU | |
1756 | cores where a 8-word STM instruction give significantly higher | |
1757 | memory write throughput than a sequence of individual 32bit stores. | |
1758 | ||
1759 | A possible side effect is a slight increase in scheduling latency | |
1760 | between threads sharing the same address space if they invoke | |
1761 | such copy operations with large buffers. | |
1762 | ||
1763 | However, if the CPU data cache is using a write-allocate mode, | |
1764 | this option is unlikely to provide any performance gain. | |
1765 | ||
70c70d97 NP |
1766 | config SECCOMP |
1767 | bool | |
1768 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1769 | ---help--- | |
1770 | This kernel feature is useful for number crunching applications | |
1771 | that may need to compute untrusted bytecode during their | |
1772 | execution. By using pipes or other transports made available to | |
1773 | the process as file descriptors supporting the read/write | |
1774 | syscalls, it's possible to isolate those applications in | |
1775 | their own address space using seccomp. Once seccomp is | |
1776 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1777 | and the task is only allowed to execute a few safe syscalls | |
1778 | defined by each seccomp mode. | |
1779 | ||
c743f380 NP |
1780 | config CC_STACKPROTECTOR |
1781 | bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" | |
1782 | help | |
1783 | This option turns on the -fstack-protector GCC feature. This | |
1784 | feature puts, at the beginning of functions, a canary value on | |
1785 | the stack just before the return address, and validates | |
1786 | the value just before actually returning. Stack based buffer | |
1787 | overflows (that need to overwrite this return address) now also | |
1788 | overwrite the canary, which gets detected and the attack is then | |
1789 | neutralized via a kernel panic. | |
1790 | This feature requires gcc version 4.2 or above. | |
1791 | ||
eff8d644 SS |
1792 | config XEN_DOM0 |
1793 | def_bool y | |
1794 | depends on XEN | |
1795 | ||
1796 | config XEN | |
1797 | bool "Xen guest support on ARM (EXPERIMENTAL)" | |
85323a99 | 1798 | depends on ARM && AEABI && OF |
f880b67d | 1799 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1800 | depends on !GENERIC_ATOMIC64 |
17b7ab80 | 1801 | select ARM_PSCI |
eff8d644 SS |
1802 | help |
1803 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1804 | ||
1da177e4 LT |
1805 | endmenu |
1806 | ||
1807 | menu "Boot options" | |
1808 | ||
9eb8f674 GL |
1809 | config USE_OF |
1810 | bool "Flattened Device Tree support" | |
b1b3f49c | 1811 | select IRQ_DOMAIN |
9eb8f674 GL |
1812 | select OF |
1813 | select OF_EARLY_FLATTREE | |
1814 | help | |
1815 | Include support for flattened device tree machine descriptions. | |
1816 | ||
bd51e2f5 NP |
1817 | config ATAGS |
1818 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1819 | default y | |
1820 | help | |
1821 | This is the traditional way of passing data to the kernel at boot | |
1822 | time. If you are solely relying on the flattened device tree (or | |
1823 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1824 | to remove ATAGS support from your kernel binary. If unsure, | |
1825 | leave this to y. | |
1826 | ||
1827 | config DEPRECATED_PARAM_STRUCT | |
1828 | bool "Provide old way to pass kernel parameters" | |
1829 | depends on ATAGS | |
1830 | help | |
1831 | This was deprecated in 2001 and announced to live on for 5 years. | |
1832 | Some old boot loaders still use this way. | |
1833 | ||
1da177e4 LT |
1834 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1835 | # TEXT and BSS so we preserve their values in the config files. | |
1836 | config ZBOOT_ROM_TEXT | |
1837 | hex "Compressed ROM boot loader base address" | |
1838 | default "0" | |
1839 | help | |
1840 | The physical address at which the ROM-able zImage is to be | |
1841 | placed in the target. Platforms which normally make use of | |
1842 | ROM-able zImage formats normally set this to a suitable | |
1843 | value in their defconfig file. | |
1844 | ||
1845 | If ZBOOT_ROM is not enabled, this has no effect. | |
1846 | ||
1847 | config ZBOOT_ROM_BSS | |
1848 | hex "Compressed ROM boot loader BSS address" | |
1849 | default "0" | |
1850 | help | |
f8c440b2 DF |
1851 | The base address of an area of read/write memory in the target |
1852 | for the ROM-able zImage which must be available while the | |
1853 | decompressor is running. It must be large enough to hold the | |
1854 | entire decompressed kernel plus an additional 128 KiB. | |
1855 | Platforms which normally make use of ROM-able zImage formats | |
1856 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1857 | |
1858 | If ZBOOT_ROM is not enabled, this has no effect. | |
1859 | ||
1860 | config ZBOOT_ROM | |
1861 | bool "Compressed boot loader in ROM/flash" | |
1862 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
1863 | help | |
1864 | Say Y here if you intend to execute your compressed kernel image | |
1865 | (zImage) directly from ROM or flash. If unsure, say N. | |
1866 | ||
090ab3ff SH |
1867 | choice |
1868 | prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" | |
d6f94fa0 | 1869 | depends on ZBOOT_ROM && ARCH_SH7372 |
090ab3ff SH |
1870 | default ZBOOT_ROM_NONE |
1871 | help | |
1872 | Include experimental SD/MMC loading code in the ROM-able zImage. | |
59bf8964 | 1873 | With this enabled it is possible to write the ROM-able zImage |
090ab3ff SH |
1874 | kernel image to an MMC or SD card and boot the kernel straight |
1875 | from the reset vector. At reset the processor Mask ROM will load | |
59bf8964 | 1876 | the first part of the ROM-able zImage which in turn loads the |
090ab3ff SH |
1877 | rest the kernel image to RAM. |
1878 | ||
1879 | config ZBOOT_ROM_NONE | |
1880 | bool "No SD/MMC loader in zImage (EXPERIMENTAL)" | |
1881 | help | |
1882 | Do not load image from SD or MMC | |
1883 | ||
f45b1149 SH |
1884 | config ZBOOT_ROM_MMCIF |
1885 | bool "Include MMCIF loader in zImage (EXPERIMENTAL)" | |
f45b1149 | 1886 | help |
090ab3ff SH |
1887 | Load image from MMCIF hardware block. |
1888 | ||
1889 | config ZBOOT_ROM_SH_MOBILE_SDHI | |
1890 | bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" | |
1891 | help | |
1892 | Load image from SDHI hardware block | |
1893 | ||
1894 | endchoice | |
f45b1149 | 1895 | |
e2a6a3aa JB |
1896 | config ARM_APPENDED_DTB |
1897 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
d6f94fa0 | 1898 | depends on OF && !ZBOOT_ROM |
e2a6a3aa JB |
1899 | help |
1900 | With this option, the boot code will look for a device tree binary | |
1901 | (DTB) appended to zImage | |
1902 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1903 | ||
1904 | This is meant as a backward compatibility convenience for those | |
1905 | systems with a bootloader that can't be upgraded to accommodate | |
1906 | the documented boot protocol using a device tree. | |
1907 | ||
1908 | Beware that there is very little in terms of protection against | |
1909 | this option being confused by leftover garbage in memory that might | |
1910 | look like a DTB header after a reboot if no actual DTB is appended | |
1911 | to zImage. Do not leave this option active in a production kernel | |
1912 | if you don't intend to always append a DTB. Proper passing of the | |
1913 | location into r2 of a bootloader provided DTB is always preferable | |
1914 | to this option. | |
1915 | ||
b90b9a38 NP |
1916 | config ARM_ATAG_DTB_COMPAT |
1917 | bool "Supplement the appended DTB with traditional ATAG information" | |
1918 | depends on ARM_APPENDED_DTB | |
1919 | help | |
1920 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1921 | they provide ATAGs with memory configuration, the ramdisk address, | |
1922 | the kernel cmdline string, etc. Such information is dynamically | |
1923 | provided by the bootloader and can't always be stored in a static | |
1924 | DTB. To allow a device tree enabled kernel to be used with such | |
1925 | bootloaders, this option allows zImage to extract the information | |
1926 | from the ATAG list and store it at run time into the appended DTB. | |
1927 | ||
d0f34a11 GR |
1928 | choice |
1929 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1930 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1931 | ||
1932 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1933 | bool "Use bootloader kernel arguments if available" | |
1934 | help | |
1935 | Uses the command-line options passed by the boot loader instead of | |
1936 | the device tree bootargs property. If the boot loader doesn't provide | |
1937 | any, the device tree bootargs property will be used. | |
1938 | ||
1939 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1940 | bool "Extend with bootloader kernel arguments" | |
1941 | help | |
1942 | The command-line arguments provided by the boot loader will be | |
1943 | appended to the the device tree bootargs property. | |
1944 | ||
1945 | endchoice | |
1946 | ||
1da177e4 LT |
1947 | config CMDLINE |
1948 | string "Default kernel command string" | |
1949 | default "" | |
1950 | help | |
1951 | On some architectures (EBSA110 and CATS), there is currently no way | |
1952 | for the boot loader to pass arguments to the kernel. For these | |
1953 | architectures, you should supply some command-line options at build | |
1954 | time by entering them here. As a minimum, you should specify the | |
1955 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1956 | ||
4394c124 VB |
1957 | choice |
1958 | prompt "Kernel command line type" if CMDLINE != "" | |
1959 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 1960 | depends on ATAGS |
4394c124 VB |
1961 | |
1962 | config CMDLINE_FROM_BOOTLOADER | |
1963 | bool "Use bootloader kernel arguments if available" | |
1964 | help | |
1965 | Uses the command-line options passed by the boot loader. If | |
1966 | the boot loader doesn't provide any, the default kernel command | |
1967 | string provided in CMDLINE will be used. | |
1968 | ||
1969 | config CMDLINE_EXTEND | |
1970 | bool "Extend bootloader kernel arguments" | |
1971 | help | |
1972 | The command-line arguments provided by the boot loader will be | |
1973 | appended to the default kernel command string. | |
1974 | ||
92d2040d AH |
1975 | config CMDLINE_FORCE |
1976 | bool "Always use the default kernel command string" | |
92d2040d AH |
1977 | help |
1978 | Always use the default kernel command string, even if the boot | |
1979 | loader passes other arguments to the kernel. | |
1980 | This is useful if you cannot or don't want to change the | |
1981 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1982 | endchoice |
92d2040d | 1983 | |
1da177e4 LT |
1984 | config XIP_KERNEL |
1985 | bool "Kernel Execute-In-Place from ROM" | |
387798b3 | 1986 | depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
1987 | help |
1988 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1989 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1990 | space since the text section of the kernel is not loaded from flash | |
1991 | to RAM. Read-write sections, such as the data section and stack, | |
1992 | are still copied to RAM. The XIP kernel is not compressed since | |
1993 | it has to run directly from flash, so it will take more space to | |
1994 | store it. The flash address used to link the kernel object files, | |
1995 | and for storing it, is configuration dependent. Therefore, if you | |
1996 | say Y here, you must know the proper physical address where to | |
1997 | store the kernel image depending on your own flash memory usage. | |
1998 | ||
1999 | Also note that the make target becomes "make xipImage" rather than | |
2000 | "make zImage" or "make Image". The final kernel binary to put in | |
2001 | ROM memory will be arch/arm/boot/xipImage. | |
2002 | ||
2003 | If unsure, say N. | |
2004 | ||
2005 | config XIP_PHYS_ADDR | |
2006 | hex "XIP Kernel Physical Location" | |
2007 | depends on XIP_KERNEL | |
2008 | default "0x00080000" | |
2009 | help | |
2010 | This is the physical address in your flash memory the kernel will | |
2011 | be linked for and stored to. This address is dependent on your | |
2012 | own flash usage. | |
2013 | ||
c587e4a6 RP |
2014 | config KEXEC |
2015 | bool "Kexec system call (EXPERIMENTAL)" | |
d6f94fa0 | 2016 | depends on (!SMP || HOTPLUG_CPU) |
c587e4a6 RP |
2017 | help |
2018 | kexec is a system call that implements the ability to shutdown your | |
2019 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 2020 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
2021 | you can start any kernel with it, not just Linux. |
2022 | ||
2023 | It is an ongoing process to be certain the hardware in a machine | |
2024 | is properly shutdown, so do not be surprised if this code does not | |
2025 | initially work for you. It may help to enable device hotplugging | |
2026 | support. | |
2027 | ||
4cd9d6f7 RP |
2028 | config ATAGS_PROC |
2029 | bool "Export atags in procfs" | |
bd51e2f5 | 2030 | depends on ATAGS && KEXEC |
b98d7291 | 2031 | default y |
4cd9d6f7 RP |
2032 | help |
2033 | Should the atags used to boot the kernel be exported in an "atags" | |
2034 | file in procfs. Useful with kexec. | |
2035 | ||
cb5d39b3 MW |
2036 | config CRASH_DUMP |
2037 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
2038 | help |
2039 | Generate crash dump after being started by kexec. This should | |
2040 | be normally only set in special crash dump kernels which are | |
2041 | loaded in the main kernel with kexec-tools into a specially | |
2042 | reserved region and then later executed after a crash by | |
2043 | kdump/kexec. The crash dump kernel must be compiled to a | |
2044 | memory address not used by the main kernel | |
2045 | ||
2046 | For more details see Documentation/kdump/kdump.txt | |
2047 | ||
e69edc79 EM |
2048 | config AUTO_ZRELADDR |
2049 | bool "Auto calculation of the decompressed kernel image address" | |
2050 | depends on !ZBOOT_ROM && !ARCH_U300 | |
2051 | help | |
2052 | ZRELADDR is the physical address where the decompressed kernel | |
2053 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2054 | will be determined at run-time by masking the current IP with | |
2055 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2056 | from start of memory. | |
2057 | ||
1da177e4 LT |
2058 | endmenu |
2059 | ||
ac9d7efc | 2060 | menu "CPU Power Management" |
1da177e4 | 2061 | |
89c52ed4 | 2062 | if ARCH_HAS_CPUFREQ |
1da177e4 LT |
2063 | source "drivers/cpufreq/Kconfig" |
2064 | ||
9d56c02a BD |
2065 | config CPU_FREQ_S3C |
2066 | bool | |
2067 | help | |
2068 | Internal configuration node for common cpufreq on Samsung SoC | |
2069 | ||
2070 | config CPU_FREQ_S3C24XX | |
4a50bfe3 | 2071 | bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" |
d6f94fa0 | 2072 | depends on ARCH_S3C24XX && CPU_FREQ |
9d56c02a BD |
2073 | select CPU_FREQ_S3C |
2074 | help | |
2075 | This enables the CPUfreq driver for the Samsung S3C24XX family | |
2076 | of CPUs. | |
2077 | ||
2078 | For details, take a look at <file:Documentation/cpu-freq>. | |
2079 | ||
2080 | If in doubt, say N. | |
2081 | ||
2082 | config CPU_FREQ_S3C24XX_PLL | |
4a50bfe3 | 2083 | bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" |
d6f94fa0 | 2084 | depends on CPU_FREQ_S3C24XX |
9d56c02a BD |
2085 | help |
2086 | Compile in support for changing the PLL frequency from the | |
2087 | S3C24XX series CPUfreq driver. The PLL takes time to settle | |
2088 | after a frequency change, so by default it is not enabled. | |
2089 | ||
2090 | This also means that the PLL tables for the selected CPU(s) will | |
2091 | be built which may increase the size of the kernel image. | |
2092 | ||
2093 | config CPU_FREQ_S3C24XX_DEBUG | |
2094 | bool "Debug CPUfreq Samsung driver core" | |
2095 | depends on CPU_FREQ_S3C24XX | |
2096 | help | |
2097 | Enable s3c_freq_dbg for the Samsung S3C CPUfreq core | |
2098 | ||
2099 | config CPU_FREQ_S3C24XX_IODEBUG | |
2100 | bool "Debug CPUfreq Samsung driver IO timing" | |
2101 | depends on CPU_FREQ_S3C24XX | |
2102 | help | |
2103 | Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core | |
2104 | ||
e6d197a6 BD |
2105 | config CPU_FREQ_S3C24XX_DEBUGFS |
2106 | bool "Export debugfs for CPUFreq" | |
2107 | depends on CPU_FREQ_S3C24XX && DEBUG_FS | |
2108 | help | |
2109 | Export status information via debugfs. | |
2110 | ||
1da177e4 LT |
2111 | endif |
2112 | ||
ac9d7efc RK |
2113 | source "drivers/cpuidle/Kconfig" |
2114 | ||
2115 | endmenu | |
2116 | ||
1da177e4 LT |
2117 | menu "Floating point emulation" |
2118 | ||
2119 | comment "At least one emulation must be selected" | |
2120 | ||
2121 | config FPE_NWFPE | |
2122 | bool "NWFPE math emulation" | |
593c252a | 2123 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2124 | ---help--- |
2125 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2126 | This is necessary to run most binaries. Linux does not currently | |
2127 | support floating point hardware so you need to say Y here even if | |
2128 | your machine has an FPA or floating point co-processor podule. | |
2129 | ||
2130 | You may say N here if you are going to load the Acorn FPEmulator | |
2131 | early in the bootup. | |
2132 | ||
2133 | config FPE_NWFPE_XP | |
2134 | bool "Support extended precision" | |
bedf142b | 2135 | depends on FPE_NWFPE |
1da177e4 LT |
2136 | help |
2137 | Say Y to include 80-bit support in the kernel floating-point | |
2138 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2139 | Note that gcc does not generate 80-bit operations by default, | |
2140 | so in most cases this option only enlarges the size of the | |
2141 | floating point emulator without any good reason. | |
2142 | ||
2143 | You almost surely want to say N here. | |
2144 | ||
2145 | config FPE_FASTFPE | |
2146 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 2147 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
1da177e4 LT |
2148 | ---help--- |
2149 | Say Y here to include the FAST floating point emulator in the kernel. | |
2150 | This is an experimental much faster emulator which now also has full | |
2151 | precision for the mantissa. It does not support any exceptions. | |
2152 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2153 | ||
2154 | It should be sufficient for most programs. It may be not suitable | |
2155 | for scientific calculations, but you have to check this for yourself. | |
2156 | If you do not feel you need a faster FP emulation you should better | |
2157 | choose NWFPE. | |
2158 | ||
2159 | config VFP | |
2160 | bool "VFP-format floating point maths" | |
e399b1a4 | 2161 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2162 | help |
2163 | Say Y to include VFP support code in the kernel. This is needed | |
2164 | if your hardware includes a VFP unit. | |
2165 | ||
2166 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2167 | release notes and additional status information. | |
2168 | ||
2169 | Say N if your target does not have VFP hardware. | |
2170 | ||
25ebee02 CM |
2171 | config VFPv3 |
2172 | bool | |
2173 | depends on VFP | |
2174 | default y if CPU_V7 | |
2175 | ||
b5872db4 CM |
2176 | config NEON |
2177 | bool "Advanced SIMD (NEON) Extension support" | |
2178 | depends on VFPv3 && CPU_V7 | |
2179 | help | |
2180 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2181 | Extension. | |
2182 | ||
1da177e4 LT |
2183 | endmenu |
2184 | ||
2185 | menu "Userspace binary formats" | |
2186 | ||
2187 | source "fs/Kconfig.binfmt" | |
2188 | ||
2189 | config ARTHUR | |
2190 | tristate "RISC OS personality" | |
704bdda0 | 2191 | depends on !AEABI |
1da177e4 LT |
2192 | help |
2193 | Say Y here to include the kernel code necessary if you want to run | |
2194 | Acorn RISC OS/Arthur binaries under Linux. This code is still very | |
2195 | experimental; if this sounds frightening, say N and sleep in peace. | |
2196 | You can also say M here to compile this support as a module (which | |
2197 | will be called arthur). | |
2198 | ||
2199 | endmenu | |
2200 | ||
2201 | menu "Power management options" | |
2202 | ||
eceab4ac | 2203 | source "kernel/power/Kconfig" |
1da177e4 | 2204 | |
f4cb5700 | 2205 | config ARCH_SUSPEND_POSSIBLE |
4b1082ca | 2206 | depends on !ARCH_S5PC100 |
6a786182 | 2207 | depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ |
3f5d0819 | 2208 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2209 | def_bool y |
2210 | ||
15e0d9e3 AB |
2211 | config ARM_CPU_SUSPEND |
2212 | def_bool PM_SLEEP | |
2213 | ||
1da177e4 LT |
2214 | endmenu |
2215 | ||
d5950b43 SR |
2216 | source "net/Kconfig" |
2217 | ||
ac25150f | 2218 | source "drivers/Kconfig" |
1da177e4 LT |
2219 | |
2220 | source "fs/Kconfig" | |
2221 | ||
1da177e4 LT |
2222 | source "arch/arm/Kconfig.debug" |
2223 | ||
2224 | source "security/Kconfig" | |
2225 | ||
2226 | source "crypto/Kconfig" | |
2227 | ||
2228 | source "lib/Kconfig" | |
749cf76c CD |
2229 | |
2230 | source "arch/arm/kvm/Kconfig" |