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ARM: dts: am335x-evm: NAND: update MTD partition table
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / am335x-evm.dts
CommitLineData
32bb00e0
AC		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
eb33ef66 10#include "am33xx.dtsi"
32bb00e0
AC		 11
12/ {
13 model = "TI AM335x EVM";
14 compatible = "ti,am335x-evm", "ti,am33xx";
15
efeedcf2
AC		 16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
32bb00e0
AC		 22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 };
53d91034 26
1b2a9702
AC		 27 vbat: fixedregulator@0 {
28 compatible = "regulator-fixed";
29 regulator-name = "vbat";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
32 regulator-boot-on;
33 };
492dd024
AC		 34
35 lis3_reg: fixedregulator@1 {
36 compatible = "regulator-fixed";
37 regulator-name = "lis3_reg";
38 regulator-boot-on;
39 };
2ca1d317
AC		 40
41 matrix_keypad: matrix_keypad@0 {
42 compatible = "gpio-matrix-keypad";
43 debounce-delay-ms = <5>;
44 col-scan-delay-us = <2>;
45
e94233c2
FV		 46 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
47 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
48 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
2ca1d317 49
e94233c2
FV		 50 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
51 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
2ca1d317
AC		 52
53 linux,keymap = <0x0000008b /* MENU */
54 0x0100009e /* BACK */
55 0x02000069 /* LEFT */
56 0x0001006a /* RIGHT */
57 0x0101001c /* ENTER */
58 0x0201006c>; /* DOWN */
59 };
822c9936
AC		 60
61 gpio_keys: volume_keys@0 {
62 compatible = "gpio-keys";
63 #address-cells = <1>;
64 #size-cells = <0>;
65 autorepeat;
66
67 switch@9 {
68 label = "volume-up";
69 linux,code = <115>;
e94233c2 70 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
822c9936
AC		 71 gpio-key,wakeup;
72 };
73
74 switch@10 {
75 label = "volume-down";
76 linux,code = <114>;
e94233c2 77 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
822c9936
AC		 78 gpio-key,wakeup;
79 };
80 };
6993fd01
PA		 81
82 backlight {
83 compatible = "pwm-backlight";
84 pwms = <&ecap0 0 50000 0>;
85 brightness-levels = <0 51 53 56 62 75 101 152 255>;
86 default-brightness-level = <8>;
87 };
d6cfc1e2
BP		 88
89 panel {
90 compatible = "ti,tilcdc,panel";
91 status = "okay";
92 pinctrl-names = "default";
93 pinctrl-0 = <&lcd_pins_s0>;
94 panel-info {
95 ac-bias = <255>;
96 ac-bias-intrpt = <0>;
97 dma-burst-sz = <16>;
98 bpp = <32>;
99 fdd = <0x80>;
100 sync-edge = <0>;
101 sync-ctrl = <1>;
102 raster-order = <0>;
103 fifo-th = <0>;
104 };
105
106 display-timings {
107 800x480p62 {
108 clock-frequency = <30000000>;
109 hactive = <800>;
110 vactive = <480>;
111 hfront-porch = <39>;
112 hback-porch = <39>;
113 hsync-len = <47>;
114 vback-porch = <29>;
115 vfront-porch = <13>;
116 vsync-len = <2>;
117 hsync-active = <1>;
118 vsync-active = <1>;
119 };
120 };
121 };
f608f8dd
DE		 122
123 sound {
124 compatible = "ti,da830-evm-audio";
125 ti,model = "AM335x-EVM";
126 ti,audio-codec = <&tlv320aic3106>;
127 ti,mcasp-controller = <&mcasp1>;
128 ti,codec-clock-rate = <12000000>;
129 ti,audio-routing =
130 "Headphone Jack", "HPLOUT",
131 "Headphone Jack", "HPROUT",
132 "LINE1L", "Line In",
133 "LINE1R", "Line In";
134 };
1b2a9702
AC		 135};
136
82d75afc
JMC		 137&am33xx_pinmux {
138 pinctrl-names = "default";
139 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
140
141 matrix_keypad_s0: matrix_keypad_s0 {
142 pinctrl-single,pins = <
143 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
144 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
145 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
146 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
147 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
148 >;
149 };
150
151 volume_keys_s0: volume_keys_s0 {
152 pinctrl-single,pins = <
153 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
154 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
155 >;
156 };
157
158 i2c0_pins: pinmux_i2c0_pins {
159 pinctrl-single,pins = <
160 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
161 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
162 >;
163 };
164
165 i2c1_pins: pinmux_i2c1_pins {
166 pinctrl-single,pins = <
167 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
168 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
169 >;
170 };
171
172 uart0_pins: pinmux_uart0_pins {
173 pinctrl-single,pins = <
174 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
175 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
176 >;
177 };
178
179 clkout2_pin: pinmux_clkout2_pin {
180 pinctrl-single,pins = <
181 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
182 >;
183 };
184
185 nandflash_pins_s0: nandflash_pins_s0 {
186 pinctrl-single,pins = <
187 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
188 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
189 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
190 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
191 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
192 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
193 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
194 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
195 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
196 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
197 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
198 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
199 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
200 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
201 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
202 >;
203 };
204
205 ecap0_pins: backlight_pins {
206 pinctrl-single,pins = <
207 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
208 >;
209 };
210
211 cpsw_default: cpsw_default {
212 pinctrl-single,pins = <
213 /* Slave 1 */
214 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
215 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
216 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
217 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
218 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
219 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
220 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
221 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
222 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
223 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
224 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
225 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
226 >;
227 };
228
229 cpsw_sleep: cpsw_sleep {
230 pinctrl-single,pins = <
231 /* Slave 1 reset value */
232 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
233 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
234 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
235 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
236 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
237 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
238 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
239 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
240 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
241 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
242 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
243 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
244 >;
245 };
246
247 davinci_mdio_default: davinci_mdio_default {
248 pinctrl-single,pins = <
249 /* MDIO */
250 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
251 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
252 >;
253 };
254
255 davinci_mdio_sleep: davinci_mdio_sleep {
256 pinctrl-single,pins = <
257 /* MDIO reset value */
258 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
259 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
260 >;
261 };
d6cfc1e2
BP		 262
263 lcd_pins_s0: lcd_pins_s0 {
264 pinctrl-single,pins = <
265 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
266 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
267 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
268 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
269 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
270 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
271 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
272 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
273 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
274 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
275 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
276 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
277 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
278 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
279 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
280 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
281 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
282 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
283 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
284 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
285 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
286 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
287 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
288 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
289 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
290 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
291 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
292 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
293 >;
294 };
f608f8dd
DE		 295
296 am335x_evm_audio_pins: am335x_evm_audio_pins {
297 pinctrl-single,pins = <
298 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
299 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
300 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
301 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
302 >;
303 };
82d75afc
JMC		 304};
305
e0efaafb
JMC		 306&uart0 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&uart0_pins>;
309
310 status = "okay";
311};
312
313&i2c0 {
314 pinctrl-names = "default";
315 pinctrl-0 = <&i2c0_pins>;
316
317 status = "okay";
318 clock-frequency = <400000>;
319
320 tps: tps@2d {
321 reg = <0x2d>;
322 };
323};
324
325&usb {
326 status = "okay";
327
328 control@44e10000 {
329 status = "okay";
330 };
331
332 usb-phy@47401300 {
333 status = "okay";
334 };
335
336 usb-phy@47401b00 {
337 status = "okay";
338 };
339
340 usb@47401000 {
341 status = "okay";
342 };
343
344 usb@47401800 {
345 status = "okay";
346 dr_mode = "host";
347 };
348
349 dma-controller@07402000 {
350 status = "okay";
351 };
352};
353
354&i2c1 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c1_pins>;
357
358 status = "okay";
359 clock-frequency = <100000>;
360
361 lis331dlh: lis331dlh@18 {
362 compatible = "st,lis331dlh", "st,lis3lv02d";
363 reg = <0x18>;
364 Vdd-supply = <&lis3_reg>;
365 Vdd_IO-supply = <&lis3_reg>;
366
367 st,click-single-x;
368 st,click-single-y;
369 st,click-single-z;
370 st,click-thresh-x = <10>;
371 st,click-thresh-y = <10>;
372 st,click-thresh-z = <10>;
373 st,irq1-click;
374 st,irq2-click;
375 st,wakeup-x-lo;
376 st,wakeup-x-hi;
377 st,wakeup-y-lo;
378 st,wakeup-y-hi;
379 st,wakeup-z-lo;
380 st,wakeup-z-hi;
381 st,min-limit-x = <120>;
382 st,min-limit-y = <120>;
383 st,min-limit-z = <140>;
384 st,max-limit-x = <550>;
385 st,max-limit-y = <550>;
386 st,max-limit-z = <750>;
387 };
388
389 tsl2550: tsl2550@39 {
390 compatible = "taos,tsl2550";
391 reg = <0x39>;
392 };
393
394 tmp275: tmp275@48 {
395 compatible = "ti,tmp275";
396 reg = <0x48>;
397 };
f608f8dd
DE		 398
399 tlv320aic3106: tlv320aic3106@1b {
400 compatible = "ti,tlv320aic3106";
401 reg = <0x1b>;
402 status = "okay";
403
404 /* Regulators */
405 AVDD-supply = <&vaux2_reg>;
406 IOVDD-supply = <&vaux2_reg>;
407 DRVDD-supply = <&vaux2_reg>;
408 DVDD-supply = <&vbat>;
409 };
e0efaafb
JMC		 410};
411
d6cfc1e2
BP		 412&lcdc {
413 status = "okay";
414};
415
e0efaafb
JMC		 416&elm {
417 status = "okay";
418};
419
420&epwmss0 {
421 status = "okay";
422
423 ecap0: ecap@48300100 {
424 status = "okay";
425 pinctrl-names = "default";
426 pinctrl-0 = <&ecap0_pins>;
427 };
428};
429
430&gpmc {
431 status = "okay";
432 pinctrl-names = "default";
433 pinctrl-0 = <&nandflash_pins_s0>;
434 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
435 nand@0,0 {
436 reg = <0 0 0>; /* CS0, offset 0 */
437 nand-bus-width = <8>;
438 ti,nand-ecc-opt = "bch8";
439 gpmc,device-nand = "true";
440 gpmc,device-width = <1>;
441 gpmc,sync-clk-ps = <0>;
442 gpmc,cs-on-ns = <0>;
443 gpmc,cs-rd-off-ns = <44>;
444 gpmc,cs-wr-off-ns = <44>;
445 gpmc,adv-on-ns = <6>;
446 gpmc,adv-rd-off-ns = <34>;
447 gpmc,adv-wr-off-ns = <44>;
448 gpmc,we-on-ns = <0>;
449 gpmc,we-off-ns = <40>;
450 gpmc,oe-on-ns = <0>;
451 gpmc,oe-off-ns = <54>;
452 gpmc,access-ns = <64>;
453 gpmc,rd-cycle-ns = <82>;
454 gpmc,wr-cycle-ns = <82>;
455 gpmc,wait-on-read = "true";
456 gpmc,wait-on-write = "true";
457 gpmc,bus-turnaround-ns = <0>;
458 gpmc,cycle2cycle-delay-ns = <0>;
459 gpmc,clk-activation-ns = <0>;
460 gpmc,wait-monitoring-ns = <0>;
461 gpmc,wr-access-ns = <40>;
462 gpmc,wr-data-mux-bus-ns = <0>;
e0efaafb 463 elm_id = <&elm>;
e0efaafb 464 /* MTD partition table */
91994fac
PG		 465 /* All SPL-* partitions are sized to minimal length
466 * which can be independently programmable. For
467 * NAND flash this is equal to size of erase-block */
468 #address-cells = <1>;
469 #size-cells = <1>;
e0efaafb 470 partition@0 {
91994fac 471 label = "NAND.SPL";
e0efaafb
JMC		 472 reg = <0x00000000 0x000020000>;
473 };
e0efaafb 474 partition@1 {
91994fac 475 label = "NAND.SPL.backup1";
e0efaafb
JMC		 476 reg = <0x00020000 0x00020000>;
477 };
e0efaafb 478 partition@2 {
91994fac 479 label = "NAND.SPL.backup2";
e0efaafb
JMC		 480 reg = <0x00040000 0x00020000>;
481 };
e0efaafb 482 partition@3 {
91994fac 483 label = "NAND.SPL.backup3";
e0efaafb
JMC		 484 reg = <0x00060000 0x00020000>;
485 };
e0efaafb 486 partition@4 {
91994fac
PG		 487 label = "NAND.u-boot-spl";
488 reg = <0x00080000 0x00040000>;
e0efaafb 489 };
e0efaafb 490 partition@5 {
91994fac
PG		 491 label = "NAND.u-boot";
492 reg = <0x000C0000 0x00100000>;
e0efaafb 493 };
e0efaafb 494 partition@6 {
91994fac
PG		 495 label = "NAND.u-boot-env";
496 reg = <0x001C0000 0x00020000>;
e0efaafb 497 };
e0efaafb 498 partition@7 {
91994fac
PG		 499 label = "NAND.u-boot-env.backup1";
500 reg = <0x001E0000 0x00020000>;
501 };
502 partition@8 {
503 label = "NAND.kernel";
504 reg = <0x00200000 0x00800000>;
505 };
506 partition@9 {
507 label = "NAND.file-system";
508 reg = <0x00A00000 0x0F600000>;
e0efaafb
JMC		 509 };
510 };
511};
512
eb33ef66 513#include "tps65910.dtsi"
1b2a9702 514
f608f8dd
DE		 515&mcasp1 {
516 pinctrl-names = "default";
517 pinctrl-0 = <&am335x_evm_audio_pins>;
518
519 status = "okay";
520
521 op-mode = <0>; /* MCASP_IIS_MODE */
522 tdm-slots = <2>;
523 /* 4 serializers */
524 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
525 0 0 1 2
526 >;
527 tx-num-evt = <1>;
528 rx-num-evt = <1>;
529};
530
1b2a9702
AC		 531&tps {
532 vcc1-supply = <&vbat>;
533 vcc2-supply = <&vbat>;
534 vcc3-supply = <&vbat>;
535 vcc4-supply = <&vbat>;
536 vcc5-supply = <&vbat>;
537 vcc6-supply = <&vbat>;
538 vcc7-supply = <&vbat>;
539 vccio-supply = <&vbat>;
540
541 regulators {
542 vrtc_reg: regulator@0 {
543 regulator-always-on;
544 };
545
546 vio_reg: regulator@1 {
547 regulator-always-on;
548 };
549
550 vdd1_reg: regulator@2 {
551 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
552 regulator-name = "vdd_mpu";
553 regulator-min-microvolt = <912500>;
554 regulator-max-microvolt = <1312500>;
555 regulator-boot-on;
556 regulator-always-on;
557 };
558
559 vdd2_reg: regulator@3 {
560 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
561 regulator-name = "vdd_core";
562 regulator-min-microvolt = <912500>;
563 regulator-max-microvolt = <1150000>;
564 regulator-boot-on;
565 regulator-always-on;
566 };
567
568 vdd3_reg: regulator@4 {
569 regulator-always-on;
570 };
571
572 vdig1_reg: regulator@5 {
573 regulator-always-on;
574 };
575
576 vdig2_reg: regulator@6 {
577 regulator-always-on;
578 };
579
580 vpll_reg: regulator@7 {
581 regulator-always-on;
582 };
583
584 vdac_reg: regulator@8 {
585 regulator-always-on;
586 };
587
588 vaux1_reg: regulator@9 {
589 regulator-always-on;
590 };
591
592 vaux2_reg: regulator@10 {
593 regulator-always-on;
594 };
595
596 vaux33_reg: regulator@11 {
597 regulator-always-on;
598 };
599
600 vmmc_reg: regulator@12 {
55b4452b
MP		 601 regulator-min-microvolt = <1800000>;
602 regulator-max-microvolt = <3300000>;
1b2a9702
AC		 603 regulator-always-on;
604 };
53d91034 605 };
32bb00e0 606};
1a39a65c 607
50c7d2bd
M		 608&mac {
609 pinctrl-names = "default", "sleep";
610 pinctrl-0 = <&cpsw_default>;
611 pinctrl-1 = <&cpsw_sleep>;
612};
613
614&davinci_mdio {
615 pinctrl-names = "default", "sleep";
616 pinctrl-0 = <&davinci_mdio_default>;
617 pinctrl-1 = <&davinci_mdio_sleep>;
618};
619
1a39a65c
M		 620&cpsw_emac0 {
621 phy_id = <&davinci_mdio>, <0>;
6d75afe2 622 phy-mode = "rgmii-txid";
1a39a65c
M		 623};
624
625&cpsw_emac1 {
626 phy_id = <&davinci_mdio>, <1>;
6d75afe2 627 phy-mode = "rgmii-txid";
1a39a65c 628};
a82279dd
PR		 629
630&tscadc {
631 status = "okay";
632 tsc {
633 ti,wires = <4>;
634 ti,x-plate-resistance = <200>;
c9aeb249 635 ti,coordinate-readouts = <5>;
a82279dd
PR		 636 ti,wire-config = <0x00 0x11 0x22 0x33>;
637 };
638
639 adc {
18926ede 640 ti,adc-channels = <4 5 6 7>;
a82279dd
PR		 641 };
642};
55b4452b
MP		 643
644&mmc1 {
645 status = "okay";
646 vmmc-supply = <&vmmc_reg>;
0d8d40fc 647 bus-width = <4>;
55b4452b 648};
f8302e1e
MG		 649
650&sham {
651 status = "okay";
652};
99919e5e
MG		 653
654&aes {
655 status = "okay";
656};
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