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Merge tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / am335x-lxm.dts
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
d5744541
GM		 2/*
3 * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com
d5744541
GM		 4 */
5/dts-v1/;
6
7#include "am33xx.dtsi"
8
9/ {
10 model = "NovaTech OrionLXm";
11 compatible = "novatech,am335x-lxm", "ti,am33xx";
12
13 cpus {
14 cpu@0 {
15 cpu0-supply = <&vdd1_reg>;
16 };
17 };
18
278cb79c 19 memory@80000000 {
d5744541
GM		 20 device_type = "memory";
21 reg = <0x80000000 0x20000000>; /* 512 MB */
22 };
23
24 /* Power supply provides a fixed 5V @2A */
4c049a5b 25 vbat: fixedregulator0 {
d5744541
GM		 26 compatible = "regulator-fixed";
27 regulator-name = "vbat";
28 regulator-min-microvolt = <5000000>;
29 regulator-max-microvolt = <5000000>;
30 regulator-boot-on;
31 };
32
33 /* Power supply provides a fixed 3.3V @3A */
4c049a5b 34 vmmcsd_fixed: fixedregulator1 {
d5744541
GM		 35 compatible = "regulator-fixed";
36 regulator-name = "vmmcsd_fixed";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 regulator-boot-on;
40 };
41};
42
43&am33xx_pinmux {
44 mmc1_pins: pinmux_mmc1_pins {
45 pinctrl-single,pins = <
c422b10e
CQ		 46 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
47 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
48 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
49 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
50 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
51 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
d5744541
GM		 52 >;
53 };
54
55 i2c0_pins: pinmux_i2c0_pins {
56 pinctrl-single,pins = <
c422b10e
CQ		 57 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
58 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
d5744541
GM		 59 >;
60 };
61
62 cpsw_default: cpsw_default {
63 pinctrl-single,pins = <
64 /* Slave 1 */
c422b10e
CQ		 65 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */
66 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */
67 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */
68 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */
69 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */
70 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */
71 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */
72 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */
73 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
d5744541
GM		 74
75 /* Slave 2 */
c422b10e
CQ		 76 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */
77 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */
78 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */
79 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */
80 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */
81 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */
82 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */
83 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */
84 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */
d5744541
GM		 85 >;
86 };
87
88 cpsw_sleep: cpsw_sleep {
89 pinctrl-single,pins = <
90 /* Slave 1 reset value */
c422b10e
CQ		 91 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */
92 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */
93 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */
94 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */
95 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */
96 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */
97 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */
98 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */
99 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */
d5744541
GM		 100
101 /* Slave 2 reset value*/
c422b10e
CQ		 102 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */
103 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */
104 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */
105 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */
106 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */
107 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */
108 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */
109 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */
110 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */
d5744541
GM		 111 >;
112 };
113
114 davinci_mdio_default: davinci_mdio_default {
115 pinctrl-single,pins = <
116 /* MDIO */
c422b10e
CQ		 117 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
118 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
d5744541
GM		 119 >;
120 };
121
122 davinci_mdio_sleep: davinci_mdio_sleep {
123 pinctrl-single,pins = <
124 /* MDIO reset value */
c422b10e
CQ		 125 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
126 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
d5744541
GM		 127 >;
128 };
129
130 emmc_pins: pinmux_emmc_pins {
131 pinctrl-single,pins = <
c422b10e
CQ		 132 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
133 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
134 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
135 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
136 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
137 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
138 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
139 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
140 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
141 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
d5744541
GM		 142 >;
143 };
144
145 uart0_pins: pinmux_uart0_pins {
146 pinctrl-single,pins = <
c422b10e
CQ		 147 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
148 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
d5744541
GM		 149 >;
150 };
151};
152
153&i2c0 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&i2c0_pins>;
156
157 status = "okay";
158 clock-frequency = <400000>;
159
160 serial_config1: serial_config1@20 {
161 compatible = "nxp,pca9539";
162 reg = <0x20>;
163 };
164
165 serial_config2: serial_config2@21 {
166 compatible = "nxp,pca9539";
167 reg = <0x21>;
168 };
169
170 tps: tps@2d {
171 compatible = "ti,tps65910";
172 reg = <0x2d>;
173 };
174};
175
176/include/ "tps65910.dtsi"
177
178&tps {
179 vcc1-supply = <&vbat>;
180 vcc2-supply = <&vbat>;
181 vcc3-supply = <&vbat>;
182 vcc4-supply = <&vbat>;
183 vcc5-supply = <&vbat>;
184 vcc6-supply = <&vbat>;
185 vcc7-supply = <&vbat>;
186 vccio-supply = <&vbat>;
187
188 regulators {
189 /* vrtc - unused */
190
191 vio_reg: regulator@1 {
192 regulator-name = "vio_1v5,ddr";
193 regulator-min-microvolt = <1500000>;
194 regulator-max-microvolt = <1500000>;
195 regulator-boot-on;
196 regulator-always-on;
197 };
198
199 vdd1_reg: regulator@2 {
200 regulator-name = "vdd1,mpu";
201 regulator-min-microvolt = <600000>;
202 regulator-max-microvolt = <1500000>;
203 regulator-boot-on;
204 regulator-always-on;
205 };
206
207 vdd2_reg: regulator@3 {
208 regulator-name = "vdd2_1v1,core";
209 regulator-min-microvolt = <1100000>;
210 regulator-max-microvolt = <1100000>;
211 regulator-boot-on;
212 regulator-always-on;
213 };
214
215 /* vdd3 - unused */
216
217 /* vdig1 - unused */
218
219 vdig2_reg: regulator@6 {
220 regulator-name = "vdig2_1v8,vdds_pll";
221 regulator-min-microvolt = <1800000>;
222 regulator-max-microvolt = <1800000>;
223 regulator-boot-on;
224 regulator-always-on;
225 };
226
227 /* vpll - unused */
228
229 vdac_reg: regulator@8 {
230 regulator-name = "vdac_1v8,vdds";
231 regulator-min-microvolt = <1800000>;
232 regulator-max-microvolt = <1800000>;
233 regulator-boot-on;
234 regulator-always-on;
235 };
236
237 vaux1_reg: regulator@9 {
238 regulator-name = "vaux1_1v8,usb";
239 regulator-min-microvolt = <1800000>;
240 regulator-max-microvolt = <1800000>;
241 regulator-boot-on;
242 regulator-always-on;
243 };
244
245 vaux2_reg: regulator@10 {
246 regulator-name = "vaux2_3v3,io";
247 regulator-min-microvolt = <3300000>;
248 regulator-max-microvolt = <3300000>;
249 regulator-boot-on;
250 regulator-always-on;
251 };
252
253 vaux33_reg: regulator@11 {
254 regulator-name = "vaux33_3v3,usb";
255 regulator-min-microvolt = <3300000>;
256 regulator-max-microvolt = <3300000>;
257 regulator-boot-on;
258 regulator-always-on;
259 };
260
261 vmmc_reg: regulator@12 {
262 regulator-name = "vmmc_3v3,io";
263 regulator-min-microvolt = <3300000>;
264 regulator-max-microvolt = <3300000>;
265 regulator-boot-on;
266 regulator-always-on;
267 };
268 };
269};
270
271&sham {
272 status = "okay";
273};
274
275&aes {
276 status = "okay";
277};
278
279&uart0 {
280 pinctrl-names = "default";
281 pinctrl-0 = <&uart0_pins>;
282
283 status = "okay";
284};
285
286&usb {
287 status = "okay";
288};
289
290&usb_ctrl_mod {
291 status = "okay";
292};
293
294&usb0_phy {
295 status = "okay";
296};
297
298&usb1_phy {
299 status = "okay";
300};
301
302&usb0 {
303 status = "okay";
304 dr_mode = "host";
305};
306
307&usb1 {
308 status = "okay";
309 dr_mode = "host";
310};
311
312&cppi41dma {
313 status = "okay";
314};
315
316&cpsw_emac0 {
5ec73320 317 phy-handle = <&ethphy0>;
d5744541
GM		 318 phy-mode = "rmii";
319 dual_emac_res_vlan = <2>;
320};
321
322&cpsw_emac1 {
5ec73320 323 phy-handle = <&ethphy1>;
d5744541
GM		 324 phy-mode = "rmii";
325 dual_emac_res_vlan = <3>;
326};
327
328&mac {
329 pinctrl-names = "default", "sleep";
330 pinctrl-0 = <&cpsw_default>;
331 pinctrl-1 = <&cpsw_sleep>;
332 dual_emac = <1>;
333 status = "okay";
334};
335
336&davinci_mdio {
337 pinctrl-names = "default", "sleep";
338 pinctrl-0 = <&davinci_mdio_default>;
339 pinctrl-1 = <&davinci_mdio_sleep>;
340 status = "okay";
5ec73320
GS		 341
342 ethphy0: ethernet-phy@5 {
343 reg = <5>;
344 };
345
346 ethphy1: ethernet-phy@4 {
347 reg = <4>;
348 };
d5744541
GM		 349};
350
351&mmc1 {
352 pinctrl-names = "default";
353 pinctrl-0 = <&mmc1_pins>;
354 vmmc-supply = <&vmmcsd_fixed>;
355 bus-width = <4>;
356 status = "okay";
357};
358
359&mmc2 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&emmc_pins>;
362 vmmc-supply = <&vmmcsd_fixed>;
363 bus-width = <8>;
364 ti,non-removable;
365 status = "okay";
366};
367
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