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Merge tag 'powerpc-5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / am335x-moxa-uc-8100-me-t.dts
CommitLineData
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SL		 1/*
2 * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/
3 *
4 * Author: SZ Lin (林上智) <sz.lin@moxa.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/dts-v1/;
12
13#include "am33xx.dtsi"
14
15/ {
16 model = "Moxa UC-8100-ME-T";
17 compatible = "moxa,uc-8100-me-t", "ti,am33xx";
18
19 cpus {
20 cpu@0 {
21 cpu0-supply = <&vdd1_reg>;
22 };
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0x80000000 0x20000000>; /* 512 MB */
28 };
29
30 vbat: vbat-regulator {
31 compatible = "regulator-fixed";
32 };
33
34 /* Power supply provides a fixed 3.3V @3A */
35 vmmcsd_fixed: vmmcsd-regulator {
36 compatible = "regulator-fixed";
37 regulator-name = "vmmcsd_fixed";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-boot-on;
41 };
42
43 leds {
44 compatible = "gpio-leds";
45 led1 {
46 label = "uc8100me:CEL1";
47 gpios = <&gpio_xten 8 0>;
48 default-state = "off";
49 };
50
51 led2 {
52 label = "uc8100me:CEL2";
53 gpios = <&gpio_xten 9 0>;
54 default-state = "off";
55 };
56
57 led3 {
58 label = "uc8100me:CEL3";
59 gpios = <&gpio_xten 10 0>;
60 default-state = "off";
61 };
62
63 led4 {
64 label = "uc8100me:DIA1";
65 gpios = <&gpio_xten 11 0>;
66 default-state = "off";
67 };
68 led5 {
69 label = "uc8100me:DIA2";
70 gpios = <&gpio_xten 12 0>;
71 default-state = "off";
72 };
73 led6 {
74 label = "uc8100me:DIA3";
75 gpios = <&gpio_xten 13 0>;
76 default-state = "off";
77 };
78 led7 {
79 label = "uc8100me:SD";
80 gpios = <&gpio_xten 14 0>;
81 default-state = "off";
82 };
83 led8 {
84 label = "uc8100me:USB";
85 gpios = <&gpio_xten 15 0>;
86 default-state = "off";
87 };
88 led9 {
89 label = "uc8100me:USER";
90 gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
91 default-state = "off";
92 };
93 };
94
95 buttons: push_button {
96 compatible = "gpio-keys";
97 };
98
99};
100
101&am33xx_pinmux {
102 pinctrl-names = "default";
103 pinctrl-0 = <&minipcie_pins>;
104
105 minipcie_pins: pinmux_minipcie {
106 pinctrl-single,pins = <
c68a4ffd
CQ		 107 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */
108 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */
109 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/
5e452865
SL		 110 >;
111 };
112
113 push_button_pins: pinmux_push_button {
114 pinctrl-single,pins = <
c68a4ffd 115 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */
5e452865
SL		 116 >;
117 };
118
119 i2c0_pins: pinmux_i2c0_pins {
120 pinctrl-single,pins = <
c68a4ffd
CQ		 121 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
122 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
5e452865
SL		 123 >;
124 };
125
126
127 i2c1_pins: pinmux_i2c1_pins {
128 pinctrl-single,pins = <
c68a4ffd
CQ		 129 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */
130 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */
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SL		 131 >;
132 };
133
134 uart0_pins: pinmux_uart0_pins {
135 pinctrl-single,pins = <
c68a4ffd
CQ		 136 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
137 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
5e452865
SL		 138 >;
139 };
140
141 uart1_pins: pinmux_uart1_pins {
142 pinctrl-single,pins = <
c68a4ffd
CQ		 143 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
144 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
145 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
146 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
5e452865
SL		 147 >;
148 };
149
150 uart2_pins: pinmux_uart2_pins {
151 pinctrl-single,pins = <
c68a4ffd
CQ		 152 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */
153 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */
154 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */
155 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */
5e452865
SL		 156 >;
157 };
158
159 cpsw_default: cpsw_default {
160 pinctrl-single,pins = <
161 /* Slave 1 */
c68a4ffd
CQ		 162 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
163 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)
164 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
165 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
166 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
167 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
168 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
169 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
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SL		 170
171 /* Slave 2 */
c68a4ffd
CQ		 172 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */
173 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */
174 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */
175 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */
176 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */
177 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */
178 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */
179 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */
5e452865
SL		 180
181 >;
182 };
183
184 davinci_mdio_default: davinci_mdio_default {
185 pinctrl-single,pins = <
186 /* MDIO */
c68a4ffd
CQ		 187 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
188 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
5e452865
SL		 189 >;
190 };
191
192 mmc0_pins_default: pinmux_mmc0_pins {
193 pinctrl-single,pins = <
c68a4ffd
CQ		 194 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
195 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
196 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
197 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
198 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
199 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
200 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */
201 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */
5e452865
SL		 202 >;
203 };
204
205 mmc2_pins_default: pinmux_mmc2_pins {
206 pinctrl-single,pins = <
207 /* eMMC */
c68a4ffd
CQ		 208 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */
209 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */
210 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */
211 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */
212 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */
213 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */
214 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */
215 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */
216 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
217 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */
5e452865
SL		 218 >;
219 };
220
221 spi0_pins: pinmux_spi0 {
222 pinctrl-single,pins = <
c68a4ffd
CQ		 223 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
224 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
225 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
226 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
5e452865
SL		 227 >;
228 };
229
230};
231
232&uart0 {
233 /* Console */
234 status = "okay";
235 pinctrl-names = "default";
236 pinctrl-0 = <&uart0_pins>;
237};
238
239&uart1 {
240 /* UART 1 setting */
241 status = "okay";
242 pinctrl-names = "default";
243 pinctrl-0 = <&uart1_pins>;
244};
245
246&uart5 {
247 /* UART 2 setting */
248 status = "okay";
249 pinctrl-names = "default";
250 pinctrl-0 = <&uart2_pins>;
251};
252
253&i2c0 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&i2c0_pins>;
256
257 status = "okay";
258 clock-frequency = <400000>;
259
260 tpm: tpm@20 {
261 compatible = "infineon,slb9645tt";
262 reg = <0x20>;
263 };
264
265 tps: tps@2d {
266 compatible = "ti,tps65910";
267 reg = <0x2d>;
268 };
269
270 eeprom: eeprom@50 {
271 compatible = "atmel,24c16";
272 pagesize = <16>;
273 reg = <0x50>;
274 };
275
276 rtc_wdt: rtc_wdt@68 {
277 compatible = "dallas,ds1374";
278 reg = <0x68>;
279 };
280};
281
282&i2c1 {
283 pinctrl-names = "default";
284 pinctrl-0 = <&i2c1_pins>;
285
286 status = "okay";
287 clock-frequency = <400000>;
288 gpio_xten: gpio_xten@27 {
289 compatible = "nxp,pca9535";
290 gpio-controller;
291 #gpio-cells = <2>;
292 reg = <0x27>;
293 };
294};
295
296&usb {
297 status = "okay";
298};
299
300&usb_ctrl_mod {
301 status = "okay";
302};
303
304&usb0_phy {
305 status = "okay";
306};
307
308&usb1_phy {
309 status = "okay";
310};
311
312&usb0 {
313 status = "okay";
314 dr_mode = "host";
315};
316
317&usb1 {
318 status = "okay";
319 dr_mode = "host";
320};
321
322&cppi41dma {
323 status = "okay";
324};
325
326#include "tps65910.dtsi"
327
328&tps {
329 vcc1-supply = <&vbat>;
330 vcc2-supply = <&vbat>;
331 vcc3-supply = <&vbat>;
332 vcc4-supply = <&vbat>;
333 vcc5-supply = <&vbat>;
334 vcc6-supply = <&vbat>;
335 vcc7-supply = <&vbat>;
336 vccio-supply = <&vbat>;
337
338 regulators {
339 vrtc_reg: regulator@0 {
340 regulator-always-on;
341 };
342
343 vio_reg: regulator@1 {
344 regulator-always-on;
345 };
346
347 vdd1_reg: regulator@2 {
348 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
349 regulator-name = "vdd_mpu";
350 regulator-min-microvolt = <912500>;
351 regulator-max-microvolt = <1378000>;
352 regulator-boot-on;
353 regulator-always-on;
354 };
355
356 vdd2_reg: regulator@3 {
357 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
358 regulator-name = "vdd_core";
359 regulator-min-microvolt = <912500>;
360 regulator-max-microvolt = <1150000>;
361 regulator-boot-on;
362 regulator-always-on;
363 };
364
365 vdd3_reg: regulator@4 {
366 regulator-always-on;
367 };
368
369 vdig1_reg: regulator@5 {
370 regulator-always-on;
371 };
372
373 vdig2_reg: regulator@6 {
374 regulator-always-on;
375 };
376
377 vpll_reg: regulator@7 {
378 regulator-always-on;
379 };
380
381 vdac_reg: regulator@8 {
382 regulator-always-on;
383 };
384
385 vaux1_reg: regulator@9 {
386 regulator-always-on;
387 };
388
389 vaux2_reg: regulator@10 {
390 regulator-always-on;
391 };
392
393 vaux33_reg: regulator@11 {
394 regulator-always-on;
395 };
396
397 vmmc_reg: regulator@12 {
398 compatible = "regulator-fixed";
399 regulator-name = "vmmc_reg";
400 regulator-min-microvolt = <3300000>;
401 regulator-max-microvolt = <3300000>;
402 regulator-always-on;
403 };
404 };
405};
406
407/* Power */
408&vbat {
409 regulator-name = "vbat";
410 regulator-min-microvolt = <5000000>;
411 regulator-max-microvolt = <5000000>;
412};
413
414&mac {
415 pinctrl-names = "default";
416 pinctrl-0 = <&cpsw_default>;
417 dual_emac = <1>;
418 status = "okay";
419};
420
421&davinci_mdio {
422 pinctrl-names = "default";
423 pinctrl-0 = <&davinci_mdio_default>;
424 status = "okay";
5ef346bb
GS		 425
426 ethphy0: ethernet-phy@4 {
427 reg = <4>;
428 };
429
430 ethphy1: ethernet-phy@5 {
431 reg = <5>;
432 };
5e452865
SL		 433};
434
435&cpsw_emac0 {
436 status = "okay";
5ef346bb 437 phy-handle = <&ethphy0>;
5e452865
SL		 438 phy-mode = "rmii";
439 dual_emac_res_vlan = <1>;
440};
441
442&cpsw_emac1 {
443 status = "okay";
5ef346bb 444 phy-handle = <&ethphy1>;
5e452865
SL		 445 phy-mode = "rmii";
446 dual_emac_res_vlan = <2>;
447};
448
5e452865
SL		 449&sham {
450 status = "okay";
451};
452
453&aes {
454 status = "okay";
455};
456
457&gpio0 {
458 ti,no-reset-on-init;
459};
460
461&mmc1 {
462 pinctrl-names = "default";
463 vmmc-supply = <&vmmcsd_fixed>;
464 bus-width = <4>;
465 pinctrl-0 = <&mmc0_pins_default>;
466 cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
467 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
468 status = "okay";
469};
470
471&mmc3 {
472 dmas = <&edma_xbar 12 0 1
473 &edma_xbar 13 0 2>;
474 dma-names = "tx", "rx";
475 pinctrl-names = "default";
476 vmmc-supply = <&vmmcsd_fixed>;
477 bus-width = <8>;
478 pinctrl-0 = <&mmc2_pins_default>;
479 ti,non-removable;
480 status = "okay";
481};
482
483&buttons {
484 pinctrl-names = "default";
485 pinctrl-0 = <&push_button_pins>;
486 #address-cells = <1>;
487 #size-cells = <0>;
488
489 button@0 {
490 label = "push_button";
491 linux,code = <0x100>;
492 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
493 };
494};
495
496/* SPI Busses */
497&spi0 {
498 status = "okay";
499 pinctrl-names = "default";
500 pinctrl-0 = <&spi0_pins>;
501
502 m25p80@0 {
503 compatible = "mx25l6405d";
504 spi-max-frequency = <40000000>;
505
506 reg = <0>;
507 spi-cpol;
508 spi-cpha;
509 #address-cells = <1>;
510 #size-cells = <1>;
511
512 /* reg : The partition's offset and size within the mtd bank. */
513 partitions@0 {
514 label = "MLO";
515 reg = <0x0 0x80000>;
516 };
517
518 partitions@1 {
519 label = "U-Boot";
520 reg = <0x80000 0x100000>;
521 };
522
523 partitions@2 {
524 label = "U-Boot Env";
525 reg = <0x180000 0x20000>;
526 };
527 };
528};
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