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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
c6135a6f UM |
2 | /* |
3 | * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335 | |
4 | * | |
5 | * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ | |
c6135a6f UM |
6 | */ |
7 | ||
8 | #include "am335x-cm-t335.dts" | |
9 | ||
10 | / { | |
11 | model = "CompuLab CM-T335 on SB-T335"; | |
12 | compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"; | |
3089e40e UM |
13 | |
14 | /* DRM display driver */ | |
15 | panel { | |
16 | compatible = "ti,tilcdc,panel"; | |
17 | status = "okay"; | |
18 | pinctrl-names = "default", "sleep"; | |
19 | pinctrl-0 = <&lcd_pins_default>; | |
20 | pinctrl-1 = <&lcd_pins_sleep>; | |
21 | ||
22 | panel-info { | |
23 | ac-bias = <255>; | |
24 | ac-bias-intrpt = <0>; | |
25 | dma-burst-sz = <16>; | |
26 | bpp = <32>; | |
27 | fdd = <0x80>; | |
28 | sync-edge = <0>; | |
29 | sync-ctrl = <1>; | |
30 | raster-order = <0>; | |
31 | fifo-th = <0>; | |
32 | }; | |
33 | display-timings { | |
34 | /* Timing selection performed by U-Boot */ | |
35 | timing0: lcd {/* 800x480p62 */ | |
36 | clock-frequency = <30000000>; | |
37 | hactive = <800>; | |
38 | vactive = <480>; | |
39 | hfront-porch = <39>; | |
40 | hback-porch = <39>; | |
41 | hsync-len = <47>; | |
42 | vback-porch = <29>; | |
43 | vfront-porch = <13>; | |
44 | vsync-len = <2>; | |
45 | hsync-active = <1>; | |
46 | vsync-active = <1>; | |
47 | }; | |
48 | timing1: dvi { /* 1024x768p60 */ | |
49 | clock-frequency = <65000000>; | |
50 | hactive = <1024>; | |
51 | hfront-porch = <24>; | |
52 | hback-porch = <160>; | |
53 | hsync-len = <136>; | |
54 | vactive = <768>; | |
55 | vfront-porch = <3>; | |
56 | vback-porch = <29>; | |
57 | vsync-len = <6>; | |
58 | hsync-active = <0>; | |
59 | vsync-active = <0>; | |
60 | }; | |
61 | }; | |
62 | }; | |
63 | }; | |
64 | ||
65 | &am33xx_pinmux { | |
66 | /* Display */ | |
67 | lcd_pins_default: lcd_pins_default { | |
68 | pinctrl-single,pins = < | |
69 | /* gpmc_ad8.lcd_data23 */ | |
631493a1 | 70 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) |
3089e40e | 71 | /* gpmc_ad9.lcd_data22 */ |
631493a1 | 72 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) |
3089e40e | 73 | /* gpmc_ad10.lcd_data21 */ |
631493a1 | 74 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) |
3089e40e | 75 | /* gpmc_ad11.lcd_data20 */ |
631493a1 | 76 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) |
3089e40e | 77 | /* gpmc_ad12.lcd_data19 */ |
631493a1 | 78 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) |
3089e40e | 79 | /* gpmc_ad13.lcd_data18 */ |
631493a1 | 80 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) |
3089e40e | 81 | /* gpmc_ad14.lcd_data17 */ |
631493a1 | 82 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) |
3089e40e | 83 | /* gpmc_ad15.lcd_data16 */ |
631493a1 CQ |
84 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) |
85 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) | |
86 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) | |
87 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) | |
88 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) | |
89 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) | |
90 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) | |
91 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) | |
92 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) | |
93 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) | |
94 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) | |
95 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) | |
96 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) | |
97 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) | |
98 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) | |
99 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) | |
100 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) | |
101 | AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) | |
102 | AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) | |
103 | AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) | |
104 | AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) | |
3089e40e UM |
105 | >; |
106 | }; | |
107 | ||
108 | lcd_pins_sleep: lcd_pins_sleep { | |
109 | pinctrl-single,pins = < | |
110 | /* gpmc_ad8.lcd_data23 */ | |
631493a1 | 111 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) |
3089e40e | 112 | /* gpmc_ad9.lcd_data22 */ |
631493a1 | 113 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) |
3089e40e | 114 | /* gpmc_ad10.lcd_data21 */ |
631493a1 | 115 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) |
3089e40e | 116 | /* gpmc_ad11.lcd_data20 */ |
631493a1 | 117 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) |
3089e40e | 118 | /* gpmc_ad12.lcd_data19 */ |
631493a1 | 119 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) |
3089e40e | 120 | /* gpmc_ad13.lcd_data18 */ |
631493a1 | 121 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) |
3089e40e | 122 | /* gpmc_ad14.lcd_data17 */ |
631493a1 | 123 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) |
3089e40e | 124 | /* gpmc_ad15.lcd_data16 */ |
631493a1 CQ |
125 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) |
126 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) | |
127 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) | |
128 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) | |
129 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) | |
130 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) | |
131 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) | |
132 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) | |
133 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) | |
134 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) | |
135 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) | |
136 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) | |
137 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) | |
138 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) | |
139 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) | |
140 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) | |
141 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) | |
142 | AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) | |
143 | AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) | |
144 | AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) | |
145 | AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) | |
3089e40e UM |
146 | >; |
147 | }; | |
c6135a6f | 148 | }; |
98e5d898 UM |
149 | |
150 | &i2c0 { | |
151 | /* GPIO extender */ | |
152 | gpio_ext: pca9555@26 { | |
153 | compatible = "nxp,pca9555"; | |
154 | pinctrl-names = "default"; | |
155 | gpio-controller; | |
156 | #gpio-cells = <2>; | |
157 | reg = <0x26>; | |
ccd73f07 | 158 | dvi-ena-hog { |
3089e40e UM |
159 | gpio-hog; |
160 | gpios = <13 GPIO_ACTIVE_HIGH>; | |
161 | output-high; | |
162 | line-name = "dvi-enable"; | |
163 | }; | |
ccd73f07 | 164 | lcd-ena-hog { |
3089e40e UM |
165 | gpio-hog; |
166 | gpios = <11 GPIO_ACTIVE_HIGH>; | |
167 | output-high; | |
168 | line-name = "lcd-enable"; | |
169 | }; | |
98e5d898 UM |
170 | }; |
171 | }; | |
3089e40e UM |
172 | |
173 | /* Display */ | |
174 | &lcdc { | |
175 | status = "okay"; | |
176 | }; |