[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / am33xx-clocks.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for AM33xx clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&scm_clocks {
	sys_clkin_ck: sys_clkin_ck@40 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
		ti,bit-shift = <22>;
		reg = <0x0040>;
	};

	adc_tsc_fck: adc_tsc_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dcan0_fck: dcan0_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dcan1_fck: dcan1_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	mcasp0_fck: mcasp0_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	mcasp1_fck: mcasp1_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	smartreflex0_fck: smartreflex0_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	smartreflex1_fck: smartreflex1_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	sha0_fck: sha0_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	aes0_fck: aes0_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	rng_fck: rng_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&l4ls_gclk>;
		ti,bit-shift = <0>;
		reg = <0x0664>;
	};

	ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&l4ls_gclk>;
		ti,bit-shift = <1>;
		reg = <0x0664>;
	};

	ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&l4ls_gclk>;
		ti,bit-shift = <2>;
		reg = <0x0664>;
	};
};
&prcm_clocks {
	clk_32768_ck: clk_32768_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	clk_rc32k_ck: clk_rc32k_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32000>;
	};

	virt_19200000_ck: virt_19200000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <19200000>;
	};

	virt_24000000_ck: virt_24000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
	};

	virt_25000000_ck: virt_25000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <25000000>;
	};

	virt_26000000_ck: virt_26000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
	};

	tclkin_ck: tclkin_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
	};

	dpll_core_ck: dpll_core_ck@490 {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-core-clock";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x0490>, <0x045c>, <0x0468>;
	};

	dpll_core_x2_ck: dpll_core_x2_ck {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-x2-clock";
		clocks = <&dpll_core_ck>;
	};

	dpll_core_m4_ck: dpll_core_m4_ck@480 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0480>;
		ti,index-starts-at-one;
	};

	dpll_core_m5_ck: dpll_core_m5_ck@484 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0484>;
		ti,index-starts-at-one;
	};

	dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <31>;
		reg = <0x04d8>;
		ti,index-starts-at-one;
	};

	dpll_mpu_ck: dpll_mpu_ck@488 {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-clock";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x0488>, <0x0420>, <0x042c>;
	};

	dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_mpu_ck>;
		ti,max-div = <31>;
		reg = <0x04a8>;
		ti,index-starts-at-one;
	};

	dpll_ddr_ck: dpll_ddr_ck@494 {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-no-gate-clock";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x0494>, <0x0434>, <0x0440>;
	};

	dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_ddr_ck>;
		ti,max-div = <31>;
		reg = <0x04a0>;
		ti,index-starts-at-one;
	};

	dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_ddr_m2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	dpll_disp_ck: dpll_disp_ck@498 {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-no-gate-clock";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x0498>, <0x0448>, <0x0454>;
	};

	dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_disp_ck>;
		ti,max-div = <31>;
		reg = <0x04a4>;
		ti,index-starts-at-one;
		ti,set-rate-parent;
	};

	dpll_per_ck: dpll_per_ck@48c {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-no-gate-j-type-clock";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x048c>, <0x0470>, <0x049c>;
	};

	dpll_per_m2_ck: dpll_per_m2_ck@4ac {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_per_ck>;
		ti,max-div = <31>;
		reg = <0x04ac>;
		ti,index-starts-at-one;
	};

	dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	clk_24mhz: clk_24mhz {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <8>;
	};

	clkdiv32k_ck: clkdiv32k_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&clk_24mhz>;
		clock-mult = <1>;
		clock-div = <732>;
	};

	l3_gclk: l3_gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_m4_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	pruss_ocp_gclk: pruss_ocp_gclk@530 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
		reg = <0x0530>;
	};

	mmu_fck: mmu_fck@914 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_core_m4_ck>;
		ti,bit-shift = <1>;
		reg = <0x0914>;
	};

	timer1_fck: timer1_fck@528 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
		reg = <0x0528>;
	};

	timer2_fck: timer2_fck@508 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x0508>;
	};

	timer3_fck: timer3_fck@50c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x050c>;
	};

	timer4_fck: timer4_fck@510 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x0510>;
	};

	timer5_fck: timer5_fck@518 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x0518>;
	};

	timer6_fck: timer6_fck@51c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x051c>;
	};

	timer7_fck: timer7_fck@504 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x0504>;
	};

	usbotg_fck: usbotg_fck@47c {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_per_ck>;
		ti,bit-shift = <8>;
		reg = <0x047c>;
	};

	dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_m4_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	ieee5000_fck: ieee5000_fck@e4 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_core_m4_div2_ck>;
		ti,bit-shift = <1>;
		reg = <0x00e4>;
	};

	wdt1_fck: wdt1_fck@538 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x0538>;
	};

	l4_rtc_gclk: l4_rtc_gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_m4_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	l4hs_gclk: l4hs_gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_m4_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	l3s_gclk: l3s_gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_m4_div2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	l4fw_gclk: l4fw_gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_m4_div2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	l4ls_gclk: l4ls_gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_m4_div2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	sysclk_div_ck: sysclk_div_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_m4_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_core_m5_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
		reg = <0x0520>;
	};

	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x053c>;
	};

	lcd_gclk: lcd_gclk@534 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
		reg = <0x0534>;
		ti,set-rate-parent;
	};

	mmc_clk: mmc_clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
		ti,bit-shift = <1>;
		reg = <0x052c>;
	};

	gfx_fck_div_ck: gfx_fck_div_ck@52c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&gfx_fclk_clksel_ck>;
		reg = <0x052c>;
		ti,max-div = <2>;
	};

	sysclkout_pre_ck: sysclkout_pre_ck@700 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
		reg = <0x0700>;
	};

	clkout2_div_ck: clkout2_div_ck@700 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&sysclkout_pre_ck>;
		ti,bit-shift = <3>;
		ti,max-div = <8>;
		reg = <0x0700>;
	};

	clkout2_ck: clkout2_ck@700 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&clkout2_div_ck>;
		ti,bit-shift = <7>;
		reg = <0x0700>;
	};
};

&prcm {
	per_cm: per-cm@0 {
		compatible = "ti,omap4-cm";
		reg = <0x0 0x400>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0x400>;

		l4ls_clkctrl: l4ls-clkctrl@38 {
			compatible = "ti,clkctrl";
			reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
			#clock-cells = <2>;
		};

		l3s_clkctrl: l3s-clkctrl@1c {
			compatible = "ti,clkctrl";
			reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
			#clock-cells = <2>;
		};

		l3_clkctrl: l3-clkctrl@24 {
			compatible = "ti,clkctrl";
			reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
			#clock-cells = <2>;
		};

		l4hs_clkctrl: l4hs-clkctrl@120 {
			compatible = "ti,clkctrl";
			reg = <0x120 0x4>;
			#clock-cells = <2>;
		};

		pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
			compatible = "ti,clkctrl";
			reg = <0xe8 0x4>;
			#clock-cells = <2>;
		};

		cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
			compatible = "ti,clkctrl";
			reg = <0x0 0x18>;
			#clock-cells = <2>;
		};

		lcdc_clkctrl: lcdc-clkctrl@18 {
			compatible = "ti,clkctrl";
			reg = <0x18 0x4>;
			#clock-cells = <2>;
		};

		clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
			compatible = "ti,clkctrl";
			reg = <0x14c 0x4>;
			#clock-cells = <2>;
		};
	};

	wkup_cm: wkup-cm@400 {
		compatible = "ti,omap4-cm";
		reg = <0x400 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x400 0x100>;

		l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
			compatible = "ti,clkctrl";
			reg = <0x0 0x10>, <0xb4 0x24>;
			#clock-cells = <2>;
		};

		l3_aon_clkctrl: l3-aon-clkctrl@14 {
			compatible = "ti,clkctrl";
			reg = <0x14 0x4>;
			#clock-cells = <2>;
		};

		l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
			compatible = "ti,clkctrl";
			reg = <0xb0 0x4>;
			#clock-cells = <2>;
		};
	};

	mpu_cm: mpu-cm@600 {
		compatible = "ti,omap4-cm";
		reg = <0x600 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x600 0x100>;

		mpu_clkctrl: mpu-clkctrl@0 {
			compatible = "ti,clkctrl";
			reg = <0x0 0x8>;
			#clock-cells = <2>;
		};
	};

	l4_rtc_cm: l4-rtc-cm@800 {
		compatible = "ti,omap4-cm";
		reg = <0x800 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x800 0x100>;

		l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
			compatible = "ti,clkctrl";
			reg = <0x0 0x4>;
			#clock-cells = <2>;
		};
	};

	gfx_l3_cm: gfx-l3-cm@900 {
		compatible = "ti,omap4-cm";
		reg = <0x900 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x900 0x100>;

		gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
			compatible = "ti,clkctrl";
			reg = <0x0 0x8>;
			#clock-cells = <2>;
		};
	};

	l4_cefuse_cm: l4-cefuse-cm@a00 {
		compatible = "ti,omap4-cm";
		reg = <0xa00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xa00 0x100>;

		l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
			compatible = "ti,clkctrl";
			reg = <0x0 0x24>;
			#clock-cells = <2>;
		};
	};
};
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
ea291c98 TK	2	/*
	3	* Device Tree Source for AM33xx clock data
	4	*
	5	* Copyright (C) 2013 Texas Instruments, Inc.
ea291c98	6	*/
e3bc5358	7	&scm_clocks {
b524cab3	8	sys_clkin_ck: sys_clkin_ck@40 {
ea291c98 TK	9	#clock-cells = <0>;
	10	compatible = "ti,mux-clock";
	11	clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
	12	ti,bit-shift = <22>;
	13	reg = <0x0040>;
	14	};
	15
	16	adc_tsc_fck: adc_tsc_fck {
	17	#clock-cells = <0>;
	18	compatible = "fixed-factor-clock";
	19	clocks = <&sys_clkin_ck>;
	20	clock-mult = <1>;
	21	clock-div = <1>;
	22	};
	23
	24	dcan0_fck: dcan0_fck {
	25	#clock-cells = <0>;
	26	compatible = "fixed-factor-clock";
	27	clocks = <&sys_clkin_ck>;
	28	clock-mult = <1>;
	29	clock-div = <1>;
	30	};
	31
	32	dcan1_fck: dcan1_fck {
	33	#clock-cells = <0>;
	34	compatible = "fixed-factor-clock";
	35	clocks = <&sys_clkin_ck>;
	36	clock-mult = <1>;
	37	clock-div = <1>;
	38	};
	39
	40	mcasp0_fck: mcasp0_fck {
	41	#clock-cells = <0>;
	42	compatible = "fixed-factor-clock";
	43	clocks = <&sys_clkin_ck>;
	44	clock-mult = <1>;
	45	clock-div = <1>;
	46	};
	47
	48	mcasp1_fck: mcasp1_fck {
	49	#clock-cells = <0>;
	50	compatible = "fixed-factor-clock";
	51	clocks = <&sys_clkin_ck>;
	52	clock-mult = <1>;
	53	clock-div = <1>;
	54	};
	55
	56	smartreflex0_fck: smartreflex0_fck {
	57	#clock-cells = <0>;
	58	compatible = "fixed-factor-clock";
	59	clocks = <&sys_clkin_ck>;
	60	clock-mult = <1>;
	61	clock-div = <1>;
	62	};
	63
	64	smartreflex1_fck: smartreflex1_fck {
	65	#clock-cells = <0>;
	66	compatible = "fixed-factor-clock";
	67	clocks = <&sys_clkin_ck>;
	68	clock-mult = <1>;
	69	clock-div = <1>;
	70	};
	71
	72	sha0_fck: sha0_fck {
73	#clock-cells = <0>;
74	compatible = "fixed-factor-clock";
75	clocks = <&sys_clkin_ck>;
76	clock-mult = <1>;
77	clock-div = <1>;
78	};
79
80	aes0_fck: aes0_fck {
81	#clock-cells = <0>;
82	compatible = "fixed-factor-clock";
83	clocks = <&sys_clkin_ck>;
84	clock-mult = <1>;
85	clock-div = <1>;
86	};
87
88	rng_fck: rng_fck {
89	#clock-cells = <0>;
90	compatible = "fixed-factor-clock";
91	clocks = <&sys_clkin_ck>;
92	clock-mult = <1>;
93	clock-div = <1>;
94	};
95
9e100eba	96	ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
ea291c98	97	#clock-cells = <0>;
9e100eba	98	compatible = "ti,gate-clock";
6e22616e	99	clocks = <&l4ls_gclk>;
ea291c98 TK	100	ti,bit-shift = <0>;
	101	reg = <0x0664>;
	102	};
	103
9e100eba	104	ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
ea291c98	105	#clock-cells = <0>;
9e100eba	106	compatible = "ti,gate-clock";
6e22616e	107	clocks = <&l4ls_gclk>;
ea291c98 TK	108	ti,bit-shift = <1>;
	109	reg = <0x0664>;
	110	};
	111
9e100eba	112	ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
ea291c98	113	#clock-cells = <0>;
9e100eba	114	compatible = "ti,gate-clock";
6e22616e	115	clocks = <&l4ls_gclk>;
ea291c98 TK	116	ti,bit-shift = <2>;
	117	reg = <0x0664>;
	118	};
ea291c98 TK	119	};
	120	&prcm_clocks {
	121	clk_32768_ck: clk_32768_ck {
	122	#clock-cells = <0>;
	123	compatible = "fixed-clock";
	124	clock-frequency = <32768>;
	125	};
	126
	127	clk_rc32k_ck: clk_rc32k_ck {
	128	#clock-cells = <0>;
	129	compatible = "fixed-clock";
	130	clock-frequency = <32000>;
	131	};
	132
	133	virt_19200000_ck: virt_19200000_ck {
	134	#clock-cells = <0>;
	135	compatible = "fixed-clock";
	136	clock-frequency = <19200000>;
	137	};
	138
	139	virt_24000000_ck: virt_24000000_ck {
	140	#clock-cells = <0>;
	141	compatible = "fixed-clock";
	142	clock-frequency = <24000000>;
	143	};
	144
	145	virt_25000000_ck: virt_25000000_ck {
	146	#clock-cells = <0>;
	147	compatible = "fixed-clock";
	148	clock-frequency = <25000000>;
	149	};
	150
	151	virt_26000000_ck: virt_26000000_ck {
	152	#clock-cells = <0>;
	153	compatible = "fixed-clock";
	154	clock-frequency = <26000000>;
	155	};
	156
	157	tclkin_ck: tclkin_ck {
	158	#clock-cells = <0>;
	159	compatible = "fixed-clock";
	160	clock-frequency = <12000000>;
	161	};
	162
b524cab3	163	dpll_core_ck: dpll_core_ck@490 {
ea291c98 TK	164	#clock-cells = <0>;
	165	compatible = "ti,am3-dpll-core-clock";
	166	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
	167	reg = <0x0490>, <0x045c>, <0x0468>;
	168	};
	169
	170	dpll_core_x2_ck: dpll_core_x2_ck {
	171	#clock-cells = <0>;
	172	compatible = "ti,am3-dpll-x2-clock";
	173	clocks = <&dpll_core_ck>;
	174	};
	175
b524cab3	176	dpll_core_m4_ck: dpll_core_m4_ck@480 {
ea291c98 TK	177	#clock-cells = <0>;
	178	compatible = "ti,divider-clock";
	179	clocks = <&dpll_core_x2_ck>;
	180	ti,max-div = <31>;
	181	reg = <0x0480>;
	182	ti,index-starts-at-one;
	183	};
	184
b524cab3	185	dpll_core_m5_ck: dpll_core_m5_ck@484 {
ea291c98 TK	186	#clock-cells = <0>;
	187	compatible = "ti,divider-clock";
	188	clocks = <&dpll_core_x2_ck>;
	189	ti,max-div = <31>;
	190	reg = <0x0484>;
	191	ti,index-starts-at-one;
	192	};
	193
b524cab3	194	dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
ea291c98 TK	195	#clock-cells = <0>;
	196	compatible = "ti,divider-clock";
	197	clocks = <&dpll_core_x2_ck>;
	198	ti,max-div = <31>;
	199	reg = <0x04d8>;
	200	ti,index-starts-at-one;
	201	};
	202
b524cab3	203	dpll_mpu_ck: dpll_mpu_ck@488 {
ea291c98 TK	204	#clock-cells = <0>;
	205	compatible = "ti,am3-dpll-clock";
	206	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
	207	reg = <0x0488>, <0x0420>, <0x042c>;
	208	};
	209
b524cab3	210	dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
ea291c98 TK	211	#clock-cells = <0>;
	212	compatible = "ti,divider-clock";
	213	clocks = <&dpll_mpu_ck>;
	214	ti,max-div = <31>;
	215	reg = <0x04a8>;
	216	ti,index-starts-at-one;
	217	};
	218
b524cab3	219	dpll_ddr_ck: dpll_ddr_ck@494 {
ea291c98 TK	220	#clock-cells = <0>;
	221	compatible = "ti,am3-dpll-no-gate-clock";
	222	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
	223	reg = <0x0494>, <0x0434>, <0x0440>;
	224	};
	225
b524cab3	226	dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
ea291c98 TK	227	#clock-cells = <0>;
	228	compatible = "ti,divider-clock";
	229	clocks = <&dpll_ddr_ck>;
	230	ti,max-div = <31>;
	231	reg = <0x04a0>;
	232	ti,index-starts-at-one;
	233	};
	234
	235	dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
	236	#clock-cells = <0>;
	237	compatible = "fixed-factor-clock";
	238	clocks = <&dpll_ddr_m2_ck>;
	239	clock-mult = <1>;
	240	clock-div = <2>;
	241	};
	242
b524cab3	243	dpll_disp_ck: dpll_disp_ck@498 {
ea291c98 TK	244	#clock-cells = <0>;
	245	compatible = "ti,am3-dpll-no-gate-clock";
	246	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
	247	reg = <0x0498>, <0x0448>, <0x0454>;
	248	};
	249
b524cab3	250	dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
ea291c98 TK	251	#clock-cells = <0>;
	252	compatible = "ti,divider-clock";
	253	clocks = <&dpll_disp_ck>;
	254	ti,max-div = <31>;
	255	reg = <0x04a4>;
	256	ti,index-starts-at-one;
	257	ti,set-rate-parent;
	258	};
	259
b524cab3	260	dpll_per_ck: dpll_per_ck@48c {
ea291c98 TK	261	#clock-cells = <0>;
	262	compatible = "ti,am3-dpll-no-gate-j-type-clock";
	263	clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
	264	reg = <0x048c>, <0x0470>, <0x049c>;
	265	};
	266
b524cab3	267	dpll_per_m2_ck: dpll_per_m2_ck@4ac {
ea291c98 TK	268	#clock-cells = <0>;
	269	compatible = "ti,divider-clock";
	270	clocks = <&dpll_per_ck>;
	271	ti,max-div = <31>;
	272	reg = <0x04ac>;
	273	ti,index-starts-at-one;
	274	};
	275
	276	dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
	277	#clock-cells = <0>;
	278	compatible = "fixed-factor-clock";
	279	clocks = <&dpll_per_m2_ck>;
	280	clock-mult = <1>;
	281	clock-div = <4>;
	282	};
	283
	284	dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
	285	#clock-cells = <0>;
	286	compatible = "fixed-factor-clock";
	287	clocks = <&dpll_per_m2_ck>;
	288	clock-mult = <1>;
	289	clock-div = <4>;
	290	};
	291
ea291c98 TK	292	clk_24mhz: clk_24mhz {
	293	#clock-cells = <0>;
	294	compatible = "fixed-factor-clock";
	295	clocks = <&dpll_per_m2_ck>;
	296	clock-mult = <1>;
	297	clock-div = <8>;
	298	};
	299
	300	clkdiv32k_ck: clkdiv32k_ck {
	301	#clock-cells = <0>;
	302	compatible = "fixed-factor-clock";
	303	clocks = <&clk_24mhz>;
	304	clock-mult = <1>;
	305	clock-div = <732>;
	306	};
	307
ea291c98 TK	308	l3_gclk: l3_gclk {
	309	#clock-cells = <0>;
	310	compatible = "fixed-factor-clock";
	311	clocks = <&dpll_core_m4_ck>;
	312	clock-mult = <1>;
	313	clock-div = <1>;
	314	};
	315
b524cab3	316	pruss_ocp_gclk: pruss_ocp_gclk@530 {
ea291c98 TK	317	#clock-cells = <0>;
	318	compatible = "ti,mux-clock";
	319	clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
	320	reg = <0x0530>;
	321	};
	322
b524cab3	323	mmu_fck: mmu_fck@914 {
ea291c98 TK	324	#clock-cells = <0>;
	325	compatible = "ti,gate-clock";
	326	clocks = <&dpll_core_m4_ck>;
	327	ti,bit-shift = <1>;
	328	reg = <0x0914>;
	329	};
	330
b524cab3	331	timer1_fck: timer1_fck@528 {
ea291c98 TK	332	#clock-cells = <0>;
ea291c98 TK	333	compatible = "ti,mux-clock";
69fd70c7	334	clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
ea291c98 TK	335	reg = <0x0528>;
	336	};
	337
b524cab3	338	timer2_fck: timer2_fck@508 {
ea291c98 TK	339	#clock-cells = <0>;
ea291c98 TK	340	compatible = "ti,mux-clock";
69fd70c7	341	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
ea291c98 TK	342	reg = <0x0508>;
	343	};
	344
b524cab3	345	timer3_fck: timer3_fck@50c {
ea291c98 TK	346	#clock-cells = <0>;
ea291c98 TK	347	compatible = "ti,mux-clock";
69fd70c7	348	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
ea291c98 TK	349	reg = <0x050c>;
	350	};
	351
b524cab3	352	timer4_fck: timer4_fck@510 {
ea291c98 TK	353	#clock-cells = <0>;
ea291c98 TK	354	compatible = "ti,mux-clock";
69fd70c7	355	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
ea291c98 TK	356	reg = <0x0510>;
	357	};
	358
b524cab3	359	timer5_fck: timer5_fck@518 {
ea291c98 TK	360	#clock-cells = <0>;
ea291c98 TK	361	compatible = "ti,mux-clock";
69fd70c7	362	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
ea291c98 TK	363	reg = <0x0518>;
	364	};
	365
b524cab3	366	timer6_fck: timer6_fck@51c {
ea291c98 TK	367	#clock-cells = <0>;
ea291c98 TK	368	compatible = "ti,mux-clock";
69fd70c7	369	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
ea291c98 TK	370	reg = <0x051c>;
	371	};
	372
b524cab3	373	timer7_fck: timer7_fck@504 {
ea291c98 TK	374	#clock-cells = <0>;
ea291c98 TK	375	compatible = "ti,mux-clock";
69fd70c7	376	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
ea291c98 TK	377	reg = <0x0504>;
	378	};
	379
b524cab3	380	usbotg_fck: usbotg_fck@47c {
ea291c98 TK	381	#clock-cells = <0>;
	382	compatible = "ti,gate-clock";
	383	clocks = <&dpll_per_ck>;
	384	ti,bit-shift = <8>;
	385	reg = <0x047c>;
	386	};
	387
	388	dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
	389	#clock-cells = <0>;
	390	compatible = "fixed-factor-clock";
	391	clocks = <&dpll_core_m4_ck>;
	392	clock-mult = <1>;
	393	clock-div = <2>;
	394	};
	395
b524cab3	396	ieee5000_fck: ieee5000_fck@e4 {
ea291c98 TK	397	#clock-cells = <0>;
	398	compatible = "ti,gate-clock";
	399	clocks = <&dpll_core_m4_div2_ck>;
	400	ti,bit-shift = <1>;
	401	reg = <0x00e4>;
	402	};
	403
b524cab3	404	wdt1_fck: wdt1_fck@538 {
ea291c98 TK	405	#clock-cells = <0>;
ea291c98 TK	406	compatible = "ti,mux-clock";
69fd70c7	407	clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
ea291c98 TK	408	reg = <0x0538>;
	409	};
	410
	411	l4_rtc_gclk: l4_rtc_gclk {
	412	#clock-cells = <0>;
	413	compatible = "fixed-factor-clock";
	414	clocks = <&dpll_core_m4_ck>;
	415	clock-mult = <1>;
	416	clock-div = <2>;
	417	};
	418
	419	l4hs_gclk: l4hs_gclk {
	420	#clock-cells = <0>;
	421	compatible = "fixed-factor-clock";
	422	clocks = <&dpll_core_m4_ck>;
	423	clock-mult = <1>;
	424	clock-div = <1>;
	425	};
	426
	427	l3s_gclk: l3s_gclk {
	428	#clock-cells = <0>;
	429	compatible = "fixed-factor-clock";
	430	clocks = <&dpll_core_m4_div2_ck>;
	431	clock-mult = <1>;
	432	clock-div = <1>;
	433	};
	434
	435	l4fw_gclk: l4fw_gclk {
	436	#clock-cells = <0>;
	437	compatible = "fixed-factor-clock";
	438	clocks = <&dpll_core_m4_div2_ck>;
	439	clock-mult = <1>;
	440	clock-div = <1>;
	441	};
	442
	443	l4ls_gclk: l4ls_gclk {
	444	#clock-cells = <0>;
	445	compatible = "fixed-factor-clock";
	446	clocks = <&dpll_core_m4_div2_ck>;
	447	clock-mult = <1>;
	448	clock-div = <1>;
	449	};
	450
	451	sysclk_div_ck: sysclk_div_ck {
	452	#clock-cells = <0>;
	453	compatible = "fixed-factor-clock";
	454	clocks = <&dpll_core_m4_ck>;
	455	clock-mult = <1>;
	456	clock-div = <1>;
	457	};
	458
	459	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
	460	#clock-cells = <0>;
	461	compatible = "fixed-factor-clock";
	462	clocks = <&dpll_core_m5_ck>;
	463	clock-mult = <1>;
	464	clock-div = <2>;
	465	};
	466
b524cab3	467	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
ea291c98 TK	468	#clock-cells = <0>;
	469	compatible = "ti,mux-clock";
	470	clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
	471	reg = <0x0520>;
	472	};
	473
b524cab3	474	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
ea291c98 TK	475	#clock-cells = <0>;
ea291c98 TK	476	compatible = "ti,mux-clock";
69fd70c7	477	clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
ea291c98 TK	478	reg = <0x053c>;
	479	};
	480
b524cab3	481	lcd_gclk: lcd_gclk@534 {
ea291c98 TK	482	#clock-cells = <0>;
	483	compatible = "ti,mux-clock";
	484	clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
	485	reg = <0x0534>;
	486	ti,set-rate-parent;
	487	};
	488
	489	mmc_clk: mmc_clk {
	490	#clock-cells = <0>;
	491	compatible = "fixed-factor-clock";
	492	clocks = <&dpll_per_m2_ck>;
	493	clock-mult = <1>;
	494	clock-div = <2>;
	495	};
	496
b524cab3	497	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
ea291c98 TK	498	#clock-cells = <0>;
	499	compatible = "ti,mux-clock";
	500	clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
	501	ti,bit-shift = <1>;
	502	reg = <0x052c>;
	503	};
	504
b524cab3	505	gfx_fck_div_ck: gfx_fck_div_ck@52c {
ea291c98 TK	506	#clock-cells = <0>;
	507	compatible = "ti,divider-clock";
	508	clocks = <&gfx_fclk_clksel_ck>;
	509	reg = <0x052c>;
	510	ti,max-div = <2>;
	511	};
	512
b524cab3	513	sysclkout_pre_ck: sysclkout_pre_ck@700 {
ea291c98 TK	514	#clock-cells = <0>;
	515	compatible = "ti,mux-clock";
	516	clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
	517	reg = <0x0700>;
	518	};
	519
b524cab3	520	clkout2_div_ck: clkout2_div_ck@700 {
ea291c98 TK	521	#clock-cells = <0>;
	522	compatible = "ti,divider-clock";
	523	clocks = <&sysclkout_pre_ck>;
	524	ti,bit-shift = <3>;
	525	ti,max-div = <8>;
	526	reg = <0x0700>;
	527	};
	528
b524cab3	529	clkout2_ck: clkout2_ck@700 {
ea291c98 TK	530	#clock-cells = <0>;
	531	compatible = "ti,gate-clock";
	532	clocks = <&clkout2_div_ck>;
	533	ti,bit-shift = <7>;
	534	reg = <0x0700>;
	535	};
	536	};
	537
0537634f	538	&prcm {
69fd70c7	539	per_cm: per-cm@0 {
0537634f	540	compatible = "ti,omap4-cm";
69fd70c7	541	reg = <0x0 0x400>;
0537634f TK	542	#address-cells = <1>;
0537634f TK	543	#size-cells = <1>;
69fd70c7	544	ranges = <0 0x0 0x400>;
0537634f	545
69fd70c7	546	l4ls_clkctrl: l4ls-clkctrl@38 {
0537634f	547	compatible = "ti,clkctrl";
69fd70c7 TK	548	reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
	549	#clock-cells = <2>;
	550	};
	551
	552	l3s_clkctrl: l3s-clkctrl@1c {
	553	compatible = "ti,clkctrl";
	554	reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
	555	#clock-cells = <2>;
	556	};
	557
	558	l3_clkctrl: l3-clkctrl@24 {
	559	compatible = "ti,clkctrl";
	560	reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
	561	#clock-cells = <2>;
	562	};
	563
	564	l4hs_clkctrl: l4hs-clkctrl@120 {
	565	compatible = "ti,clkctrl";
	566	reg = <0x120 0x4>;
	567	#clock-cells = <2>;
	568	};
	569
	570	pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
	571	compatible = "ti,clkctrl";
	572	reg = <0xe8 0x4>;
	573	#clock-cells = <2>;
	574	};
	575
	576	cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
	577	compatible = "ti,clkctrl";
	578	reg = <0x0 0x18>;
	579	#clock-cells = <2>;
	580	};
	581
	582	lcdc_clkctrl: lcdc-clkctrl@18 {
	583	compatible = "ti,clkctrl";
	584	reg = <0x18 0x4>;
	585	#clock-cells = <2>;
	586	};
	587
	588	clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
	589	compatible = "ti,clkctrl";
	590	reg = <0x14c 0x4>;
0537634f TK	591	#clock-cells = <2>;
	592	};
	593	};
	594
69fd70c7	595	wkup_cm: wkup-cm@400 {
0537634f TK	596	compatible = "ti,omap4-cm";
	597	reg = <0x400 0x100>;
	598	#address-cells = <1>;
	599	#size-cells = <1>;
	600	ranges = <0 0x400 0x100>;
	601
69fd70c7 TK	602	l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
	603	compatible = "ti,clkctrl";
	604	reg = <0x0 0x10>, <0xb4 0x24>;
	605	#clock-cells = <2>;
	606	};
	607
	608	l3_aon_clkctrl: l3-aon-clkctrl@14 {
	609	compatible = "ti,clkctrl";
	610	reg = <0x14 0x4>;
	611	#clock-cells = <2>;
	612	};
	613
	614	l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
0537634f	615	compatible = "ti,clkctrl";
69fd70c7	616	reg = <0xb0 0x4>;
0537634f TK	617	#clock-cells = <2>;
	618	};
	619	};
	620
69fd70c7	621	mpu_cm: mpu-cm@600 {
0537634f TK	622	compatible = "ti,omap4-cm";
	623	reg = <0x600 0x100>;
	624	#address-cells = <1>;
	625	#size-cells = <1>;
	626	ranges = <0 0x600 0x100>;
	627
69fd70c7	628	mpu_clkctrl: mpu-clkctrl@0 {
0537634f	629	compatible = "ti,clkctrl";
69fd70c7	630	reg = <0x0 0x8>;
0537634f TK	631	#clock-cells = <2>;
	632	};
	633	};
	634
69fd70c7	635	l4_rtc_cm: l4-rtc-cm@800 {
0537634f TK	636	compatible = "ti,omap4-cm";
	637	reg = <0x800 0x100>;
	638	#address-cells = <1>;
	639	#size-cells = <1>;
	640	ranges = <0 0x800 0x100>;
	641
69fd70c7	642	l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
0537634f TK	643	compatible = "ti,clkctrl";
	644	reg = <0x0 0x4>;
	645	#clock-cells = <2>;
	646	};
	647	};
	648
69fd70c7	649	gfx_l3_cm: gfx-l3-cm@900 {
0537634f TK	650	compatible = "ti,omap4-cm";
	651	reg = <0x900 0x100>;
	652	#address-cells = <1>;
	653	#size-cells = <1>;
	654	ranges = <0 0x900 0x100>;
	655
69fd70c7	656	gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
0537634f	657	compatible = "ti,clkctrl";
69fd70c7	658	reg = <0x0 0x8>;
0537634f TK	659	#clock-cells = <2>;
	660	};
	661	};
	662
69fd70c7	663	l4_cefuse_cm: l4-cefuse-cm@a00 {
0537634f TK	664	compatible = "ti,omap4-cm";
	665	reg = <0xa00 0x100>;
	666	#address-cells = <1>;
	667	#size-cells = <1>;
	668	ranges = <0 0xa00 0x100>;
	669
69fd70c7	670	l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
0537634f	671	compatible = "ti,clkctrl";
69fd70c7	672	reg = <0x0 0x24>;
0537634f TK	673	#clock-cells = <2>;
0537634f TK	674	};
ea291c98 TK	675	};
ea291c98 TK	676	};