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Merge tag 'sound-4.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / am33xx.dtsi
CommitLineData
5fc0b42a
AC		 1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
e94233c2 11#include <dt-bindings/gpio/gpio.h>
6a8a6b65 12#include <dt-bindings/pinctrl/am33xx.h>
e94233c2 13
5fc0b42a
AC		 14/ {
15 compatible = "ti,am33xx";
4c94ac29 16 interrupt-parent = <&intc>;
f8bf0161
JMC		 17 #address-cells = <1>;
18 #size-cells = <1>;
1d8d6d3f 19 chosen { };
5fc0b42a
AC		 20
21 aliases {
6a968678
NM		 22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
dde3b0d6
VH		 25 serial0 = &uart0;
26 serial1 = &uart1;
27 serial2 = &uart2;
28 serial3 = &uart3;
29 serial4 = &uart4;
30 serial5 = &uart5;
7a57ee87
AC		 31 d_can0 = &dcan0;
32 d_can1 = &dcan1;
97238b35
SAS		 33 usb0 = &usb0;
34 usb1 = &usb1;
35 phy0 = &usb0_phy;
36 phy1 = &usb1_phy;
8170056d
DM		 37 ethernet0 = &cpsw_emac0;
38 ethernet1 = &cpsw_emac1;
cddfae25
SM		 39 spi0 = &spi0;
40 spi1 = &spi1;
5fc0b42a
AC		 41 };
42
43 cpus {
2e0d513f
LP		 44 #address-cells = <1>;
45 #size-cells = <0>;
5fc0b42a
AC		 46 cpu@0 {
47 compatible = "arm,cortex-a8";
2e0d513f
LP		 48 device_type = "cpu";
49 reg = <0>;
efeedcf2 50
72ac40fc 51 operating-points-v2 = <&cpu0_opp_table>;
8d766fa2
NM		 52
53 clocks = <&dpll_mpu_ck>;
54 clock-names = "cpu";
55
efeedcf2 56 clock-latency = <300000>; /* From omap-cpufreq driver */
5fc0b42a
AC		 57 };
58 };
59
72ac40fc
DG		 60 cpu0_opp_table: opp-table {
61 compatible = "operating-points-v2-ti-cpu";
62 syscon = <&scm_conf>;
63
64 /*
65 * The three following nodes are marked with opp-suspend
66 * because the can not be enabled simultaneously on a
67 * single SoC.
68 */
b9cb2ba7 69 opp50-300000000 {
72ac40fc
DG		 70 opp-hz = /bits/ 64 <300000000>;
71 opp-microvolt = <950000 931000 969000>;
72 opp-supported-hw = <0x06 0x0010>;
73 opp-suspend;
74 };
75
b9cb2ba7 76 opp100-275000000 {
72ac40fc
DG		 77 opp-hz = /bits/ 64 <275000000>;
78 opp-microvolt = <1100000 1078000 1122000>;
79 opp-supported-hw = <0x01 0x00FF>;
80 opp-suspend;
81 };
82
b9cb2ba7 83 opp100-300000000 {
72ac40fc
DG		 84 opp-hz = /bits/ 64 <300000000>;
85 opp-microvolt = <1100000 1078000 1122000>;
86 opp-supported-hw = <0x06 0x0020>;
87 opp-suspend;
88 };
89
b9cb2ba7 90 opp100-500000000 {
72ac40fc
DG		 91 opp-hz = /bits/ 64 <500000000>;
92 opp-microvolt = <1100000 1078000 1122000>;
93 opp-supported-hw = <0x01 0xFFFF>;
94 };
95
b9cb2ba7 96 opp100-600000000 {
72ac40fc
DG		 97 opp-hz = /bits/ 64 <600000000>;
98 opp-microvolt = <1100000 1078000 1122000>;
99 opp-supported-hw = <0x06 0x0040>;
100 };
101
b9cb2ba7 102 opp120-600000000 {
72ac40fc
DG		 103 opp-hz = /bits/ 64 <600000000>;
104 opp-microvolt = <1200000 1176000 1224000>;
105 opp-supported-hw = <0x01 0xFFFF>;
106 };
107
b9cb2ba7 108 opp120-720000000 {
72ac40fc
DG		 109 opp-hz = /bits/ 64 <720000000>;
110 opp-microvolt = <1200000 1176000 1224000>;
111 opp-supported-hw = <0x06 0x0080>;
112 };
113
b9cb2ba7 114 oppturbo-720000000 {
72ac40fc
DG		 115 opp-hz = /bits/ 64 <720000000>;
116 opp-microvolt = <1260000 1234800 1285200>;
117 opp-supported-hw = <0x01 0xFFFF>;
118 };
119
b9cb2ba7 120 oppturbo-800000000 {
72ac40fc
DG		 121 opp-hz = /bits/ 64 <800000000>;
122 opp-microvolt = <1260000 1234800 1285200>;
123 opp-supported-hw = <0x06 0x0100>;
124 };
125
b9cb2ba7 126 oppnitro-1000000000 {
72ac40fc
DG		 127 opp-hz = /bits/ 64 <1000000000>;
128 opp-microvolt = <1325000 1298500 1351500>;
129 opp-supported-hw = <0x04 0x0200>;
130 };
131 };
132
cd57dc5a 133 pmu@4b000000 {
6797cdbe
AB		 134 compatible = "arm,cortex-a8-pmu";
135 interrupts = <3>;
cd57dc5a
TL		 136 reg = <0x4b000000 0x1000000>;
137 ti,hwmods = "debugss";
6797cdbe
AB		 138 };
139
5fc0b42a 140 /*
5c5be9db 141 * The soc node represents the soc top level view. It is used for IPs
5fc0b42a
AC		 142 * that are not memory mapped in the MPU view or for the MPU itself.
143 */
144 soc {
145 compatible = "ti,omap-infra";
146 mpu {
147 compatible = "ti,omap3-mpu";
148 ti,hwmods = "mpu";
149 };
150 };
151
152 /*
153 * XXX: Use a flat representation of the AM33XX interconnect.
b7ab524b
GU		 154 * The real AM33XX interconnect network is quite complex. Since
155 * it will not bring real advantage to represent that in DT
5fc0b42a
AC		 156 * for the moment, just use a fake OCP bus entry to represent
157 * the whole bus hierarchy.
158 */
159 ocp {
160 compatible = "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164 ti,hwmods = "l3_main";
165
e3bc5358
TK		 166 l4_wkup: l4_wkup@44c00000 {
167 compatible = "ti,am3-l4-wkup", "simple-bus";
168 #address-cells = <1>;
169 #size-cells = <1>;
170 ranges = <0 0x44c00000 0x280000>;
ea291c98 171
d129be27
SA		 172 wkup_m3: wkup_m3@100000 {
173 compatible = "ti,am3352-wkup-m3";
174 reg = <0x100000 0x4000>,
175 <0x180000 0x2000>;
176 reg-names = "umem", "dmem";
177 ti,hwmods = "wkup_m3";
178 ti,pm-firmware = "am335x-pm-firmware.elf";
179 };
180
e3bc5358
TK		 181 prcm: prcm@200000 {
182 compatible = "ti,am3-prcm";
183 reg = <0x200000 0x4000>;
ea291c98 184
e3bc5358
TK		 185 prcm_clocks: clocks {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
ea291c98 189
e3bc5358
TK		 190 prcm_clockdomains: clockdomains {
191 };
ea291c98
TK		 192 };
193
e3bc5358
TK		 194 scm: scm@210000 {
195 compatible = "ti,am3-scm", "simple-bus";
196 reg = <0x210000 0x2000>;
197 #address-cells = <1>;
198 #size-cells = <1>;
be76fd31 199 #pinctrl-cells = <1>;
e3bc5358
TK		 200 ranges = <0 0x210000 0x2000>;
201
202 am33xx_pinmux: pinmux@800 {
203 compatible = "pinctrl-single";
204 reg = <0x800 0x238>;
205 #address-cells = <1>;
206 #size-cells = <0>;
be76fd31 207 #pinctrl-cells = <1>;
e3bc5358
TK		 208 pinctrl-single,register-width = <32>;
209 pinctrl-single,function-mask = <0x7f>;
210 };
211
212 scm_conf: scm_conf@0 {
1aa09df0 213 compatible = "syscon", "simple-bus";
e3bc5358
TK		 214 reg = <0x0 0x800>;
215 #address-cells = <1>;
216 #size-cells = <1>;
1aa09df0 217 ranges = <0 0 0x800>;
e3bc5358
TK		 218
219 scm_clocks: clocks {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 };
223 };
224
99937129
SA		 225 wkup_m3_ipc: wkup_m3_ipc@1324 {
226 compatible = "ti,am3352-wkup-m3-ipc";
227 reg = <0x1324 0x24>;
228 interrupts = <78>;
229 ti,rproc = <&wkup_m3>;
230 mboxes = <&mailbox &mbox_wkupm3>;
231 };
232
b5e50906
PU		 233 edma_xbar: dma-router@f90 {
234 compatible = "ti,am335x-edma-crossbar";
235 reg = <0xf90 0x40>;
236 #dma-cells = <3>;
237 dma-requests = <32>;
238 dma-masters = <&edma>;
239 };
240
e3bc5358
TK		 241 scm_clockdomains: clockdomains {
242 };
ea291c98
TK		 243 };
244 };
245
5fc0b42a 246 intc: interrupt-controller@48200000 {
cab82b76 247 compatible = "ti,am33xx-intc";
5fc0b42a
AC		 248 interrupt-controller;
249 #interrupt-cells = <1>;
5fc0b42a
AC		 250 reg = <0x48200000 0x1000>;
251 };
252
505975d3 253 edma: edma@49000000 {
b5e50906
PU		 254 compatible = "ti,edma3-tpcc";
255 ti,hwmods = "tpcc";
256 reg = <0x49000000 0x10000>;
257 reg-names = "edma3_cc";
505975d3 258 interrupts = <12 13 14>;
a5206553 259 interrupt-names = "edma3_ccint", "edma3_mperr",
b5e50906
PU		 260 "edma3_ccerrint";
261 dma-requests = <64>;
262 #dma-cells = <2>;
263
264 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
265 <&edma_tptc2 0>;
266
267 ti,edma-memcpy-channels = <20 21>;
268 };
269
270 edma_tptc0: tptc@49800000 {
271 compatible = "ti,edma3-tptc";
272 ti,hwmods = "tptc0";
273 reg = <0x49800000 0x100000>;
274 interrupts = <112>;
275 interrupt-names = "edma3_tcerrint";
276 };
277
278 edma_tptc1: tptc@49900000 {
279 compatible = "ti,edma3-tptc";
280 ti,hwmods = "tptc1";
281 reg = <0x49900000 0x100000>;
282 interrupts = <113>;
283 interrupt-names = "edma3_tcerrint";
284 };
285
286 edma_tptc2: tptc@49a00000 {
287 compatible = "ti,edma3-tptc";
288 ti,hwmods = "tptc2";
289 reg = <0x49a00000 0x100000>;
290 interrupts = <114>;
291 interrupt-names = "edma3_tcerrint";
505975d3
MP		 292 };
293
b918e2c0 294 gpio0: gpio@44e07000 {
5fc0b42a
AC		 295 compatible = "ti,omap4-gpio";
296 ti,hwmods = "gpio1";
297 gpio-controller;
298 #gpio-cells = <2>;
299 interrupt-controller;
5eac0eb7 300 #interrupt-cells = <2>;
4462b31c 301 reg = <0x44e07000 0x1000>;
4462b31c 302 interrupts = <96>;
5fc0b42a
AC		 303 };
304
b918e2c0 305 gpio1: gpio@4804c000 {
5fc0b42a
AC		 306 compatible = "ti,omap4-gpio";
307 ti,hwmods = "gpio2";
308 gpio-controller;
309 #gpio-cells = <2>;
310 interrupt-controller;
5eac0eb7 311 #interrupt-cells = <2>;
4462b31c 312 reg = <0x4804c000 0x1000>;
4462b31c 313 interrupts = <98>;
5fc0b42a
AC		 314 };
315
b918e2c0 316 gpio2: gpio@481ac000 {
5fc0b42a
AC		 317 compatible = "ti,omap4-gpio";
318 ti,hwmods = "gpio3";
319 gpio-controller;
320 #gpio-cells = <2>;
321 interrupt-controller;
5eac0eb7 322 #interrupt-cells = <2>;
4462b31c 323 reg = <0x481ac000 0x1000>;
4462b31c 324 interrupts = <32>;
5fc0b42a
AC		 325 };
326
b918e2c0 327 gpio3: gpio@481ae000 {
5fc0b42a
AC		 328 compatible = "ti,omap4-gpio";
329 ti,hwmods = "gpio4";
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
5eac0eb7 333 #interrupt-cells = <2>;
4462b31c 334 reg = <0x481ae000 0x1000>;
4462b31c 335 interrupts = <62>;
5fc0b42a
AC		 336 };
337
dde3b0d6 338 uart0: serial@44e09000 {
4fcdff9b 339 compatible = "ti,am3352-uart", "ti,omap3-uart";
5fc0b42a
AC		 340 ti,hwmods = "uart1";
341 clock-frequency = <48000000>;
4462b31c 342 reg = <0x44e09000 0x2000>;
4462b31c 343 interrupts = <72>;
53d91034 344 status = "disabled";
b5e50906 345 dmas = <&edma 26 0>, <&edma 27 0>;
13fd3d57 346 dma-names = "tx", "rx";
5fc0b42a
AC		 347 };
348
dde3b0d6 349 uart1: serial@48022000 {
4fcdff9b 350 compatible = "ti,am3352-uart", "ti,omap3-uart";
5fc0b42a
AC		 351 ti,hwmods = "uart2";
352 clock-frequency = <48000000>;
4462b31c 353 reg = <0x48022000 0x2000>;
4462b31c 354 interrupts = <73>;
53d91034 355 status = "disabled";
b5e50906 356 dmas = <&edma 28 0>, <&edma 29 0>;
13fd3d57 357 dma-names = "tx", "rx";
5fc0b42a
AC		 358 };
359
dde3b0d6 360 uart2: serial@48024000 {
4fcdff9b 361 compatible = "ti,am3352-uart", "ti,omap3-uart";
5fc0b42a
AC		 362 ti,hwmods = "uart3";
363 clock-frequency = <48000000>;
4462b31c 364 reg = <0x48024000 0x2000>;
4462b31c 365 interrupts = <74>;
53d91034 366 status = "disabled";
b5e50906 367 dmas = <&edma 30 0>, <&edma 31 0>;
13fd3d57 368 dma-names = "tx", "rx";
5fc0b42a
AC		 369 };
370
dde3b0d6 371 uart3: serial@481a6000 {
4fcdff9b 372 compatible = "ti,am3352-uart", "ti,omap3-uart";
5fc0b42a
AC		 373 ti,hwmods = "uart4";
374 clock-frequency = <48000000>;
4462b31c 375 reg = <0x481a6000 0x2000>;
4462b31c 376 interrupts = <44>;
53d91034 377 status = "disabled";
5fc0b42a
AC		 378 };
379
dde3b0d6 380 uart4: serial@481a8000 {
4fcdff9b 381 compatible = "ti,am3352-uart", "ti,omap3-uart";
5fc0b42a
AC		 382 ti,hwmods = "uart5";
383 clock-frequency = <48000000>;
4462b31c 384 reg = <0x481a8000 0x2000>;
4462b31c 385 interrupts = <45>;
53d91034 386 status = "disabled";
5fc0b42a
AC		 387 };
388
dde3b0d6 389 uart5: serial@481aa000 {
4fcdff9b 390 compatible = "ti,am3352-uart", "ti,omap3-uart";
5fc0b42a
AC		 391 ti,hwmods = "uart6";
392 clock-frequency = <48000000>;
4462b31c 393 reg = <0x481aa000 0x2000>;
4462b31c 394 interrupts = <46>;
53d91034 395 status = "disabled";
5fc0b42a
AC		 396 };
397
b918e2c0 398 i2c0: i2c@44e0b000 {
5fc0b42a
AC		 399 compatible = "ti,omap4-i2c";
400 #address-cells = <1>;
401 #size-cells = <0>;
402 ti,hwmods = "i2c1";
4462b31c 403 reg = <0x44e0b000 0x1000>;
4462b31c 404 interrupts = <70>;
53d91034 405 status = "disabled";
5fc0b42a
AC		 406 };
407
b918e2c0 408 i2c1: i2c@4802a000 {
5fc0b42a
AC		 409 compatible = "ti,omap4-i2c";
410 #address-cells = <1>;
411 #size-cells = <0>;
412 ti,hwmods = "i2c2";
4462b31c 413 reg = <0x4802a000 0x1000>;
4462b31c 414 interrupts = <71>;
53d91034 415 status = "disabled";
5fc0b42a
AC		 416 };
417
b918e2c0 418 i2c2: i2c@4819c000 {
5fc0b42a
AC		 419 compatible = "ti,omap4-i2c";
420 #address-cells = <1>;
421 #size-cells = <0>;
422 ti,hwmods = "i2c3";
4462b31c 423 reg = <0x4819c000 0x1000>;
4462b31c 424 interrupts = <30>;
53d91034 425 status = "disabled";
5fc0b42a 426 };
5f789ebc 427
55b4452b
MP		 428 mmc1: mmc@48060000 {
429 compatible = "ti,omap4-hsmmc";
430 ti,hwmods = "mmc1";
431 ti,dual-volt;
432 ti,needs-special-reset;
433 ti,needs-special-hs-handling;
b5e50906
PU		 434 dmas = <&edma_xbar 24 0 0
435 &edma_xbar 25 0 0>;
55b4452b
MP		 436 dma-names = "tx", "rx";
437 interrupts = <64>;
55b4452b
MP		 438 reg = <0x48060000 0x1000>;
439 status = "disabled";
440 };
441
442 mmc2: mmc@481d8000 {
443 compatible = "ti,omap4-hsmmc";
444 ti,hwmods = "mmc2";
445 ti,needs-special-reset;
b5e50906
PU		 446 dmas = <&edma 2 0
447 &edma 3 0>;
55b4452b
MP		 448 dma-names = "tx", "rx";
449 interrupts = <28>;
55b4452b
MP		 450 reg = <0x481d8000 0x1000>;
451 status = "disabled";
452 };
453
454 mmc3: mmc@47810000 {
455 compatible = "ti,omap4-hsmmc";
456 ti,hwmods = "mmc3";
457 ti,needs-special-reset;
458 interrupts = <29>;
55b4452b
MP		 459 reg = <0x47810000 0x1000>;
460 status = "disabled";
461 };
462
d4cbe80d
SA		 463 hwspinlock: spinlock@480ca000 {
464 compatible = "ti,omap4-hwspinlock";
465 reg = <0x480ca000 0x1000>;
466 ti,hwmods = "spinlock";
34054213 467 #hwlock-cells = <1>;
d4cbe80d
SA		 468 };
469
5f789ebc
AM		 470 wdt2: wdt@44e35000 {
471 compatible = "ti,omap3-wdt";
472 ti,hwmods = "wd_timer2";
4462b31c 473 reg = <0x44e35000 0x1000>;
4462b31c 474 interrupts = <91>;
5f789ebc 475 };
059b185d 476
e23aabc6
RQ		 477 dcan0: can@481cc000 {
478 compatible = "ti,am3352-d_can";
059b185d 479 ti,hwmods = "d_can0";
e23aabc6
RQ		 480 reg = <0x481cc000 0x2000>;
481 clocks = <&dcan0_fck>;
482 clock-names = "fck";
e3bc5358 483 syscon-raminit = <&scm_conf 0x644 0>;
059b185d 484 interrupts = <52>;
059b185d
AC		 485 status = "disabled";
486 };
487
e23aabc6
RQ		 488 dcan1: can@481d0000 {
489 compatible = "ti,am3352-d_can";
059b185d 490 ti,hwmods = "d_can1";
e23aabc6
RQ		 491 reg = <0x481d0000 0x2000>;
492 clocks = <&dcan1_fck>;
493 clock-names = "fck";
e3bc5358 494 syscon-raminit = <&scm_conf 0x644 1>;
059b185d 495 interrupts = <55>;
059b185d
AC		 496 status = "disabled";
497 };
fab8ad0b 498
40242301
SA		 499 mailbox: mailbox@480C8000 {
500 compatible = "ti,omap4-mailbox";
501 reg = <0x480C8000 0x200>;
502 interrupts = <77>;
503 ti,hwmods = "mailbox";
24df0453 504 #mbox-cells = <1>;
40242301
SA		 505 ti,mbox-num-users = <4>;
506 ti,mbox-num-fifos = <8>;
d27704d1 507 mbox_wkupm3: wkup_m3 {
2800971f 508 ti,mbox-send-noirq;
d27704d1
SA		 509 ti,mbox-tx = <0 0 0>;
510 ti,mbox-rx = <0 0 3>;
511 };
40242301
SA		 512 };
513
fab8ad0b 514 timer1: timer@44e31000 {
002e1ec5 515 compatible = "ti,am335x-timer-1ms";
fab8ad0b
JH		 516 reg = <0x44e31000 0x400>;
517 interrupts = <67>;
518 ti,hwmods = "timer1";
519 ti,timer-alwon;
520 };
521
522 timer2: timer@48040000 {
002e1ec5 523 compatible = "ti,am335x-timer";
fab8ad0b
JH		 524 reg = <0x48040000 0x400>;
525 interrupts = <68>;
526 ti,hwmods = "timer2";
527 };
528
529 timer3: timer@48042000 {
002e1ec5 530 compatible = "ti,am335x-timer";
fab8ad0b
JH		 531 reg = <0x48042000 0x400>;
532 interrupts = <69>;
533 ti,hwmods = "timer3";
534 };
535
536 timer4: timer@48044000 {
002e1ec5 537 compatible = "ti,am335x-timer";
fab8ad0b
JH		 538 reg = <0x48044000 0x400>;
539 interrupts = <92>;
540 ti,hwmods = "timer4";
541 ti,timer-pwm;
542 };
543
544 timer5: timer@48046000 {
002e1ec5 545 compatible = "ti,am335x-timer";
fab8ad0b
JH		 546 reg = <0x48046000 0x400>;
547 interrupts = <93>;
548 ti,hwmods = "timer5";
549 ti,timer-pwm;
550 };
551
552 timer6: timer@48048000 {
002e1ec5 553 compatible = "ti,am335x-timer";
fab8ad0b
JH		 554 reg = <0x48048000 0x400>;
555 interrupts = <94>;
556 ti,hwmods = "timer6";
557 ti,timer-pwm;
558 };
559
560 timer7: timer@4804a000 {
002e1ec5 561 compatible = "ti,am335x-timer";
fab8ad0b
JH		 562 reg = <0x4804a000 0x400>;
563 interrupts = <95>;
564 ti,hwmods = "timer7";
565 ti,timer-pwm;
566 };
0d935c16 567
ccd8b9e0 568 rtc: rtc@44e3e000 {
6ac7b4a2 569 compatible = "ti,am3352-rtc", "ti,da830-rtc";
0d935c16
AM		 570 reg = <0x44e3e000 0x1000>;
571 interrupts = <75
572 76>;
573 ti,hwmods = "rtc";
17fad5f3
K		 574 clocks = <&clkdiv32k_ick>;
575 clock-names = "int-clk";
0d935c16 576 };
9fd3c748
PA		 577
578 spi0: spi@48030000 {
579 compatible = "ti,omap4-mcspi";
580 #address-cells = <1>;
581 #size-cells = <0>;
582 reg = <0x48030000 0x400>;
7b3754c6 583 interrupts = <65>;
9fd3c748
PA		 584 ti,spi-num-cs = <2>;
585 ti,hwmods = "spi0";
b5e50906
PU		 586 dmas = <&edma 16 0
587 &edma 17 0
588 &edma 18 0
589 &edma 19 0>;
f5e2f807 590 dma-names = "tx0", "rx0", "tx1", "rx1";
9fd3c748
PA		 591 status = "disabled";
592 };
593
594 spi1: spi@481a0000 {
595 compatible = "ti,omap4-mcspi";
596 #address-cells = <1>;
597 #size-cells = <0>;
598 reg = <0x481a0000 0x400>;
7b3754c6 599 interrupts = <125>;
9fd3c748
PA		 600 ti,spi-num-cs = <2>;
601 ti,hwmods = "spi1";
b5e50906
PU		 602 dmas = <&edma 42 0
603 &edma 43 0
604 &edma 44 0
605 &edma 45 0>;
f5e2f807 606 dma-names = "tx0", "rx0", "tx1", "rx1";
9fd3c748
PA		 607 status = "disabled";
608 };
35b47fbb 609
97238b35
SAS		 610 usb: usb@47400000 {
611 compatible = "ti,am33xx-usb";
612 reg = <0x47400000 0x1000>;
613 ranges;
614 #address-cells = <1>;
615 #size-cells = <1>;
35b47fbb 616 ti,hwmods = "usb_otg_hs";
97238b35
SAS		 617 status = "disabled";
618
8abcdd68 619 usb_ctrl_mod: control@44e10620 {
97238b35
SAS		 620 compatible = "ti,am335x-usb-ctrl-module";
621 reg = <0x44e10620 0x10
622 0x44e10648 0x4>;
623 reg-names = "phy_ctrl", "wakeup";
624 status = "disabled";
625 };
626
c031a7d4 627 usb0_phy: usb-phy@47401300 {
97238b35
SAS		 628 compatible = "ti,am335x-usb-phy";
629 reg = <0x47401300 0x100>;
630 reg-names = "phy";
631 status = "disabled";
e7243b76 632 ti,ctrl_mod = <&usb_ctrl_mod>;
f0e11ff8 633 #phy-cells = <0>;
97238b35
SAS		 634 };
635
636 usb0: usb@47401000 {
637 compatible = "ti,musb-am33xx";
97238b35 638 status = "disabled";
c031a7d4
SAS		 639 reg = <0x47401400 0x400
640 0x47401000 0x200>;
641 reg-names = "mc", "control";
642
643 interrupts = <18>;
644 interrupt-names = "mc";
645 dr_mode = "otg";
646 mentor,multipoint = <1>;
647 mentor,num-eps = <16>;
648 mentor,ram-bits = <12>;
649 mentor,power = <500>;
650 phys = <&usb0_phy>;
9b3452d1
SAS		 651
652 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
653 &cppi41dma 2 0 &cppi41dma 3 0
654 &cppi41dma 4 0 &cppi41dma 5 0
655 &cppi41dma 6 0 &cppi41dma 7 0
656 &cppi41dma 8 0 &cppi41dma 9 0
657 &cppi41dma 10 0 &cppi41dma 11 0
658 &cppi41dma 12 0 &cppi41dma 13 0
659 &cppi41dma 14 0 &cppi41dma 0 1
660 &cppi41dma 1 1 &cppi41dma 2 1
661 &cppi41dma 3 1 &cppi41dma 4 1
662 &cppi41dma 5 1 &cppi41dma 6 1
663 &cppi41dma 7 1 &cppi41dma 8 1
664 &cppi41dma 9 1 &cppi41dma 10 1
665 &cppi41dma 11 1 &cppi41dma 12 1
666 &cppi41dma 13 1 &cppi41dma 14 1>;
667 dma-names =
668 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
669 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
670 "rx14", "rx15",
671 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
672 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
673 "tx14", "tx15";
97238b35
SAS		 674 };
675
c031a7d4 676 usb1_phy: usb-phy@47401b00 {
97238b35
SAS		 677 compatible = "ti,am335x-usb-phy";
678 reg = <0x47401b00 0x100>;
679 reg-names = "phy";
680 status = "disabled";
e7243b76 681 ti,ctrl_mod = <&usb_ctrl_mod>;
f0e11ff8 682 #phy-cells = <0>;
97238b35
SAS		 683 };
684
685 usb1: usb@47401800 {
686 compatible = "ti,musb-am33xx";
97238b35 687 status = "disabled";
c031a7d4
SAS		 688 reg = <0x47401c00 0x400
689 0x47401800 0x200>;
690 reg-names = "mc", "control";
691 interrupts = <19>;
692 interrupt-names = "mc";
693 dr_mode = "otg";
694 mentor,multipoint = <1>;
695 mentor,num-eps = <16>;
696 mentor,ram-bits = <12>;
697 mentor,power = <500>;
698 phys = <&usb1_phy>;
9b3452d1
SAS		 699
700 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
701 &cppi41dma 17 0 &cppi41dma 18 0
702 &cppi41dma 19 0 &cppi41dma 20 0
703 &cppi41dma 21 0 &cppi41dma 22 0
704 &cppi41dma 23 0 &cppi41dma 24 0
705 &cppi41dma 25 0 &cppi41dma 26 0
706 &cppi41dma 27 0 &cppi41dma 28 0
707 &cppi41dma 29 0 &cppi41dma 15 1
708 &cppi41dma 16 1 &cppi41dma 17 1
709 &cppi41dma 18 1 &cppi41dma 19 1
710 &cppi41dma 20 1 &cppi41dma 21 1
711 &cppi41dma 22 1 &cppi41dma 23 1
712 &cppi41dma 24 1 &cppi41dma 25 1
713 &cppi41dma 26 1 &cppi41dma 27 1
714 &cppi41dma 28 1 &cppi41dma 29 1>;
715 dma-names =
716 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
717 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
718 "rx14", "rx15",
719 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
720 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
721 "tx14", "tx15";
97238b35 722 };
9b3452d1 723
8abcdd68 724 cppi41dma: dma-controller@47402000 {
9b3452d1
SAS		 725 compatible = "ti,am3359-cppi41";
726 reg = <0x47400000 0x1000
727 0x47402000 0x1000
728 0x47403000 0x1000
729 0x47404000 0x4000>;
3b6394b4 730 reg-names = "glue", "controller", "scheduler", "queuemgr";
9b3452d1
SAS		 731 interrupts = <17>;
732 interrupt-names = "glue";
733 #dma-cells = <2>;
734 #dma-channels = <30>;
735 #dma-requests = <256>;
736 status = "disabled";
737 };
35b47fbb 738 };
6be35c70 739
0a7486c9
PA		 740 epwmss0: epwmss@48300000 {
741 compatible = "ti,am33xx-pwmss";
742 reg = <0x48300000 0x10>;
743 ti,hwmods = "epwmss0";
744 #address-cells = <1>;
745 #size-cells = <1>;
746 status = "disabled";
747 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
748 0x48300180 0x48300180 0x80 /* EQEP */
749 0x48300200 0x48300200 0x80>; /* EHRPWM */
750
751 ecap0: ecap@48300100 {
229110c1
FCJ		 752 compatible = "ti,am3352-ecap",
753 "ti,am33xx-ecap";
0a7486c9
PA		 754 #pwm-cells = <3>;
755 reg = <0x48300100 0x80>;
229110c1
FCJ		 756 clocks = <&l4ls_gclk>;
757 clock-names = "fck";
e8c85a3e
MP		 758 interrupts = <31>;
759 interrupt-names = "ecap0";
0a7486c9
PA		 760 status = "disabled";
761 };
762
dce2a652 763 ehrpwm0: pwm@48300200 {
229110c1
FCJ		 764 compatible = "ti,am3352-ehrpwm",
765 "ti,am33xx-ehrpwm";
0a7486c9
PA		 766 #pwm-cells = <3>;
767 reg = <0x48300200 0x80>;
229110c1
FCJ		 768 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
769 clock-names = "tbclk", "fck";
0a7486c9
PA		 770 status = "disabled";
771 };
772 };
773
774 epwmss1: epwmss@48302000 {
775 compatible = "ti,am33xx-pwmss";
776 reg = <0x48302000 0x10>;
777 ti,hwmods = "epwmss1";
778 #address-cells = <1>;
779 #size-cells = <1>;
780 status = "disabled";
781 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
782 0x48302180 0x48302180 0x80 /* EQEP */
783 0x48302200 0x48302200 0x80>; /* EHRPWM */
784
785 ecap1: ecap@48302100 {
229110c1
FCJ		 786 compatible = "ti,am3352-ecap",
787 "ti,am33xx-ecap";
0a7486c9
PA		 788 #pwm-cells = <3>;
789 reg = <0x48302100 0x80>;
229110c1
FCJ		 790 clocks = <&l4ls_gclk>;
791 clock-names = "fck";
e8c85a3e
MP		 792 interrupts = <47>;
793 interrupt-names = "ecap1";
0a7486c9
PA		 794 status = "disabled";
795 };
796
dce2a652 797 ehrpwm1: pwm@48302200 {
229110c1
FCJ		 798 compatible = "ti,am3352-ehrpwm",
799 "ti,am33xx-ehrpwm";
0a7486c9
PA		 800 #pwm-cells = <3>;
801 reg = <0x48302200 0x80>;
229110c1
FCJ		 802 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
803 clock-names = "tbclk", "fck";
0a7486c9
PA		 804 status = "disabled";
805 };
806 };
807
808 epwmss2: epwmss@48304000 {
809 compatible = "ti,am33xx-pwmss";
810 reg = <0x48304000 0x10>;
811 ti,hwmods = "epwmss2";
812 #address-cells = <1>;
813 #size-cells = <1>;
814 status = "disabled";
815 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
816 0x48304180 0x48304180 0x80 /* EQEP */
817 0x48304200 0x48304200 0x80>; /* EHRPWM */
818
819 ecap2: ecap@48304100 {
229110c1
FCJ		 820 compatible = "ti,am3352-ecap",
821 "ti,am33xx-ecap";
0a7486c9
PA		 822 #pwm-cells = <3>;
823 reg = <0x48304100 0x80>;
229110c1
FCJ		 824 clocks = <&l4ls_gclk>;
825 clock-names = "fck";
e8c85a3e
MP		 826 interrupts = <61>;
827 interrupt-names = "ecap2";
0a7486c9
PA		 828 status = "disabled";
829 };
830
dce2a652 831 ehrpwm2: pwm@48304200 {
229110c1
FCJ		 832 compatible = "ti,am3352-ehrpwm",
833 "ti,am33xx-ehrpwm";
0a7486c9
PA		 834 #pwm-cells = <3>;
835 reg = <0x48304200 0x80>;
229110c1
FCJ		 836 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
837 clock-names = "tbclk", "fck";
0a7486c9
PA		 838 status = "disabled";
839 };
840 };
841
1a39a65c 842 mac: ethernet@4a100000 {
21696f71 843 compatible = "ti,am335x-cpsw","ti,cpsw";
1a39a65c 844 ti,hwmods = "cpgmac0";
0987a6ef
GC		 845 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
846 clock-names = "fck", "cpts";
1a39a65c
M		 847 cpdma_channels = <8>;
848 ale_entries = <1024>;
849 bd_ram_size = <0x2000>;
1a39a65c
M		 850 mac_control = <0x20>;
851 slaves = <2>;
e86ac13b 852 active_slave = <0>;
1a39a65c
M		 853 cpts_clock_mult = <0x80000000>;
854 cpts_clock_shift = <29>;
855 reg = <0x4a100000 0x800
856 0x4a101200 0x100>;
857 #address-cells = <1>;
858 #size-cells = <1>;
1a39a65c
M		 859 /*
860 * c0_rx_thresh_pend
861 * c0_rx_pend
862 * c0_tx_pend
863 * c0_misc_pend
864 */
865 interrupts = <40 41 42 43>;
866 ranges;
e3bc5358 867 syscon = <&scm_conf>;
16c75a13 868 status = "disabled";
1a39a65c
M		 869
870 davinci_mdio: mdio@4a101000 {
9efd1a6f 871 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1a39a65c
M		 872 #address-cells = <1>;
873 #size-cells = <0>;
874 ti,hwmods = "davinci_mdio";
875 bus_freq = <1000000>;
876 reg = <0x4a101000 0x100>;
16c75a13 877 status = "disabled";
1a39a65c
M		 878 };
879
880 cpsw_emac0: slave@4a100200 {
881 /* Filled in by U-Boot */
882 mac-address = [ 00 00 00 00 00 00 ];
883 };
884
885 cpsw_emac1: slave@4a100300 {
886 /* Filled in by U-Boot */
887 mac-address = [ 00 00 00 00 00 00 ];
888 };
39ffbd91
M		 889
890 phy_sel: cpsw-phy-sel@44e10650 {
891 compatible = "ti,am3352-cpsw-phy-sel";
892 reg= <0x44e10650 0x4>;
893 reg-names = "gmii-sel";
894 };
1a39a65c 895 };
f6575c90
VB		 896
897 ocmcram: ocmcram@40300000 {
8b9a2810
RN		 898 compatible = "mmio-sram";
899 reg = <0x40300000 0x10000>; /* 64k */
f6575c90
VB		 900 };
901
15e8246b
PA		 902 elm: elm@48080000 {
903 compatible = "ti,am3352-elm";
904 reg = <0x48080000 0x2000>;
905 interrupts = <4>;
906 ti,hwmods = "elm";
d6cfc1e2
BP		 907 status = "disabled";
908 };
909
910 lcdc: lcdc@4830e000 {
911 compatible = "ti,am33xx-tilcdc";
912 reg = <0x4830e000 0x1000>;
d6cfc1e2
BP		 913 interrupts = <36>;
914 ti,hwmods = "lcdc";
15e8246b
PA		 915 status = "disabled";
916 };
917
a82279dd
PR		 918 tscadc: tscadc@44e0d000 {
919 compatible = "ti,am3359-tscadc";
920 reg = <0x44e0d000 0x1000>;
a82279dd
PR		 921 interrupts = <16>;
922 ti,hwmods = "adc_tsc";
923 status = "disabled";
55e871fc
M		 924 dmas = <&edma 53 0>, <&edma 57 0>;
925 dma-names = "fifo0", "fifo1";
a82279dd
PR		 926
927 tsc {
928 compatible = "ti,am3359-tsc";
929 };
930 am335x_adc: adc {
931 #io-channel-cells = <1>;
932 compatible = "ti,am3359-adc";
933 };
a82279dd
PR		 934 };
935
cd57dc5a
TL		 936 emif: emif@4c000000 {
937 compatible = "ti,emif-am3352";
938 reg = <0x4c000000 0x1000000>;
939 ti,hwmods = "emif";
940 };
941
e45879ec
PA		 942 gpmc: gpmc@50000000 {
943 compatible = "ti,am3352-gpmc";
944 ti,hwmods = "gpmc";
f12ecbe2 945 ti,no-idle-on-init;
e45879ec
PA		 946 reg = <0x50000000 0x2000>;
947 interrupts = <100>;
a2abf904 948 dmas = <&edma 52 0>;
201c7e33 949 dma-names = "rxtx";
00dddcaa
LP		 950 gpmc,num-cs = <7>;
951 gpmc,num-waitpins = <2>;
e45879ec
PA		 952 #address-cells = <2>;
953 #size-cells = <1>;
03752148
RQ		 954 interrupt-controller;
955 #interrupt-cells = <2>;
4eb4dd57
RQ		 956 gpio-controller;
957 #gpio-cells = <2>;
e45879ec
PA		 958 status = "disabled";
959 };
f8302e1e
MG		 960
961 sham: sham@53100000 {
962 compatible = "ti,omap4-sham";
963 ti,hwmods = "sham";
964 reg = <0x53100000 0x200>;
965 interrupts = <109>;
b5e50906 966 dmas = <&edma 36 0>;
f8302e1e
MG		 967 dma-names = "rx";
968 };
99919e5e
MG		 969
970 aes: aes@53500000 {
971 compatible = "ti,omap4-aes";
972 ti,hwmods = "aes";
973 reg = <0x53500000 0xa0>;
7af8884a 974 interrupts = <103>;
b5e50906
PU		 975 dmas = <&edma 6 0>,
976 <&edma 5 0>;
99919e5e
MG		 977 dma-names = "tx", "rx";
978 };
3f72f875
PA		 979
980 mcasp0: mcasp@48038000 {
981 compatible = "ti,am33xx-mcasp-audio";
982 ti,hwmods = "mcasp0";
0bee55ab
JS		 983 reg = <0x48038000 0x2000>,
984 <0x46000000 0x400000>;
985 reg-names = "mpu", "dat";
3f72f875 986 interrupts = <80>, <81>;
ae107d06 987 interrupt-names = "tx", "rx";
3f72f875 988 status = "disabled";
b5e50906
PU		 989 dmas = <&edma 8 2>,
990 <&edma 9 2>;
3f72f875
PA		 991 dma-names = "tx", "rx";
992 };
993
994 mcasp1: mcasp@4803C000 {
995 compatible = "ti,am33xx-mcasp-audio";
996 ti,hwmods = "mcasp1";
0bee55ab
JS		 997 reg = <0x4803C000 0x2000>,
998 <0x46400000 0x400000>;
999 reg-names = "mpu", "dat";
3f72f875 1000 interrupts = <82>, <83>;
ae107d06 1001 interrupt-names = "tx", "rx";
3f72f875 1002 status = "disabled";
b5e50906
PU		 1003 dmas = <&edma 10 2>,
1004 <&edma 11 2>;
3f72f875
PA		 1005 dma-names = "tx", "rx";
1006 };
ed845d6b
LV		 1007
1008 rng: rng@48310000 {
1009 compatible = "ti,omap4-rng";
1010 ti,hwmods = "rng";
1011 reg = <0x48310000 0x2000>;
1012 interrupts = <111>;
1013 };
5fc0b42a
AC		 1014 };
1015};
ea291c98
TK		 1016
1017/include/ "am33xx-clocks.dtsi"
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