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6cfd8117 AM |
1 | /* |
2 | * Device Tree Source for AM4372 SoC | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
d2885dbb | 11 | #include <dt-bindings/gpio/gpio.h> |
6cfd8117 AM |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
13 | ||
14 | #include "skeleton.dtsi" | |
15 | ||
16 | / { | |
17 | compatible = "ti,am4372", "ti,am43"; | |
18 | interrupt-parent = <&gic>; | |
19 | ||
20 | ||
21 | aliases { | |
6a968678 NM |
22 | i2c0 = &i2c0; |
23 | i2c1 = &i2c1; | |
24 | i2c2 = &i2c2; | |
6cfd8117 | 25 | serial0 = &uart0; |
9e3269b8 LV |
26 | ethernet0 = &cpsw_emac0; |
27 | ethernet1 = &cpsw_emac1; | |
6cfd8117 AM |
28 | }; |
29 | ||
30 | cpus { | |
738c7409 AM |
31 | #address-cells = <1>; |
32 | #size-cells = <0>; | |
6cfd8117 AM |
33 | cpu@0 { |
34 | compatible = "arm,cortex-a9"; | |
738c7409 AM |
35 | device_type = "cpu"; |
36 | reg = <0>; | |
8d766fa2 NM |
37 | |
38 | clocks = <&dpll_mpu_ck>; | |
39 | clock-names = "cpu"; | |
40 | ||
41 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
6cfd8117 AM |
42 | }; |
43 | }; | |
44 | ||
45 | gic: interrupt-controller@48241000 { | |
46 | compatible = "arm,cortex-a9-gic"; | |
47 | interrupt-controller; | |
48 | #interrupt-cells = <3>; | |
49 | reg = <0x48241000 0x1000>, | |
50 | <0x48240100 0x0100>; | |
51 | }; | |
52 | ||
9e3269b8 LV |
53 | l2-cache-controller@48242000 { |
54 | compatible = "arm,pl310-cache"; | |
55 | reg = <0x48242000 0x1000>; | |
56 | cache-unified; | |
57 | cache-level = <2>; | |
58 | }; | |
59 | ||
60 | am43xx_pinmux: pinmux@44e10800 { | |
61 | compatible = "pinctrl-single"; | |
62 | reg = <0x44e10800 0x31c>; | |
63 | #address-cells = <1>; | |
64 | #size-cells = <0>; | |
65 | pinctrl-single,register-width = <32>; | |
66 | pinctrl-single,function-mask = <0xffffffff>; | |
67 | }; | |
68 | ||
6cfd8117 AM |
69 | ocp { |
70 | compatible = "simple-bus"; | |
71 | #address-cells = <1>; | |
72 | #size-cells = <1>; | |
73 | ranges; | |
9e3269b8 LV |
74 | ti,hwmods = "l3_main"; |
75 | ||
6a679208 TK |
76 | prcm: prcm@44df0000 { |
77 | compatible = "ti,am4-prcm"; | |
78 | reg = <0x44df0000 0x11000>; | |
79 | ||
80 | prcm_clocks: clocks { | |
81 | #address-cells = <1>; | |
82 | #size-cells = <0>; | |
83 | }; | |
84 | ||
85 | prcm_clockdomains: clockdomains { | |
86 | }; | |
87 | }; | |
88 | ||
89 | scrm: scrm@44e10000 { | |
90 | compatible = "ti,am4-scrm"; | |
91 | reg = <0x44e10000 0x2000>; | |
92 | ||
93 | scrm_clocks: clocks { | |
94 | #address-cells = <1>; | |
95 | #size-cells = <0>; | |
96 | }; | |
97 | ||
98 | scrm_clockdomains: clockdomains { | |
99 | }; | |
100 | }; | |
101 | ||
9e3269b8 LV |
102 | edma: edma@49000000 { |
103 | compatible = "ti,edma3"; | |
104 | ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; | |
105 | reg = <0x49000000 0x10000>, | |
106 | <0x44e10f90 0x10>; | |
107 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
108 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
109 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
110 | #dma-cells = <1>; | |
111 | dma-channels = <64>; | |
112 | ti,edma-regions = <4>; | |
113 | ti,edma-slots = <256>; | |
114 | }; | |
6cfd8117 AM |
115 | |
116 | uart0: serial@44e09000 { | |
117 | compatible = "ti,am4372-uart","ti,omap2-uart"; | |
118 | reg = <0x44e09000 0x2000>; | |
119 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
73456012 AM |
120 | ti,hwmods = "uart1"; |
121 | }; | |
122 | ||
123 | uart1: serial@48022000 { | |
124 | compatible = "ti,am4372-uart","ti,omap2-uart"; | |
125 | reg = <0x48022000 0x2000>; | |
126 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
127 | ti,hwmods = "uart2"; | |
128 | status = "disabled"; | |
129 | }; | |
130 | ||
131 | uart2: serial@48024000 { | |
132 | compatible = "ti,am4372-uart","ti,omap2-uart"; | |
133 | reg = <0x48024000 0x2000>; | |
134 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
135 | ti,hwmods = "uart3"; | |
136 | status = "disabled"; | |
137 | }; | |
138 | ||
139 | uart3: serial@481a6000 { | |
140 | compatible = "ti,am4372-uart","ti,omap2-uart"; | |
141 | reg = <0x481a6000 0x2000>; | |
142 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
143 | ti,hwmods = "uart4"; | |
144 | status = "disabled"; | |
145 | }; | |
146 | ||
147 | uart4: serial@481a8000 { | |
148 | compatible = "ti,am4372-uart","ti,omap2-uart"; | |
149 | reg = <0x481a8000 0x2000>; | |
150 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
151 | ti,hwmods = "uart5"; | |
152 | status = "disabled"; | |
153 | }; | |
154 | ||
155 | uart5: serial@481aa000 { | |
156 | compatible = "ti,am4372-uart","ti,omap2-uart"; | |
157 | reg = <0x481aa000 0x2000>; | |
158 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
159 | ti,hwmods = "uart6"; | |
160 | status = "disabled"; | |
6cfd8117 AM |
161 | }; |
162 | ||
9e3269b8 LV |
163 | mailbox: mailbox@480C8000 { |
164 | compatible = "ti,omap4-mailbox"; | |
165 | reg = <0x480C8000 0x200>; | |
166 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
167 | ti,hwmods = "mailbox"; | |
168 | ti,mbox-num-users = <4>; | |
169 | ti,mbox-num-fifos = <8>; | |
170 | ti,mbox-names = "wkup_m3"; | |
171 | ti,mbox-data = <0 0 0 0>; | |
172 | status = "disabled"; | |
173 | }; | |
174 | ||
6cfd8117 AM |
175 | timer1: timer@44e31000 { |
176 | compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; | |
177 | reg = <0x44e31000 0x400>; | |
178 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
179 | ti,timer-alwon; | |
73456012 | 180 | ti,hwmods = "timer1"; |
6cfd8117 AM |
181 | }; |
182 | ||
183 | timer2: timer@48040000 { | |
184 | compatible = "ti,am4372-timer","ti,am335x-timer"; | |
185 | reg = <0x48040000 0x400>; | |
186 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
73456012 AM |
187 | ti,hwmods = "timer2"; |
188 | }; | |
189 | ||
190 | timer3: timer@48042000 { | |
191 | compatible = "ti,am4372-timer","ti,am335x-timer"; | |
192 | reg = <0x48042000 0x400>; | |
193 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
194 | ti,hwmods = "timer3"; | |
195 | status = "disabled"; | |
196 | }; | |
197 | ||
198 | timer4: timer@48044000 { | |
199 | compatible = "ti,am4372-timer","ti,am335x-timer"; | |
200 | reg = <0x48044000 0x400>; | |
201 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; | |
202 | ti,timer-pwm; | |
203 | ti,hwmods = "timer4"; | |
204 | status = "disabled"; | |
205 | }; | |
206 | ||
207 | timer5: timer@48046000 { | |
208 | compatible = "ti,am4372-timer","ti,am335x-timer"; | |
209 | reg = <0x48046000 0x400>; | |
210 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | |
211 | ti,timer-pwm; | |
212 | ti,hwmods = "timer5"; | |
213 | status = "disabled"; | |
214 | }; | |
215 | ||
216 | timer6: timer@48048000 { | |
217 | compatible = "ti,am4372-timer","ti,am335x-timer"; | |
218 | reg = <0x48048000 0x400>; | |
219 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
220 | ti,timer-pwm; | |
221 | ti,hwmods = "timer6"; | |
222 | status = "disabled"; | |
223 | }; | |
224 | ||
225 | timer7: timer@4804a000 { | |
226 | compatible = "ti,am4372-timer","ti,am335x-timer"; | |
227 | reg = <0x4804a000 0x400>; | |
228 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
229 | ti,timer-pwm; | |
230 | ti,hwmods = "timer7"; | |
231 | status = "disabled"; | |
232 | }; | |
233 | ||
234 | timer8: timer@481c1000 { | |
235 | compatible = "ti,am4372-timer","ti,am335x-timer"; | |
236 | reg = <0x481c1000 0x400>; | |
237 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; | |
238 | ti,hwmods = "timer8"; | |
239 | status = "disabled"; | |
240 | }; | |
241 | ||
242 | timer9: timer@4833d000 { | |
243 | compatible = "ti,am4372-timer","ti,am335x-timer"; | |
244 | reg = <0x4833d000 0x400>; | |
245 | interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | |
246 | ti,hwmods = "timer9"; | |
247 | status = "disabled"; | |
248 | }; | |
249 | ||
250 | timer10: timer@4833f000 { | |
251 | compatible = "ti,am4372-timer","ti,am335x-timer"; | |
252 | reg = <0x4833f000 0x400>; | |
253 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; | |
254 | ti,hwmods = "timer10"; | |
255 | status = "disabled"; | |
256 | }; | |
257 | ||
258 | timer11: timer@48341000 { | |
259 | compatible = "ti,am4372-timer","ti,am335x-timer"; | |
260 | reg = <0x48341000 0x400>; | |
261 | interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
262 | ti,hwmods = "timer11"; | |
263 | status = "disabled"; | |
6cfd8117 AM |
264 | }; |
265 | ||
266 | counter32k: counter@44e86000 { | |
267 | compatible = "ti,am4372-counter32k","ti,omap-counter32k"; | |
268 | reg = <0x44e86000 0x40>; | |
73456012 AM |
269 | ti,hwmods = "counter_32k"; |
270 | }; | |
271 | ||
272 | rtc@44e3e000 { | |
273 | compatible = "ti,am4372-rtc","ti,da830-rtc"; | |
274 | reg = <0x44e3e000 0x1000>; | |
275 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH | |
276 | GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
277 | ti,hwmods = "rtc"; | |
278 | status = "disabled"; | |
279 | }; | |
280 | ||
281 | wdt@44e35000 { | |
282 | compatible = "ti,am4372-wdt","ti,omap3-wdt"; | |
283 | reg = <0x44e35000 0x1000>; | |
284 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
285 | ti,hwmods = "wd_timer2"; | |
73456012 AM |
286 | }; |
287 | ||
288 | gpio0: gpio@44e07000 { | |
289 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; | |
290 | reg = <0x44e07000 0x1000>; | |
291 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
292 | gpio-controller; | |
293 | #gpio-cells = <2>; | |
294 | interrupt-controller; | |
295 | #interrupt-cells = <2>; | |
296 | ti,hwmods = "gpio1"; | |
297 | status = "disabled"; | |
298 | }; | |
299 | ||
300 | gpio1: gpio@4804c000 { | |
301 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; | |
302 | reg = <0x4804c000 0x1000>; | |
303 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
304 | gpio-controller; | |
305 | #gpio-cells = <2>; | |
306 | interrupt-controller; | |
307 | #interrupt-cells = <2>; | |
308 | ti,hwmods = "gpio2"; | |
309 | status = "disabled"; | |
310 | }; | |
311 | ||
312 | gpio2: gpio@481ac000 { | |
313 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; | |
314 | reg = <0x481ac000 0x1000>; | |
315 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
316 | gpio-controller; | |
317 | #gpio-cells = <2>; | |
318 | interrupt-controller; | |
319 | #interrupt-cells = <2>; | |
320 | ti,hwmods = "gpio3"; | |
321 | status = "disabled"; | |
322 | }; | |
323 | ||
324 | gpio3: gpio@481ae000 { | |
325 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; | |
326 | reg = <0x481ae000 0x1000>; | |
327 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
328 | gpio-controller; | |
329 | #gpio-cells = <2>; | |
330 | interrupt-controller; | |
331 | #interrupt-cells = <2>; | |
332 | ti,hwmods = "gpio4"; | |
333 | status = "disabled"; | |
334 | }; | |
335 | ||
336 | gpio4: gpio@48320000 { | |
337 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; | |
338 | reg = <0x48320000 0x1000>; | |
339 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; | |
340 | gpio-controller; | |
341 | #gpio-cells = <2>; | |
342 | interrupt-controller; | |
343 | #interrupt-cells = <2>; | |
344 | ti,hwmods = "gpio5"; | |
345 | status = "disabled"; | |
346 | }; | |
347 | ||
348 | gpio5: gpio@48322000 { | |
349 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; | |
350 | reg = <0x48322000 0x1000>; | |
351 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
352 | gpio-controller; | |
353 | #gpio-cells = <2>; | |
354 | interrupt-controller; | |
355 | #interrupt-cells = <2>; | |
356 | ti,hwmods = "gpio6"; | |
357 | status = "disabled"; | |
358 | }; | |
359 | ||
fd4a8a68 SA |
360 | hwspinlock: spinlock@480ca000 { |
361 | compatible = "ti,omap4-hwspinlock"; | |
362 | reg = <0x480ca000 0x1000>; | |
363 | ti,hwmods = "spinlock"; | |
364 | #hwlock-cells = <1>; | |
365 | }; | |
366 | ||
73456012 AM |
367 | i2c0: i2c@44e0b000 { |
368 | compatible = "ti,am4372-i2c","ti,omap4-i2c"; | |
369 | reg = <0x44e0b000 0x1000>; | |
370 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | |
371 | ti,hwmods = "i2c1"; | |
372 | #address-cells = <1>; | |
373 | #size-cells = <0>; | |
374 | status = "disabled"; | |
375 | }; | |
376 | ||
377 | i2c1: i2c@4802a000 { | |
378 | compatible = "ti,am4372-i2c","ti,omap4-i2c"; | |
379 | reg = <0x4802a000 0x1000>; | |
380 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
381 | ti,hwmods = "i2c2"; | |
382 | #address-cells = <1>; | |
383 | #size-cells = <0>; | |
384 | status = "disabled"; | |
385 | }; | |
386 | ||
387 | i2c2: i2c@4819c000 { | |
388 | compatible = "ti,am4372-i2c","ti,omap4-i2c"; | |
389 | reg = <0x4819c000 0x1000>; | |
390 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
391 | ti,hwmods = "i2c3"; | |
392 | #address-cells = <1>; | |
393 | #size-cells = <0>; | |
394 | status = "disabled"; | |
395 | }; | |
396 | ||
397 | spi0: spi@48030000 { | |
398 | compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; | |
399 | reg = <0x48030000 0x400>; | |
400 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
401 | ti,hwmods = "spi0"; | |
402 | #address-cells = <1>; | |
403 | #size-cells = <0>; | |
404 | status = "disabled"; | |
405 | }; | |
406 | ||
9e3269b8 LV |
407 | mmc1: mmc@48060000 { |
408 | compatible = "ti,omap4-hsmmc"; | |
409 | reg = <0x48060000 0x1000>; | |
410 | ti,hwmods = "mmc1"; | |
411 | ti,dual-volt; | |
412 | ti,needs-special-reset; | |
413 | dmas = <&edma 24 | |
414 | &edma 25>; | |
415 | dma-names = "tx", "rx"; | |
416 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | |
417 | status = "disabled"; | |
418 | }; | |
419 | ||
420 | mmc2: mmc@481d8000 { | |
421 | compatible = "ti,omap4-hsmmc"; | |
422 | reg = <0x481d8000 0x1000>; | |
423 | ti,hwmods = "mmc2"; | |
424 | ti,needs-special-reset; | |
425 | dmas = <&edma 2 | |
426 | &edma 3>; | |
427 | dma-names = "tx", "rx"; | |
428 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
429 | status = "disabled"; | |
430 | }; | |
431 | ||
432 | mmc3: mmc@47810000 { | |
433 | compatible = "ti,omap4-hsmmc"; | |
434 | reg = <0x47810000 0x1000>; | |
435 | ti,hwmods = "mmc3"; | |
436 | ti,needs-special-reset; | |
437 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
438 | status = "disabled"; | |
439 | }; | |
440 | ||
73456012 AM |
441 | spi1: spi@481a0000 { |
442 | compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; | |
443 | reg = <0x481a0000 0x400>; | |
444 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
445 | ti,hwmods = "spi1"; | |
446 | #address-cells = <1>; | |
447 | #size-cells = <0>; | |
448 | status = "disabled"; | |
449 | }; | |
450 | ||
451 | spi2: spi@481a2000 { | |
452 | compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; | |
453 | reg = <0x481a2000 0x400>; | |
454 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; | |
455 | ti,hwmods = "spi2"; | |
456 | #address-cells = <1>; | |
457 | #size-cells = <0>; | |
458 | status = "disabled"; | |
459 | }; | |
460 | ||
461 | spi3: spi@481a4000 { | |
462 | compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; | |
463 | reg = <0x481a4000 0x400>; | |
464 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; | |
465 | ti,hwmods = "spi3"; | |
466 | #address-cells = <1>; | |
467 | #size-cells = <0>; | |
468 | status = "disabled"; | |
469 | }; | |
470 | ||
471 | spi4: spi@48345000 { | |
472 | compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; | |
473 | reg = <0x48345000 0x400>; | |
474 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; | |
475 | ti,hwmods = "spi4"; | |
476 | #address-cells = <1>; | |
477 | #size-cells = <0>; | |
478 | status = "disabled"; | |
479 | }; | |
480 | ||
481 | mac: ethernet@4a100000 { | |
482 | compatible = "ti,am4372-cpsw","ti,cpsw"; | |
483 | reg = <0x4a100000 0x800 | |
484 | 0x4a101200 0x100>; | |
485 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH | |
486 | GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH | |
487 | GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH | |
488 | GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
9e3269b8 LV |
489 | #address-cells = <1>; |
490 | #size-cells = <1>; | |
73456012 AM |
491 | ti,hwmods = "cpgmac0"; |
492 | status = "disabled"; | |
9e3269b8 LV |
493 | cpdma_channels = <8>; |
494 | ale_entries = <1024>; | |
495 | bd_ram_size = <0x2000>; | |
496 | no_bd_ram = <0>; | |
497 | rx_descs = <64>; | |
498 | mac_control = <0x20>; | |
499 | slaves = <2>; | |
500 | active_slave = <0>; | |
501 | cpts_clock_mult = <0x80000000>; | |
502 | cpts_clock_shift = <29>; | |
503 | ranges; | |
504 | ||
505 | davinci_mdio: mdio@4a101000 { | |
506 | compatible = "ti,am4372-mdio","ti,davinci_mdio"; | |
507 | reg = <0x4a101000 0x100>; | |
508 | #address-cells = <1>; | |
509 | #size-cells = <0>; | |
510 | ti,hwmods = "davinci_mdio"; | |
511 | bus_freq = <1000000>; | |
512 | status = "disabled"; | |
513 | }; | |
514 | ||
515 | cpsw_emac0: slave@4a100200 { | |
516 | /* Filled in by U-Boot */ | |
517 | mac-address = [ 00 00 00 00 00 00 ]; | |
518 | }; | |
519 | ||
520 | cpsw_emac1: slave@4a100300 { | |
521 | /* Filled in by U-Boot */ | |
522 | mac-address = [ 00 00 00 00 00 00 ]; | |
523 | }; | |
73456012 AM |
524 | }; |
525 | ||
526 | epwmss0: epwmss@48300000 { | |
527 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; | |
528 | reg = <0x48300000 0x10>; | |
9e3269b8 LV |
529 | #address-cells = <1>; |
530 | #size-cells = <1>; | |
531 | ranges; | |
73456012 AM |
532 | ti,hwmods = "epwmss0"; |
533 | status = "disabled"; | |
9e3269b8 LV |
534 | |
535 | ecap0: ecap@48300100 { | |
536 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; | |
aa842305 | 537 | #pwm-cells = <3>; |
9e3269b8 LV |
538 | reg = <0x48300100 0x80>; |
539 | ti,hwmods = "ecap0"; | |
540 | status = "disabled"; | |
541 | }; | |
542 | ||
543 | ehrpwm0: ehrpwm@48300200 { | |
544 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | |
aa842305 | 545 | #pwm-cells = <3>; |
9e3269b8 LV |
546 | reg = <0x48300200 0x80>; |
547 | ti,hwmods = "ehrpwm0"; | |
548 | status = "disabled"; | |
549 | }; | |
73456012 AM |
550 | }; |
551 | ||
552 | epwmss1: epwmss@48302000 { | |
553 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; | |
554 | reg = <0x48302000 0x10>; | |
9e3269b8 LV |
555 | #address-cells = <1>; |
556 | #size-cells = <1>; | |
557 | ranges; | |
73456012 AM |
558 | ti,hwmods = "epwmss1"; |
559 | status = "disabled"; | |
9e3269b8 LV |
560 | |
561 | ecap1: ecap@48302100 { | |
562 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; | |
aa842305 | 563 | #pwm-cells = <3>; |
9e3269b8 LV |
564 | reg = <0x48302100 0x80>; |
565 | ti,hwmods = "ecap1"; | |
566 | status = "disabled"; | |
567 | }; | |
568 | ||
569 | ehrpwm1: ehrpwm@48302200 { | |
570 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | |
aa842305 | 571 | #pwm-cells = <3>; |
9e3269b8 LV |
572 | reg = <0x48302200 0x80>; |
573 | ti,hwmods = "ehrpwm1"; | |
574 | status = "disabled"; | |
575 | }; | |
73456012 AM |
576 | }; |
577 | ||
578 | epwmss2: epwmss@48304000 { | |
579 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; | |
580 | reg = <0x48304000 0x10>; | |
9e3269b8 LV |
581 | #address-cells = <1>; |
582 | #size-cells = <1>; | |
583 | ranges; | |
73456012 AM |
584 | ti,hwmods = "epwmss2"; |
585 | status = "disabled"; | |
9e3269b8 LV |
586 | |
587 | ecap2: ecap@48304100 { | |
588 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; | |
aa842305 | 589 | #pwm-cells = <3>; |
9e3269b8 LV |
590 | reg = <0x48304100 0x80>; |
591 | ti,hwmods = "ecap2"; | |
592 | status = "disabled"; | |
593 | }; | |
594 | ||
595 | ehrpwm2: ehrpwm@48304200 { | |
596 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | |
aa842305 | 597 | #pwm-cells = <3>; |
9e3269b8 LV |
598 | reg = <0x48304200 0x80>; |
599 | ti,hwmods = "ehrpwm2"; | |
600 | status = "disabled"; | |
601 | }; | |
73456012 AM |
602 | }; |
603 | ||
604 | epwmss3: epwmss@48306000 { | |
605 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; | |
606 | reg = <0x48306000 0x10>; | |
9e3269b8 LV |
607 | #address-cells = <1>; |
608 | #size-cells = <1>; | |
609 | ranges; | |
73456012 AM |
610 | ti,hwmods = "epwmss3"; |
611 | status = "disabled"; | |
9e3269b8 LV |
612 | |
613 | ehrpwm3: ehrpwm@48306200 { | |
614 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | |
aa842305 | 615 | #pwm-cells = <3>; |
9e3269b8 LV |
616 | reg = <0x48306200 0x80>; |
617 | ti,hwmods = "ehrpwm3"; | |
618 | status = "disabled"; | |
619 | }; | |
73456012 AM |
620 | }; |
621 | ||
622 | epwmss4: epwmss@48308000 { | |
623 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; | |
624 | reg = <0x48308000 0x10>; | |
9e3269b8 LV |
625 | #address-cells = <1>; |
626 | #size-cells = <1>; | |
627 | ranges; | |
73456012 AM |
628 | ti,hwmods = "epwmss4"; |
629 | status = "disabled"; | |
9e3269b8 LV |
630 | |
631 | ehrpwm4: ehrpwm@48308200 { | |
632 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | |
aa842305 | 633 | #pwm-cells = <3>; |
9e3269b8 LV |
634 | reg = <0x48308200 0x80>; |
635 | ti,hwmods = "ehrpwm4"; | |
636 | status = "disabled"; | |
637 | }; | |
73456012 AM |
638 | }; |
639 | ||
640 | epwmss5: epwmss@4830a000 { | |
641 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; | |
642 | reg = <0x4830a000 0x10>; | |
9e3269b8 LV |
643 | #address-cells = <1>; |
644 | #size-cells = <1>; | |
645 | ranges; | |
73456012 AM |
646 | ti,hwmods = "epwmss5"; |
647 | status = "disabled"; | |
9e3269b8 LV |
648 | |
649 | ehrpwm5: ehrpwm@4830a200 { | |
650 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; | |
aa842305 | 651 | #pwm-cells = <3>; |
9e3269b8 LV |
652 | reg = <0x4830a200 0x80>; |
653 | ti,hwmods = "ehrpwm5"; | |
654 | status = "disabled"; | |
655 | }; | |
656 | }; | |
657 | ||
658 | sham: sham@53100000 { | |
659 | compatible = "ti,omap5-sham"; | |
660 | ti,hwmods = "sham"; | |
661 | reg = <0x53100000 0x300>; | |
662 | dmas = <&edma 36>; | |
663 | dma-names = "rx"; | |
664 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
6cfd8117 | 665 | }; |
6e70a510 JF |
666 | |
667 | aes: aes@53501000 { | |
668 | compatible = "ti,omap4-aes"; | |
669 | ti,hwmods = "aes"; | |
670 | reg = <0x53501000 0xa0>; | |
671 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
9e3269b8 LV |
672 | dmas = <&edma 6 |
673 | &edma 5>; | |
674 | dma-names = "tx", "rx"; | |
6e70a510 | 675 | }; |
099f3a85 JF |
676 | |
677 | des: des@53701000 { | |
678 | compatible = "ti,omap4-des"; | |
679 | ti,hwmods = "des"; | |
680 | reg = <0x53701000 0xa0>; | |
681 | interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; | |
9e3269b8 LV |
682 | dmas = <&edma 34 |
683 | &edma 33>; | |
684 | dma-names = "tx", "rx"; | |
099f3a85 | 685 | }; |
9e3269b8 | 686 | |
b9c95bf4 PU |
687 | mcasp0: mcasp@48038000 { |
688 | compatible = "ti,am33xx-mcasp-audio"; | |
689 | ti,hwmods = "mcasp0"; | |
690 | reg = <0x48038000 0x2000>, | |
691 | <0x46000000 0x400000>; | |
692 | reg-names = "mpu", "dat"; | |
693 | interrupts = <80>, <81>; | |
ae107d06 | 694 | interrupt-names = "tx", "rx"; |
b9c95bf4 PU |
695 | status = "disabled"; |
696 | dmas = <&edma 8>, | |
697 | <&edma 9>; | |
698 | dma-names = "tx", "rx"; | |
699 | }; | |
700 | ||
701 | mcasp1: mcasp@4803C000 { | |
702 | compatible = "ti,am33xx-mcasp-audio"; | |
703 | ti,hwmods = "mcasp1"; | |
704 | reg = <0x4803C000 0x2000>, | |
705 | <0x46400000 0x400000>; | |
706 | reg-names = "mpu", "dat"; | |
707 | interrupts = <82>, <83>; | |
ae107d06 | 708 | interrupt-names = "tx", "rx"; |
b9c95bf4 PU |
709 | status = "disabled"; |
710 | dmas = <&edma 10>, | |
711 | <&edma 11>; | |
712 | dma-names = "tx", "rx"; | |
713 | }; | |
f68e355c PG |
714 | |
715 | elm: elm@48080000 { | |
716 | compatible = "ti,am3352-elm"; | |
717 | reg = <0x48080000 0x2000>; | |
718 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
719 | ti,hwmods = "elm"; | |
720 | clocks = <&l4ls_gclk>; | |
721 | clock-names = "fck"; | |
722 | status = "disabled"; | |
723 | }; | |
724 | ||
725 | gpmc: gpmc@50000000 { | |
726 | compatible = "ti,am3352-gpmc"; | |
727 | ti,hwmods = "gpmc"; | |
728 | clocks = <&l3s_gclk>; | |
729 | clock-names = "fck"; | |
730 | reg = <0x50000000 0x2000>; | |
731 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
732 | gpmc,num-cs = <7>; | |
733 | gpmc,num-waitpins = <2>; | |
734 | #address-cells = <2>; | |
735 | #size-cells = <1>; | |
736 | status = "disabled"; | |
737 | }; | |
6cfd8117 AM |
738 | }; |
739 | }; | |
6a679208 TK |
740 | |
741 | /include/ "am43xx-clocks.dtsi" |