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ARM: DTS: am33xx: Use the new DT bindings for the eDMA3
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / am4372.dtsi
CommitLineData
6cfd8117
AM		 1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
d2885dbb 11#include <dt-bindings/gpio/gpio.h>
6cfd8117
AM		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
7136d457 18 interrupt-parent = <&wakeupgen>;
6cfd8117
AM		 19
20
21 aliases {
6a968678
NM		 22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
6cfd8117 25 serial0 = &uart0;
71256d9d
SN		 26 serial1 = &uart1;
27 serial2 = &uart2;
28 serial3 = &uart3;
29 serial4 = &uart4;
30 serial5 = &uart5;
9e3269b8
LV		 31 ethernet0 = &cpsw_emac0;
32 ethernet1 = &cpsw_emac1;
e05edea4 33 spi0 = &qspi;
6cfd8117
AM		 34 };
35
36 cpus {
738c7409
AM		 37 #address-cells = <1>;
38 #size-cells = <0>;
08ecb28a 39 cpu: cpu@0 {
6cfd8117 40 compatible = "arm,cortex-a9";
738c7409
AM		 41 device_type = "cpu";
42 reg = <0>;
8d766fa2
NM		 43
44 clocks = <&dpll_mpu_ck>;
45 clock-names = "cpu";
46
47 clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117
AM		 48 };
49 };
50
51 gic: interrupt-controller@48241000 {
52 compatible = "arm,cortex-a9-gic";
53 interrupt-controller;
54 #interrupt-cells = <3>;
55 reg = <0x48241000 0x1000>,
56 <0x48240100 0x0100>;
7136d457
MZ		 57 interrupt-parent = <&gic>;
58 };
59
60 wakeupgen: interrupt-controller@48281000 {
61 compatible = "ti,omap4-wugen-mpu";
62 interrupt-controller;
63 #interrupt-cells = <3>;
64 reg = <0x48281000 0x1000>;
65 interrupt-parent = <&gic>;
6cfd8117
AM		 66 };
67
8cbd4c2f
FB		 68 scu: scu@48240000 {
69 compatible = "arm,cortex-a9-scu";
70 reg = <0x48240000 0x100>;
71 };
72
73 global_timer: timer@48240200 {
74 compatible = "arm,cortex-a9-global-timer";
75 reg = <0x48240200 0x100>;
76 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
77 interrupt-parent = <&gic>;
78 clocks = <&dpll_mpu_m2_ck>;
79 };
80
81 local_timer: timer@48240600 {
82 compatible = "arm,cortex-a9-twd-timer";
83 reg = <0x48240600 0x100>;
84 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
85 interrupt-parent = <&gic>;
86 clocks = <&dpll_mpu_m2_ck>;
87 };
88
9e3269b8
LV		 89 l2-cache-controller@48242000 {
90 compatible = "arm,pl310-cache";
91 reg = <0x48242000 0x1000>;
92 cache-unified;
93 cache-level = <2>;
94 };
95
6cfd8117 96 ocp {
2eeddb8a 97 compatible = "ti,am4372-l3-noc", "simple-bus";
6cfd8117
AM		 98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges;
9e3269b8 101 ti,hwmods = "l3_main";
2eeddb8a
AM		 102 reg = <0x44000000 0x400000
103 0x44800000 0x400000>;
104 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 106
83a5d6c9
TK		 107 l4_wkup: l4_wkup@44c00000 {
108 compatible = "ti,am4-l4-wkup", "simple-bus";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges = <0 0x44c00000 0x287000>;
6a679208 112
34020422
SA		 113 wkup_m3: wkup_m3@100000 {
114 compatible = "ti,am4372-wkup-m3";
115 reg = <0x100000 0x4000>,
116 <0x180000 0x2000>;
117 reg-names = "umem", "dmem";
118 ti,hwmods = "wkup_m3";
119 ti,pm-firmware = "am335x-pm-firmware.elf";
120 };
121
83a5d6c9
TK		 122 prcm: prcm@1f0000 {
123 compatible = "ti,am4-prcm";
124 reg = <0x1f0000 0x11000>;
6e487001 125 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6a679208 126
83a5d6c9
TK		 127 prcm_clocks: clocks {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 };
6a679208 131
83a5d6c9
TK		 132 prcm_clockdomains: clockdomains {
133 };
6a679208
TK		 134 };
135
83a5d6c9
TK		 136 scm: scm@210000 {
137 compatible = "ti,am4-scm", "simple-bus";
138 reg = <0x210000 0x4000>;
139 #address-cells = <1>;
140 #size-cells = <1>;
141 ranges = <0 0x210000 0x4000>;
142
143 am43xx_pinmux: pinmux@800 {
144 compatible = "ti,am437-padconf",
145 "pinctrl-single";
146 reg = <0x800 0x31c>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149 #interrupt-cells = <1>;
150 interrupt-controller;
151 pinctrl-single,register-width = <32>;
152 pinctrl-single,function-mask = <0xffffffff>;
153 };
154
155 scm_conf: scm_conf@0 {
156 compatible = "syscon";
157 reg = <0x0 0x800>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160
161 scm_clocks: clocks {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 };
165 };
166
c9ab94df
SA		 167 wkup_m3_ipc: wkup_m3_ipc@1324 {
168 compatible = "ti,am4372-wkup-m3-ipc";
169 reg = <0x1324 0x44>;
170 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
171 ti,rproc = <&wkup_m3>;
172 mboxes = <&mailbox &mbox_wkupm3>;
173 };
174
83a5d6c9
TK		 175 scm_clockdomains: clockdomains {
176 };
6a679208
TK		 177 };
178 };
179
fff75ee1
DG		 180 emif: emif@4c000000 {
181 compatible = "ti,emif-am4372";
182 reg = <0x4c000000 0x1000000>;
183 ti,hwmods = "emif";
184 };
185
9e3269b8
LV		 186 edma: edma@49000000 {
187 compatible = "ti,edma3";
188 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
189 reg = <0x49000000 0x10000>,
190 <0x44e10f90 0x10>;
191 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
194 #dma-cells = <1>;
9e3269b8 195 };
6cfd8117
AM		 196
197 uart0: serial@44e09000 {
198 compatible = "ti,am4372-uart","ti,omap2-uart";
199 reg = <0x44e09000 0x2000>;
200 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 201 ti,hwmods = "uart1";
202 };
203
204 uart1: serial@48022000 {
205 compatible = "ti,am4372-uart","ti,omap2-uart";
206 reg = <0x48022000 0x2000>;
207 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
208 ti,hwmods = "uart2";
209 status = "disabled";
210 };
211
212 uart2: serial@48024000 {
213 compatible = "ti,am4372-uart","ti,omap2-uart";
214 reg = <0x48024000 0x2000>;
215 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
216 ti,hwmods = "uart3";
217 status = "disabled";
218 };
219
220 uart3: serial@481a6000 {
221 compatible = "ti,am4372-uart","ti,omap2-uart";
222 reg = <0x481a6000 0x2000>;
223 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
224 ti,hwmods = "uart4";
225 status = "disabled";
226 };
227
228 uart4: serial@481a8000 {
229 compatible = "ti,am4372-uart","ti,omap2-uart";
230 reg = <0x481a8000 0x2000>;
231 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
232 ti,hwmods = "uart5";
233 status = "disabled";
234 };
235
236 uart5: serial@481aa000 {
237 compatible = "ti,am4372-uart","ti,omap2-uart";
238 reg = <0x481aa000 0x2000>;
239 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
240 ti,hwmods = "uart6";
241 status = "disabled";
6cfd8117
AM		 242 };
243
9e3269b8
LV		 244 mailbox: mailbox@480C8000 {
245 compatible = "ti,omap4-mailbox";
246 reg = <0x480C8000 0x200>;
247 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
248 ti,hwmods = "mailbox";
24df0453 249 #mbox-cells = <1>;
9e3269b8
LV		 250 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <8>;
d27704d1
SA		 252 mbox_wkupm3: wkup_m3 {
253 ti,mbox-tx = <0 0 0>;
254 ti,mbox-rx = <0 0 3>;
255 };
9e3269b8
LV		 256 };
257
6cfd8117
AM		 258 timer1: timer@44e31000 {
259 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
260 reg = <0x44e31000 0x400>;
261 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
262 ti,timer-alwon;
73456012 263 ti,hwmods = "timer1";
6cfd8117
AM		 264 };
265
266 timer2: timer@48040000 {
267 compatible = "ti,am4372-timer","ti,am335x-timer";
268 reg = <0x48040000 0x400>;
269 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 270 ti,hwmods = "timer2";
271 };
272
273 timer3: timer@48042000 {
274 compatible = "ti,am4372-timer","ti,am335x-timer";
275 reg = <0x48042000 0x400>;
276 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
277 ti,hwmods = "timer3";
278 status = "disabled";
279 };
280
281 timer4: timer@48044000 {
282 compatible = "ti,am4372-timer","ti,am335x-timer";
283 reg = <0x48044000 0x400>;
284 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
285 ti,timer-pwm;
286 ti,hwmods = "timer4";
287 status = "disabled";
288 };
289
290 timer5: timer@48046000 {
291 compatible = "ti,am4372-timer","ti,am335x-timer";
292 reg = <0x48046000 0x400>;
293 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
294 ti,timer-pwm;
295 ti,hwmods = "timer5";
296 status = "disabled";
297 };
298
299 timer6: timer@48048000 {
300 compatible = "ti,am4372-timer","ti,am335x-timer";
301 reg = <0x48048000 0x400>;
302 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
303 ti,timer-pwm;
304 ti,hwmods = "timer6";
305 status = "disabled";
306 };
307
308 timer7: timer@4804a000 {
309 compatible = "ti,am4372-timer","ti,am335x-timer";
310 reg = <0x4804a000 0x400>;
311 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
312 ti,timer-pwm;
313 ti,hwmods = "timer7";
314 status = "disabled";
315 };
316
317 timer8: timer@481c1000 {
318 compatible = "ti,am4372-timer","ti,am335x-timer";
319 reg = <0x481c1000 0x400>;
320 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
321 ti,hwmods = "timer8";
322 status = "disabled";
323 };
324
325 timer9: timer@4833d000 {
326 compatible = "ti,am4372-timer","ti,am335x-timer";
327 reg = <0x4833d000 0x400>;
328 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
329 ti,hwmods = "timer9";
330 status = "disabled";
331 };
332
333 timer10: timer@4833f000 {
334 compatible = "ti,am4372-timer","ti,am335x-timer";
335 reg = <0x4833f000 0x400>;
336 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
337 ti,hwmods = "timer10";
338 status = "disabled";
339 };
340
341 timer11: timer@48341000 {
342 compatible = "ti,am4372-timer","ti,am335x-timer";
343 reg = <0x48341000 0x400>;
344 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
345 ti,hwmods = "timer11";
346 status = "disabled";
6cfd8117
AM		 347 };
348
349 counter32k: counter@44e86000 {
350 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
351 reg = <0x44e86000 0x40>;
73456012
AM		 352 ti,hwmods = "counter_32k";
353 };
354
08ecb28a 355 rtc: rtc@44e3e000 {
05743b3a
K		 356 compatible = "ti,am4372-rtc", "ti,am3352-rtc",
357 "ti,da830-rtc";
73456012
AM		 358 reg = <0x44e3e000 0x1000>;
359 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
361 ti,hwmods = "rtc";
fff51e77
K		 362 clocks = <&clk_32768_ck>;
363 clock-names = "int-clk";
73456012
AM		 364 status = "disabled";
365 };
366
08ecb28a 367 wdt: wdt@44e35000 {
73456012
AM		 368 compatible = "ti,am4372-wdt","ti,omap3-wdt";
369 reg = <0x44e35000 0x1000>;
370 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
371 ti,hwmods = "wd_timer2";
73456012
AM		 372 };
373
374 gpio0: gpio@44e07000 {
375 compatible = "ti,am4372-gpio","ti,omap4-gpio";
376 reg = <0x44e07000 0x1000>;
377 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 ti,hwmods = "gpio1";
383 status = "disabled";
384 };
385
386 gpio1: gpio@4804c000 {
387 compatible = "ti,am4372-gpio","ti,omap4-gpio";
388 reg = <0x4804c000 0x1000>;
389 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 ti,hwmods = "gpio2";
395 status = "disabled";
396 };
397
398 gpio2: gpio@481ac000 {
399 compatible = "ti,am4372-gpio","ti,omap4-gpio";
400 reg = <0x481ac000 0x1000>;
401 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
402 gpio-controller;
403 #gpio-cells = <2>;
404 interrupt-controller;
405 #interrupt-cells = <2>;
406 ti,hwmods = "gpio3";
407 status = "disabled";
408 };
409
410 gpio3: gpio@481ae000 {
411 compatible = "ti,am4372-gpio","ti,omap4-gpio";
412 reg = <0x481ae000 0x1000>;
413 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
414 gpio-controller;
415 #gpio-cells = <2>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 ti,hwmods = "gpio4";
419 status = "disabled";
420 };
421
422 gpio4: gpio@48320000 {
423 compatible = "ti,am4372-gpio","ti,omap4-gpio";
424 reg = <0x48320000 0x1000>;
425 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
426 gpio-controller;
427 #gpio-cells = <2>;
428 interrupt-controller;
429 #interrupt-cells = <2>;
430 ti,hwmods = "gpio5";
431 status = "disabled";
432 };
433
434 gpio5: gpio@48322000 {
435 compatible = "ti,am4372-gpio","ti,omap4-gpio";
436 reg = <0x48322000 0x1000>;
437 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
438 gpio-controller;
439 #gpio-cells = <2>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 ti,hwmods = "gpio6";
443 status = "disabled";
444 };
445
fd4a8a68
SA		 446 hwspinlock: spinlock@480ca000 {
447 compatible = "ti,omap4-hwspinlock";
448 reg = <0x480ca000 0x1000>;
449 ti,hwmods = "spinlock";
450 #hwlock-cells = <1>;
451 };
452
73456012
AM		 453 i2c0: i2c@44e0b000 {
454 compatible = "ti,am4372-i2c","ti,omap4-i2c";
455 reg = <0x44e0b000 0x1000>;
456 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
457 ti,hwmods = "i2c1";
458 #address-cells = <1>;
459 #size-cells = <0>;
460 status = "disabled";
461 };
462
463 i2c1: i2c@4802a000 {
464 compatible = "ti,am4372-i2c","ti,omap4-i2c";
465 reg = <0x4802a000 0x1000>;
466 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
467 ti,hwmods = "i2c2";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 status = "disabled";
471 };
472
473 i2c2: i2c@4819c000 {
474 compatible = "ti,am4372-i2c","ti,omap4-i2c";
475 reg = <0x4819c000 0x1000>;
476 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
477 ti,hwmods = "i2c3";
478 #address-cells = <1>;
479 #size-cells = <0>;
480 status = "disabled";
481 };
482
483 spi0: spi@48030000 {
484 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
485 reg = <0x48030000 0x400>;
486 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
487 ti,hwmods = "spi0";
488 #address-cells = <1>;
489 #size-cells = <0>;
490 status = "disabled";
491 };
492
9e3269b8
LV		 493 mmc1: mmc@48060000 {
494 compatible = "ti,omap4-hsmmc";
495 reg = <0x48060000 0x1000>;
496 ti,hwmods = "mmc1";
497 ti,dual-volt;
498 ti,needs-special-reset;
499 dmas = <&edma 24
500 &edma 25>;
501 dma-names = "tx", "rx";
502 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
503 status = "disabled";
504 };
505
506 mmc2: mmc@481d8000 {
507 compatible = "ti,omap4-hsmmc";
508 reg = <0x481d8000 0x1000>;
509 ti,hwmods = "mmc2";
510 ti,needs-special-reset;
511 dmas = <&edma 2
512 &edma 3>;
513 dma-names = "tx", "rx";
514 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
515 status = "disabled";
516 };
517
518 mmc3: mmc@47810000 {
519 compatible = "ti,omap4-hsmmc";
520 reg = <0x47810000 0x1000>;
521 ti,hwmods = "mmc3";
522 ti,needs-special-reset;
523 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
524 status = "disabled";
525 };
526
73456012
AM		 527 spi1: spi@481a0000 {
528 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
529 reg = <0x481a0000 0x400>;
530 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
531 ti,hwmods = "spi1";
532 #address-cells = <1>;
533 #size-cells = <0>;
534 status = "disabled";
535 };
536
537 spi2: spi@481a2000 {
538 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
539 reg = <0x481a2000 0x400>;
540 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
541 ti,hwmods = "spi2";
542 #address-cells = <1>;
543 #size-cells = <0>;
544 status = "disabled";
545 };
546
547 spi3: spi@481a4000 {
548 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
549 reg = <0x481a4000 0x400>;
550 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
551 ti,hwmods = "spi3";
552 #address-cells = <1>;
553 #size-cells = <0>;
554 status = "disabled";
555 };
556
557 spi4: spi@48345000 {
558 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
559 reg = <0x48345000 0x400>;
560 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
561 ti,hwmods = "spi4";
562 #address-cells = <1>;
563 #size-cells = <0>;
564 status = "disabled";
565 };
566
567 mac: ethernet@4a100000 {
568 compatible = "ti,am4372-cpsw","ti,cpsw";
569 reg = <0x4a100000 0x800
570 0x4a101200 0x100>;
571 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
572 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
573 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
574 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 575 #address-cells = <1>;
576 #size-cells = <1>;
73456012 577 ti,hwmods = "cpgmac0";
dff8a207
K		 578 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
579 <&dpll_clksel_mac_clk>;
580 clock-names = "fck", "cpts", "50mclk";
581 assigned-clocks = <&dpll_clksel_mac_clk>;
582 assigned-clock-rates = <50000000>;
73456012 583 status = "disabled";
9e3269b8
LV		 584 cpdma_channels = <8>;
585 ale_entries = <1024>;
586 bd_ram_size = <0x2000>;
587 no_bd_ram = <0>;
588 rx_descs = <64>;
589 mac_control = <0x20>;
590 slaves = <2>;
591 active_slave = <0>;
592 cpts_clock_mult = <0x80000000>;
593 cpts_clock_shift = <29>;
594 ranges;
cec42849 595 syscon = <&scm_conf>;
9e3269b8
LV		 596
597 davinci_mdio: mdio@4a101000 {
598 compatible = "ti,am4372-mdio","ti,davinci_mdio";
599 reg = <0x4a101000 0x100>;
600 #address-cells = <1>;
601 #size-cells = <0>;
602 ti,hwmods = "davinci_mdio";
603 bus_freq = <1000000>;
604 status = "disabled";
605 };
606
607 cpsw_emac0: slave@4a100200 {
608 /* Filled in by U-Boot */
609 mac-address = [ 00 00 00 00 00 00 ];
610 };
611
612 cpsw_emac1: slave@4a100300 {
613 /* Filled in by U-Boot */
614 mac-address = [ 00 00 00 00 00 00 ];
615 };
a9682cfb
M		 616
617 phy_sel: cpsw-phy-sel@44e10650 {
618 compatible = "ti,am43xx-cpsw-phy-sel";
619 reg= <0x44e10650 0x4>;
620 reg-names = "gmii-sel";
621 };
73456012
AM		 622 };
623
624 epwmss0: epwmss@48300000 {
625 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
626 reg = <0x48300000 0x10>;
9e3269b8
LV		 627 #address-cells = <1>;
628 #size-cells = <1>;
629 ranges;
73456012
AM		 630 ti,hwmods = "epwmss0";
631 status = "disabled";
9e3269b8
LV		 632
633 ecap0: ecap@48300100 {
634 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 635 #pwm-cells = <3>;
9e3269b8
LV		 636 reg = <0x48300100 0x80>;
637 ti,hwmods = "ecap0";
638 status = "disabled";
639 };
640
641 ehrpwm0: ehrpwm@48300200 {
642 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 643 #pwm-cells = <3>;
9e3269b8
LV		 644 reg = <0x48300200 0x80>;
645 ti,hwmods = "ehrpwm0";
646 status = "disabled";
647 };
73456012
AM		 648 };
649
650 epwmss1: epwmss@48302000 {
651 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
652 reg = <0x48302000 0x10>;
9e3269b8
LV		 653 #address-cells = <1>;
654 #size-cells = <1>;
655 ranges;
73456012
AM		 656 ti,hwmods = "epwmss1";
657 status = "disabled";
9e3269b8
LV		 658
659 ecap1: ecap@48302100 {
660 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 661 #pwm-cells = <3>;
9e3269b8
LV		 662 reg = <0x48302100 0x80>;
663 ti,hwmods = "ecap1";
664 status = "disabled";
665 };
666
667 ehrpwm1: ehrpwm@48302200 {
668 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 669 #pwm-cells = <3>;
9e3269b8
LV		 670 reg = <0x48302200 0x80>;
671 ti,hwmods = "ehrpwm1";
672 status = "disabled";
673 };
73456012
AM		 674 };
675
676 epwmss2: epwmss@48304000 {
677 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
678 reg = <0x48304000 0x10>;
9e3269b8
LV		 679 #address-cells = <1>;
680 #size-cells = <1>;
681 ranges;
73456012
AM		 682 ti,hwmods = "epwmss2";
683 status = "disabled";
9e3269b8
LV		 684
685 ecap2: ecap@48304100 {
686 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 687 #pwm-cells = <3>;
9e3269b8
LV		 688 reg = <0x48304100 0x80>;
689 ti,hwmods = "ecap2";
690 status = "disabled";
691 };
692
693 ehrpwm2: ehrpwm@48304200 {
694 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 695 #pwm-cells = <3>;
9e3269b8
LV		 696 reg = <0x48304200 0x80>;
697 ti,hwmods = "ehrpwm2";
698 status = "disabled";
699 };
73456012
AM		 700 };
701
702 epwmss3: epwmss@48306000 {
703 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
704 reg = <0x48306000 0x10>;
9e3269b8
LV		 705 #address-cells = <1>;
706 #size-cells = <1>;
707 ranges;
73456012
AM		 708 ti,hwmods = "epwmss3";
709 status = "disabled";
9e3269b8
LV		 710
711 ehrpwm3: ehrpwm@48306200 {
712 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 713 #pwm-cells = <3>;
9e3269b8
LV		 714 reg = <0x48306200 0x80>;
715 ti,hwmods = "ehrpwm3";
716 status = "disabled";
717 };
73456012
AM		 718 };
719
720 epwmss4: epwmss@48308000 {
721 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
722 reg = <0x48308000 0x10>;
9e3269b8
LV		 723 #address-cells = <1>;
724 #size-cells = <1>;
725 ranges;
73456012
AM		 726 ti,hwmods = "epwmss4";
727 status = "disabled";
9e3269b8
LV		 728
729 ehrpwm4: ehrpwm@48308200 {
730 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 731 #pwm-cells = <3>;
9e3269b8
LV		 732 reg = <0x48308200 0x80>;
733 ti,hwmods = "ehrpwm4";
734 status = "disabled";
735 };
73456012
AM		 736 };
737
738 epwmss5: epwmss@4830a000 {
739 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
740 reg = <0x4830a000 0x10>;
9e3269b8
LV		 741 #address-cells = <1>;
742 #size-cells = <1>;
743 ranges;
73456012
AM		 744 ti,hwmods = "epwmss5";
745 status = "disabled";
9e3269b8
LV		 746
747 ehrpwm5: ehrpwm@4830a200 {
748 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 749 #pwm-cells = <3>;
9e3269b8
LV		 750 reg = <0x4830a200 0x80>;
751 ti,hwmods = "ehrpwm5";
752 status = "disabled";
753 };
754 };
755
0f39f7b9
V		 756 tscadc: tscadc@44e0d000 {
757 compatible = "ti,am3359-tscadc";
758 reg = <0x44e0d000 0x1000>;
759 ti,hwmods = "adc_tsc";
760 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&adc_tsc_fck>;
762 clock-names = "fck";
763 status = "disabled";
764
765 tsc {
766 compatible = "ti,am3359-tsc";
767 };
768
769 adc {
770 #io-channel-cells = <1>;
771 compatible = "ti,am3359-adc";
772 };
773
774 };
775
9e3269b8
LV		 776 sham: sham@53100000 {
777 compatible = "ti,omap5-sham";
778 ti,hwmods = "sham";
779 reg = <0x53100000 0x300>;
780 dmas = <&edma 36>;
781 dma-names = "rx";
782 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117 783 };
6e70a510
JF		 784
785 aes: aes@53501000 {
786 compatible = "ti,omap4-aes";
787 ti,hwmods = "aes";
788 reg = <0x53501000 0xa0>;
789 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 790 dmas = <&edma 6
791 &edma 5>;
792 dma-names = "tx", "rx";
6e70a510 793 };
099f3a85
JF		 794
795 des: des@53701000 {
796 compatible = "ti,omap4-des";
797 ti,hwmods = "des";
798 reg = <0x53701000 0xa0>;
799 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 800 dmas = <&edma 34
801 &edma 33>;
802 dma-names = "tx", "rx";
099f3a85 803 };
9e3269b8 804
b9c95bf4
PU		 805 mcasp0: mcasp@48038000 {
806 compatible = "ti,am33xx-mcasp-audio";
807 ti,hwmods = "mcasp0";
808 reg = <0x48038000 0x2000>,
809 <0x46000000 0x400000>;
810 reg-names = "mpu", "dat";
811 interrupts = <80>, <81>;
ae107d06 812 interrupt-names = "tx", "rx";
b9c95bf4
PU		 813 status = "disabled";
814 dmas = <&edma 8>,
815 <&edma 9>;
816 dma-names = "tx", "rx";
817 };
818
819 mcasp1: mcasp@4803C000 {
820 compatible = "ti,am33xx-mcasp-audio";
821 ti,hwmods = "mcasp1";
822 reg = <0x4803C000 0x2000>,
823 <0x46400000 0x400000>;
824 reg-names = "mpu", "dat";
825 interrupts = <82>, <83>;
ae107d06 826 interrupt-names = "tx", "rx";
b9c95bf4
PU		 827 status = "disabled";
828 dmas = <&edma 10>,
829 <&edma 11>;
830 dma-names = "tx", "rx";
831 };
f68e355c
PG		 832
833 elm: elm@48080000 {
834 compatible = "ti,am3352-elm";
835 reg = <0x48080000 0x2000>;
836 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
837 ti,hwmods = "elm";
838 clocks = <&l4ls_gclk>;
839 clock-names = "fck";
840 status = "disabled";
841 };
842
843 gpmc: gpmc@50000000 {
844 compatible = "ti,am3352-gpmc";
845 ti,hwmods = "gpmc";
201c7e33
FCJ		 846 dmas = <&edma 52>;
847 dma-names = "rxtx";
f68e355c
PG		 848 clocks = <&l3s_gclk>;
849 clock-names = "fck";
850 reg = <0x50000000 0x2000>;
851 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
852 gpmc,num-cs = <7>;
853 gpmc,num-waitpins = <2>;
854 #address-cells = <2>;
855 #size-cells = <1>;
856 status = "disabled";
857 };
a0ae47ea
GC		 858
859 am43xx_control_usb2phy1: control-phy@44e10620 {
860 compatible = "ti,control-phy-usb2-am437";
861 reg = <0x44e10620 0x4>;
862 reg-names = "power";
863 };
864
865 am43xx_control_usb2phy2: control-phy@0x44e10628 {
866 compatible = "ti,control-phy-usb2-am437";
867 reg = <0x44e10628 0x4>;
868 reg-names = "power";
869 };
870
871 ocp2scp0: ocp2scp@483a8000 {
20431db9 872 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 873 #address-cells = <1>;
874 #size-cells = <1>;
875 ranges;
876 ti,hwmods = "ocp2scp0";
877
878 usb2_phy1: phy@483a8000 {
879 compatible = "ti,am437x-usb2";
880 reg = <0x483a8000 0x8000>;
881 ctrl-module = <&am43xx_control_usb2phy1>;
882 clocks = <&usb_phy0_always_on_clk32k>,
883 <&usb_otg_ss0_refclk960m>;
884 clock-names = "wkupclk", "refclk";
885 #phy-cells = <0>;
886 status = "disabled";
887 };
888 };
889
890 ocp2scp1: ocp2scp@483e8000 {
20431db9 891 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 892 #address-cells = <1>;
893 #size-cells = <1>;
894 ranges;
895 ti,hwmods = "ocp2scp1";
896
897 usb2_phy2: phy@483e8000 {
898 compatible = "ti,am437x-usb2";
899 reg = <0x483e8000 0x8000>;
900 ctrl-module = <&am43xx_control_usb2phy2>;
901 clocks = <&usb_phy1_always_on_clk32k>,
902 <&usb_otg_ss1_refclk960m>;
903 clock-names = "wkupclk", "refclk";
904 #phy-cells = <0>;
905 status = "disabled";
906 };
907 };
908
909 dwc3_1: omap_dwc3@48380000 {
910 compatible = "ti,am437x-dwc3";
911 ti,hwmods = "usb_otg_ss0";
912 reg = <0x48380000 0x10000>;
913 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
914 #address-cells = <1>;
915 #size-cells = <1>;
916 utmi-mode = <1>;
917 ranges;
918
919 usb1: usb@48390000 {
920 compatible = "synopsys,dwc3";
4b143f0f 921 reg = <0x48390000 0x10000>;
1d20e4bf
FB		 922 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
925 interrupt-names = "peripheral",
926 "host",
927 "otg";
a0ae47ea
GC		 928 phys = <&usb2_phy1>;
929 phy-names = "usb2-phy";
930 maximum-speed = "high-speed";
931 dr_mode = "otg";
932 status = "disabled";
60f0e628
FB		 933 snps,dis_u3_susphy_quirk;
934 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 935 };
936 };
937
938 dwc3_2: omap_dwc3@483c0000 {
939 compatible = "ti,am437x-dwc3";
940 ti,hwmods = "usb_otg_ss1";
941 reg = <0x483c0000 0x10000>;
942 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
943 #address-cells = <1>;
944 #size-cells = <1>;
945 utmi-mode = <1>;
946 ranges;
947
948 usb2: usb@483d0000 {
949 compatible = "synopsys,dwc3";
4b143f0f 950 reg = <0x483d0000 0x10000>;
1d20e4bf
FB		 951 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
954 interrupt-names = "peripheral",
955 "host",
956 "otg";
a0ae47ea
GC		 957 phys = <&usb2_phy2>;
958 phy-names = "usb2-phy";
959 maximum-speed = "high-speed";
960 dr_mode = "otg";
961 status = "disabled";
60f0e628
FB		 962 snps,dis_u3_susphy_quirk;
963 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 964 };
965 };
2a1a5043
SP		 966
967 qspi: qspi@47900000 {
968 compatible = "ti,am4372-qspi";
969 reg = <0x47900000 0x100>;
970 #address-cells = <1>;
971 #size-cells = <0>;
972 ti,hwmods = "qspi";
973 interrupts = <0 138 0x4>;
974 num-cs = <4>;
975 status = "disabled";
976 };
741cac5f
SP		 977
978 hdq: hdq@48347000 {
a895b8a0 979 compatible = "ti,am4372-hdq";
741cac5f
SP		 980 reg = <0x48347000 0x1000>;
981 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&func_12m_clk>;
983 clock-names = "fck";
984 ti,hwmods = "hdq1w";
985 status = "disabled";
986 };
8c793367
SP		 987
988 dss: dss@4832a000 {
989 compatible = "ti,omap3-dss";
990 reg = <0x4832a000 0x200>;
991 status = "disabled";
992 ti,hwmods = "dss_core";
993 clocks = <&disp_clk>;
994 clock-names = "fck";
995 #address-cells = <1>;
996 #size-cells = <1>;
997 ranges;
998
08ecb28a 999 dispc: dispc@4832a400 {
8c793367
SP		 1000 compatible = "ti,omap3-dispc";
1001 reg = <0x4832a400 0x400>;
1002 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1003 ti,hwmods = "dss_dispc";
1004 clocks = <&disp_clk>;
1005 clock-names = "fck";
1006 };
1007
1008 rfbi: rfbi@4832a800 {
1009 compatible = "ti,omap3-rfbi";
1010 reg = <0x4832a800 0x100>;
1011 ti,hwmods = "dss_rfbi";
1012 clocks = <&disp_clk>;
1013 clock-names = "fck";
22a5dc10 1014 status = "disabled";
8c793367
SP		 1015 };
1016 };
8b9a2810
RN		 1017
1018 ocmcram: ocmcram@40300000 {
1019 compatible = "mmio-sram";
1020 reg = <0x40300000 0x40000>; /* 256k */
1021 };
9e63b0d4
RQ		 1022
1023 dcan0: can@481cc000 {
1024 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1025 ti,hwmods = "d_can0";
1026 clocks = <&dcan0_fck>;
1027 clock-names = "fck";
1028 reg = <0x481cc000 0x2000>;
83a5d6c9 1029 syscon-raminit = <&scm_conf 0x644 0>;
9e63b0d4
RQ		 1030 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1031 status = "disabled";
1032 };
1033
1034 dcan1: can@481d0000 {
1035 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1036 ti,hwmods = "d_can1";
1037 clocks = <&dcan1_fck>;
1038 clock-names = "fck";
1039 reg = <0x481d0000 0x2000>;
83a5d6c9 1040 syscon-raminit = <&scm_conf 0x644 1>;
9e63b0d4
RQ		 1041 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1042 status = "disabled";
1043 };
9d0df0a6
BP		 1044
1045 vpfe0: vpfe@48326000 {
1046 compatible = "ti,am437x-vpfe";
1047 reg = <0x48326000 0x2000>;
1048 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1049 ti,hwmods = "vpfe0";
1050 status = "disabled";
1051 };
1052
1053 vpfe1: vpfe@48328000 {
1054 compatible = "ti,am437x-vpfe";
1055 reg = <0x48328000 0x2000>;
1056 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1057 ti,hwmods = "vpfe1";
1058 status = "disabled";
1059 };
6cfd8117
AM		 1060 };
1061};
6a679208
TK		 1062
1063/include/ "am43xx-clocks.dtsi"
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