[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / am4372.dtsi

/*
 * Device Tree Source for AM4372 SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,am4372", "ti,am43";
	interrupt-parent = <&gic>;


	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		serial0 = &uart0;
		ethernet0 = &cpsw_emac0;
		ethernet1 = &cpsw_emac1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
		};
	};

	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
	};

	l2-cache-controller@48242000 {
		compatible = "arm,pl310-cache";
		reg = <0x48242000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	am43xx_pinmux: pinmux@44e10800 {
		compatible = "pinctrl-single";
		reg = <0x44e10800 0x31c>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		edma: edma@49000000 {
			compatible = "ti,edma3";
			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
			reg =	<0x49000000 0x10000>,
				<0x44e10f90 0x10>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			dma-channels = <64>;
			ti,edma-regions = <4>;
			ti,edma-slots = <256>;
		};

		uart0: serial@44e09000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x44e09000 0x2000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart1";
		};

		uart1: serial@48022000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48022000 0x2000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart2";
			status = "disabled";
		};

		uart2: serial@48024000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48024000 0x2000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart3";
			status = "disabled";
		};

		uart3: serial@481a6000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a6000 0x2000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart4";
			status = "disabled";
		};

		uart4: serial@481a8000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a8000 0x2000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart5";
			status = "disabled";
		};

		uart5: serial@481aa000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481aa000 0x2000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart6";
			status = "disabled";
		};

		mailbox: mailbox@480C8000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x480C8000 0x200>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mailbox";
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <8>;
			ti,mbox-names = "wkup_m3";
			ti,mbox-data = <0 0 0 0>;
			status = "disabled";
		};

		timer1: timer@44e31000 {
			compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
			reg = <0x44e31000 0x400>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-alwon;
			ti,hwmods = "timer1";
		};

		timer2: timer@48040000  {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48040000  0x400>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48042000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48042000 0x400>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer3";
			status = "disabled";
		};

		timer4: timer@48044000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48044000 0x400>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer4";
			status = "disabled";
		};

		timer5: timer@48046000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48046000 0x400>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer5";
			status = "disabled";
		};

		timer6: timer@48048000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48048000 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer6";
			status = "disabled";
		};

		timer7: timer@4804a000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4804a000 0x400>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer7";
			status = "disabled";
		};

		timer8: timer@481c1000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x481c1000 0x400>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer8";
			status = "disabled";
		};

		timer9: timer@4833d000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833d000 0x400>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer9";
			status = "disabled";
		};

		timer10: timer@4833f000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833f000 0x400>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer10";
			status = "disabled";
		};

		timer11: timer@48341000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48341000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer11";
			status = "disabled";
		};

		counter32k: counter@44e86000 {
			compatible = "ti,am4372-counter32k","ti,omap-counter32k";
			reg = <0x44e86000 0x40>;
			ti,hwmods = "counter_32k";
		};

		rtc@44e3e000 {
			compatible = "ti,am4372-rtc","ti,da830-rtc";
			reg = <0x44e3e000 0x1000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "rtc";
			status = "disabled";
		};

		wdt@44e35000 {
			compatible = "ti,am4372-wdt","ti,omap3-wdt";
			reg = <0x44e35000 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "wd_timer2";
		};

		gpio0: gpio@44e07000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x44e07000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio1";
			status = "disabled";
		};

		gpio1: gpio@4804c000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x4804c000 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio2";
			status = "disabled";
		};

		gpio2: gpio@481ac000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ac000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio3";
			status = "disabled";
		};

		gpio3: gpio@481ae000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ae000 0x1000>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio4";
			status = "disabled";
		};

		gpio4: gpio@48320000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48320000 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio5";
			status = "disabled";
		};

		gpio5: gpio@48322000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48322000 0x1000>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio6";
			status = "disabled";
		};

		i2c0: i2c@44e0b000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x44e0b000 0x1000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@4802a000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4802a000 0x1000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@4819c000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4819c000 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi0: spi@48030000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48030000 0x400>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi0";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mmc1: mmc@48060000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x48060000 0x1000>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&edma 24
				&edma 25>;
			dma-names = "tx", "rx";
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		mmc2: mmc@481d8000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x481d8000 0x1000>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&edma 2
				&edma 3>;
			dma-names = "tx", "rx";
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		mmc3: mmc@47810000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x47810000 0x1000>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		spi1: spi@481a0000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a0000 0x400>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@481a2000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a2000 0x400>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi3: spi@481a4000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a4000 0x400>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@48345000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48345000 0x400>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi4";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mac: ethernet@4a100000 {
			compatible = "ti,am4372-cpsw","ti,cpsw";
			reg = <0x4a100000 0x800
			       0x4a101200 0x100>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			ti,hwmods = "cpgmac0";
			status = "disabled";
			cpdma_channels = <8>;
			ale_entries = <1024>;
			bd_ram_size = <0x2000>;
			no_bd_ram = <0>;
			rx_descs = <64>;
			mac_control = <0x20>;
			slaves = <2>;
			active_slave = <0>;
			cpts_clock_mult = <0x80000000>;
			cpts_clock_shift = <29>;
			ranges;

			davinci_mdio: mdio@4a101000 {
				compatible = "ti,am4372-mdio","ti,davinci_mdio";
				reg = <0x4a101000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				ti,hwmods = "davinci_mdio";
				bus_freq = <1000000>;
				status = "disabled";
			};

			cpsw_emac0: slave@4a100200 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};

			cpsw_emac1: slave@4a100300 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};
		};

		epwmss0: epwmss@48300000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48300000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss0";
			status = "disabled";

			ecap0: ecap@48300100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
				reg = <0x48300100 0x80>;
				ti,hwmods = "ecap0";
				status = "disabled";
			};

			ehrpwm0: ehrpwm@48300200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x48300200 0x80>;
				ti,hwmods = "ehrpwm0";
				status = "disabled";
			};
		};

		epwmss1: epwmss@48302000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48302000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss1";
			status = "disabled";

			ecap1: ecap@48302100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
				reg = <0x48302100 0x80>;
				ti,hwmods = "ecap1";
				status = "disabled";
			};

			ehrpwm1: ehrpwm@48302200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x48302200 0x80>;
				ti,hwmods = "ehrpwm1";
				status = "disabled";
			};
		};

		epwmss2: epwmss@48304000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48304000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss2";
			status = "disabled";

			ecap2: ecap@48304100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
				reg = <0x48304100 0x80>;
				ti,hwmods = "ecap2";
				status = "disabled";
			};

			ehrpwm2: ehrpwm@48304200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x48304200 0x80>;
				ti,hwmods = "ehrpwm2";
				status = "disabled";
			};
		};

		epwmss3: epwmss@48306000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48306000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss3";
			status = "disabled";

			ehrpwm3: ehrpwm@48306200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x48306200 0x80>;
				ti,hwmods = "ehrpwm3";
				status = "disabled";
			};
		};

		epwmss4: epwmss@48308000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48308000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss4";
			status = "disabled";

			ehrpwm4: ehrpwm@48308200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x48308200 0x80>;
				ti,hwmods = "ehrpwm4";
				status = "disabled";
			};
		};

		epwmss5: epwmss@4830a000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x4830a000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss5";
			status = "disabled";

			ehrpwm5: ehrpwm@4830a200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x4830a200 0x80>;
				ti,hwmods = "ehrpwm5";
				status = "disabled";
			};
		};

		sham: sham@53100000 {
			compatible = "ti,omap5-sham";
			ti,hwmods = "sham";
			reg = <0x53100000 0x300>;
			dmas = <&edma 36>;
			dma-names = "rx";
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
		};

		aes: aes@53501000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes";
			reg = <0x53501000 0xa0>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&edma 6
				&edma 5>;
			dma-names = "tx", "rx";
		};

		des: des@53701000 {
			compatible = "ti,omap4-des";
			ti,hwmods = "des";
			reg = <0x53701000 0xa0>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&edma 34
				&edma 33>;
			dma-names = "tx", "rx";
		};

		mcasp0: mcasp@48038000 {
			compatible = "ti,am33xx-mcasp-audio";
			ti,hwmods = "mcasp0";
			reg = <0x48038000 0x2000>,
			      <0x46000000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <80>, <81>;
			interrupts-names = "tx", "rx";
			status = "disabled";
			dmas = <&edma 8>,
			       <&edma 9>;
			dma-names = "tx", "rx";
		};

		mcasp1: mcasp@4803C000 {
			compatible = "ti,am33xx-mcasp-audio";
			ti,hwmods = "mcasp1";
			reg = <0x4803C000 0x2000>,
			      <0x46400000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <82>, <83>;
			interrupts-names = "tx", "rx";
			status = "disabled";
			dmas = <&edma 10>,
			       <&edma 11>;
			dma-names = "tx", "rx";
		};
	};
};
Commit	Line	Data
6cfd8117 AM	1	/*
	2	* Device Tree Source for AM4372 SoC
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
	12
	13	#include "skeleton.dtsi"
	14
	15	/ {
	16	compatible = "ti,am4372", "ti,am43";
	17	interrupt-parent = <&gic>;
	18
	19
	20	aliases {
6a968678 NM	21	i2c0 = &i2c0;
	22	i2c1 = &i2c1;
	23	i2c2 = &i2c2;
6cfd8117	24	serial0 = &uart0;
9e3269b8 LV	25	ethernet0 = &cpsw_emac0;
9e3269b8 LV	26	ethernet1 = &cpsw_emac1;
6cfd8117 AM	27	};
	28
	29	cpus {
738c7409 AM	30	#address-cells = <1>;
738c7409 AM	31	#size-cells = <0>;
6cfd8117 AM	32	cpu@0 {
6cfd8117 AM	33	compatible = "arm,cortex-a9";
738c7409 AM	34	device_type = "cpu";
738c7409 AM	35	reg = <0>;
6cfd8117 AM	36	};
	37	};
	38
	39	gic: interrupt-controller@48241000 {
	40	compatible = "arm,cortex-a9-gic";
	41	interrupt-controller;
	42	#interrupt-cells = <3>;
	43	reg = <0x48241000 0x1000>,
	44	<0x48240100 0x0100>;
	45	};
	46
9e3269b8 LV	47	l2-cache-controller@48242000 {
	48	compatible = "arm,pl310-cache";
	49	reg = <0x48242000 0x1000>;
	50	cache-unified;
	51	cache-level = <2>;
	52	};
	53
	54	am43xx_pinmux: pinmux@44e10800 {
	55	compatible = "pinctrl-single";
	56	reg = <0x44e10800 0x31c>;
	57	#address-cells = <1>;
	58	#size-cells = <0>;
	59	pinctrl-single,register-width = <32>;
	60	pinctrl-single,function-mask = <0xffffffff>;
	61	};
	62
6cfd8117 AM	63	ocp {
	64	compatible = "simple-bus";
	65	#address-cells = <1>;
	66	#size-cells = <1>;
	67	ranges;
9e3269b8 LV	68	ti,hwmods = "l3_main";
	69
	70	edma: edma@49000000 {
	71	compatible = "ti,edma3";
	72	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
	73	reg = <0x49000000 0x10000>,
	74	<0x44e10f90 0x10>;
	75	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	76	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	77	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	78	#dma-cells = <1>;
	79	dma-channels = <64>;
	80	ti,edma-regions = <4>;
	81	ti,edma-slots = <256>;
	82	};
6cfd8117 AM	83
	84	uart0: serial@44e09000 {
	85	compatible = "ti,am4372-uart","ti,omap2-uart";
	86	reg = <0x44e09000 0x2000>;
	87	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012 AM	88	ti,hwmods = "uart1";
	89	};
	90
	91	uart1: serial@48022000 {
	92	compatible = "ti,am4372-uart","ti,omap2-uart";
	93	reg = <0x48022000 0x2000>;
	94	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	95	ti,hwmods = "uart2";
	96	status = "disabled";
	97	};
	98
	99	uart2: serial@48024000 {
	100	compatible = "ti,am4372-uart","ti,omap2-uart";
	101	reg = <0x48024000 0x2000>;
	102	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	103	ti,hwmods = "uart3";
	104	status = "disabled";
	105	};
	106
	107	uart3: serial@481a6000 {
	108	compatible = "ti,am4372-uart","ti,omap2-uart";
	109	reg = <0x481a6000 0x2000>;
	110	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	111	ti,hwmods = "uart4";
	112	status = "disabled";
	113	};
	114
	115	uart4: serial@481a8000 {
	116	compatible = "ti,am4372-uart","ti,omap2-uart";
	117	reg = <0x481a8000 0x2000>;
	118	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	119	ti,hwmods = "uart5";
	120	status = "disabled";
	121	};
	122
	123	uart5: serial@481aa000 {
	124	compatible = "ti,am4372-uart","ti,omap2-uart";
	125	reg = <0x481aa000 0x2000>;
	126	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	127	ti,hwmods = "uart6";
	128	status = "disabled";
6cfd8117 AM	129	};
6cfd8117 AM	130
9e3269b8 LV	131	mailbox: mailbox@480C8000 {
	132	compatible = "ti,omap4-mailbox";
	133	reg = <0x480C8000 0x200>;
	134	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	135	ti,hwmods = "mailbox";
	136	ti,mbox-num-users = <4>;
	137	ti,mbox-num-fifos = <8>;
	138	ti,mbox-names = "wkup_m3";
	139	ti,mbox-data = <0 0 0 0>;
	140	status = "disabled";
	141	};
	142
6cfd8117 AM	143	timer1: timer@44e31000 {
	144	compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
	145	reg = <0x44e31000 0x400>;
	146	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	147	ti,timer-alwon;
73456012	148	ti,hwmods = "timer1";
6cfd8117 AM	149	};
	150
	151	timer2: timer@48040000 {
	152	compatible = "ti,am4372-timer","ti,am335x-timer";
	153	reg = <0x48040000 0x400>;
	154	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012 AM	155	ti,hwmods = "timer2";
	156	};
	157
	158	timer3: timer@48042000 {
	159	compatible = "ti,am4372-timer","ti,am335x-timer";
	160	reg = <0x48042000 0x400>;
	161	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	162	ti,hwmods = "timer3";
	163	status = "disabled";
	164	};
	165
	166	timer4: timer@48044000 {
	167	compatible = "ti,am4372-timer","ti,am335x-timer";
	168	reg = <0x48044000 0x400>;
	169	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	170	ti,timer-pwm;
	171	ti,hwmods = "timer4";
	172	status = "disabled";
	173	};
	174
	175	timer5: timer@48046000 {
	176	compatible = "ti,am4372-timer","ti,am335x-timer";
	177	reg = <0x48046000 0x400>;
	178	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	179	ti,timer-pwm;
	180	ti,hwmods = "timer5";
	181	status = "disabled";
	182	};
	183
	184	timer6: timer@48048000 {
	185	compatible = "ti,am4372-timer","ti,am335x-timer";
	186	reg = <0x48048000 0x400>;
	187	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	188	ti,timer-pwm;
	189	ti,hwmods = "timer6";
	190	status = "disabled";
	191	};
	192
	193	timer7: timer@4804a000 {
	194	compatible = "ti,am4372-timer","ti,am335x-timer";
	195	reg = <0x4804a000 0x400>;
	196	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	197	ti,timer-pwm;
	198	ti,hwmods = "timer7";
	199	status = "disabled";
	200	};
	201
	202	timer8: timer@481c1000 {
	203	compatible = "ti,am4372-timer","ti,am335x-timer";
	204	reg = <0x481c1000 0x400>;
	205	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	206	ti,hwmods = "timer8";
	207	status = "disabled";
	208	};
	209
	210	timer9: timer@4833d000 {
	211	compatible = "ti,am4372-timer","ti,am335x-timer";
	212	reg = <0x4833d000 0x400>;
	213	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	214	ti,hwmods = "timer9";
	215	status = "disabled";
	216	};
	217
	218	timer10: timer@4833f000 {
219	compatible = "ti,am4372-timer","ti,am335x-timer";
220	reg = <0x4833f000 0x400>;
221	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
222	ti,hwmods = "timer10";
223	status = "disabled";
224	};
225
226	timer11: timer@48341000 {
227	compatible = "ti,am4372-timer","ti,am335x-timer";
228	reg = <0x48341000 0x400>;
229	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
230	ti,hwmods = "timer11";
231	status = "disabled";
6cfd8117 AM	232	};
	233
	234	counter32k: counter@44e86000 {
	235	compatible = "ti,am4372-counter32k","ti,omap-counter32k";
	236	reg = <0x44e86000 0x40>;
73456012 AM	237	ti,hwmods = "counter_32k";
	238	};
	239
	240	rtc@44e3e000 {
	241	compatible = "ti,am4372-rtc","ti,da830-rtc";
	242	reg = <0x44e3e000 0x1000>;
	243	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
	244	GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	245	ti,hwmods = "rtc";
	246	status = "disabled";
	247	};
	248
	249	wdt@44e35000 {
	250	compatible = "ti,am4372-wdt","ti,omap3-wdt";
	251	reg = <0x44e35000 0x1000>;
	252	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	253	ti,hwmods = "wd_timer2";
73456012 AM	254	};
	255
	256	gpio0: gpio@44e07000 {
	257	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	258	reg = <0x44e07000 0x1000>;
	259	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	260	gpio-controller;
	261	#gpio-cells = <2>;
	262	interrupt-controller;
	263	#interrupt-cells = <2>;
	264	ti,hwmods = "gpio1";
	265	status = "disabled";
	266	};
	267
	268	gpio1: gpio@4804c000 {
	269	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	270	reg = <0x4804c000 0x1000>;
	271	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	272	gpio-controller;
	273	#gpio-cells = <2>;
	274	interrupt-controller;
	275	#interrupt-cells = <2>;
	276	ti,hwmods = "gpio2";
	277	status = "disabled";
	278	};
	279
	280	gpio2: gpio@481ac000 {
	281	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	282	reg = <0x481ac000 0x1000>;
	283	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	284	gpio-controller;
	285	#gpio-cells = <2>;
	286	interrupt-controller;
	287	#interrupt-cells = <2>;
	288	ti,hwmods = "gpio3";
	289	status = "disabled";
	290	};
	291
	292	gpio3: gpio@481ae000 {
	293	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	294	reg = <0x481ae000 0x1000>;
	295	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	296	gpio-controller;
	297	#gpio-cells = <2>;
	298	interrupt-controller;
	299	#interrupt-cells = <2>;
	300	ti,hwmods = "gpio4";
	301	status = "disabled";
	302	};
	303
	304	gpio4: gpio@48320000 {
	305	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	306	reg = <0x48320000 0x1000>;
	307	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	308	gpio-controller;
	309	#gpio-cells = <2>;
	310	interrupt-controller;
	311	#interrupt-cells = <2>;
	312	ti,hwmods = "gpio5";
	313	status = "disabled";
	314	};
	315
	316	gpio5: gpio@48322000 {
	317	compatible = "ti,am4372-gpio","ti,omap4-gpio";
318	reg = <0x48322000 0x1000>;
319	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
320	gpio-controller;
321	#gpio-cells = <2>;
322	interrupt-controller;
323	#interrupt-cells = <2>;
324	ti,hwmods = "gpio6";
325	status = "disabled";
326	};
327
328	i2c0: i2c@44e0b000 {
329	compatible = "ti,am4372-i2c","ti,omap4-i2c";
330	reg = <0x44e0b000 0x1000>;
331	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
332	ti,hwmods = "i2c1";
333	#address-cells = <1>;
334	#size-cells = <0>;
335	status = "disabled";
336	};
337
338	i2c1: i2c@4802a000 {
339	compatible = "ti,am4372-i2c","ti,omap4-i2c";
340	reg = <0x4802a000 0x1000>;
341	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
342	ti,hwmods = "i2c2";
343	#address-cells = <1>;
344	#size-cells = <0>;
345	status = "disabled";
346	};
347
348	i2c2: i2c@4819c000 {
349	compatible = "ti,am4372-i2c","ti,omap4-i2c";
350	reg = <0x4819c000 0x1000>;
351	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
352	ti,hwmods = "i2c3";
353	#address-cells = <1>;
354	#size-cells = <0>;
355	status = "disabled";
356	};
357
358	spi0: spi@48030000 {
359	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
360	reg = <0x48030000 0x400>;
361	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
362	ti,hwmods = "spi0";
363	#address-cells = <1>;
364	#size-cells = <0>;
365	status = "disabled";
366	};
367
9e3269b8 LV	368	mmc1: mmc@48060000 {
	369	compatible = "ti,omap4-hsmmc";
	370	reg = <0x48060000 0x1000>;
	371	ti,hwmods = "mmc1";
	372	ti,dual-volt;
	373	ti,needs-special-reset;
	374	dmas = <&edma 24
	375	&edma 25>;
	376	dma-names = "tx", "rx";
	377	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	378	status = "disabled";
	379	};
	380
	381	mmc2: mmc@481d8000 {
	382	compatible = "ti,omap4-hsmmc";
	383	reg = <0x481d8000 0x1000>;
	384	ti,hwmods = "mmc2";
	385	ti,needs-special-reset;
	386	dmas = <&edma 2
	387	&edma 3>;
	388	dma-names = "tx", "rx";
	389	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	390	status = "disabled";
	391	};
	392
	393	mmc3: mmc@47810000 {
	394	compatible = "ti,omap4-hsmmc";
	395	reg = <0x47810000 0x1000>;
	396	ti,hwmods = "mmc3";
	397	ti,needs-special-reset;
	398	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	399	status = "disabled";
	400	};
	401
73456012 AM	402	spi1: spi@481a0000 {
	403	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	404	reg = <0x481a0000 0x400>;
	405	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	406	ti,hwmods = "spi1";
	407	#address-cells = <1>;
	408	#size-cells = <0>;
	409	status = "disabled";
	410	};
	411
	412	spi2: spi@481a2000 {
	413	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	414	reg = <0x481a2000 0x400>;
	415	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	416	ti,hwmods = "spi2";
	417	#address-cells = <1>;
	418	#size-cells = <0>;
	419	status = "disabled";
	420	};
	421
	422	spi3: spi@481a4000 {
	423	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	424	reg = <0x481a4000 0x400>;
	425	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	426	ti,hwmods = "spi3";
	427	#address-cells = <1>;
	428	#size-cells = <0>;
	429	status = "disabled";
	430	};
	431
	432	spi4: spi@48345000 {
	433	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	434	reg = <0x48345000 0x400>;
	435	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
	436	ti,hwmods = "spi4";
	437	#address-cells = <1>;
	438	#size-cells = <0>;
	439	status = "disabled";
	440	};
	441
	442	mac: ethernet@4a100000 {
	443	compatible = "ti,am4372-cpsw","ti,cpsw";
	444	reg = <0x4a100000 0x800
	445	0x4a101200 0x100>;
	446	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
	447	GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
	448	GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
	449	GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 LV	450	#address-cells = <1>;
9e3269b8 LV	451	#size-cells = <1>;
73456012 AM	452	ti,hwmods = "cpgmac0";
73456012 AM	453	status = "disabled";
9e3269b8 LV	454	cpdma_channels = <8>;
	455	ale_entries = <1024>;
	456	bd_ram_size = <0x2000>;
	457	no_bd_ram = <0>;
	458	rx_descs = <64>;
	459	mac_control = <0x20>;
	460	slaves = <2>;
	461	active_slave = <0>;
	462	cpts_clock_mult = <0x80000000>;
	463	cpts_clock_shift = <29>;
	464	ranges;
	465
	466	davinci_mdio: mdio@4a101000 {
	467	compatible = "ti,am4372-mdio","ti,davinci_mdio";
	468	reg = <0x4a101000 0x100>;
	469	#address-cells = <1>;
	470	#size-cells = <0>;
	471	ti,hwmods = "davinci_mdio";
	472	bus_freq = <1000000>;
	473	status = "disabled";
	474	};
	475
	476	cpsw_emac0: slave@4a100200 {
	477	/* Filled in by U-Boot */
	478	mac-address = [ 00 00 00 00 00 00 ];
	479	};
	480
	481	cpsw_emac1: slave@4a100300 {
	482	/* Filled in by U-Boot */
	483	mac-address = [ 00 00 00 00 00 00 ];
	484	};
73456012 AM	485	};
	486
	487	epwmss0: epwmss@48300000 {
	488	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	489	reg = <0x48300000 0x10>;
9e3269b8 LV	490	#address-cells = <1>;
	491	#size-cells = <1>;
	492	ranges;
73456012 AM	493	ti,hwmods = "epwmss0";
73456012 AM	494	status = "disabled";
9e3269b8 LV	495
	496	ecap0: ecap@48300100 {
	497	compatible = "ti,am4372-ecap","ti,am33xx-ecap";
	498	reg = <0x48300100 0x80>;
	499	ti,hwmods = "ecap0";
	500	status = "disabled";
	501	};
	502
	503	ehrpwm0: ehrpwm@48300200 {
	504	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	505	reg = <0x48300200 0x80>;
	506	ti,hwmods = "ehrpwm0";
	507	status = "disabled";
	508	};
73456012 AM	509	};
	510
	511	epwmss1: epwmss@48302000 {
	512	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	513	reg = <0x48302000 0x10>;
9e3269b8 LV	514	#address-cells = <1>;
	515	#size-cells = <1>;
	516	ranges;
73456012 AM	517	ti,hwmods = "epwmss1";
73456012 AM	518	status = "disabled";
9e3269b8 LV	519
	520	ecap1: ecap@48302100 {
	521	compatible = "ti,am4372-ecap","ti,am33xx-ecap";
	522	reg = <0x48302100 0x80>;
	523	ti,hwmods = "ecap1";
	524	status = "disabled";
	525	};
	526
	527	ehrpwm1: ehrpwm@48302200 {
	528	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	529	reg = <0x48302200 0x80>;
	530	ti,hwmods = "ehrpwm1";
	531	status = "disabled";
	532	};
73456012 AM	533	};
	534
	535	epwmss2: epwmss@48304000 {
	536	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	537	reg = <0x48304000 0x10>;
9e3269b8 LV	538	#address-cells = <1>;
	539	#size-cells = <1>;
	540	ranges;
73456012 AM	541	ti,hwmods = "epwmss2";
73456012 AM	542	status = "disabled";
9e3269b8 LV	543
	544	ecap2: ecap@48304100 {
	545	compatible = "ti,am4372-ecap","ti,am33xx-ecap";
	546	reg = <0x48304100 0x80>;
	547	ti,hwmods = "ecap2";
	548	status = "disabled";
	549	};
	550
	551	ehrpwm2: ehrpwm@48304200 {
	552	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	553	reg = <0x48304200 0x80>;
	554	ti,hwmods = "ehrpwm2";
	555	status = "disabled";
	556	};
73456012 AM	557	};
	558
	559	epwmss3: epwmss@48306000 {
	560	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	561	reg = <0x48306000 0x10>;
9e3269b8 LV	562	#address-cells = <1>;
	563	#size-cells = <1>;
	564	ranges;
73456012 AM	565	ti,hwmods = "epwmss3";
73456012 AM	566	status = "disabled";
9e3269b8 LV	567
	568	ehrpwm3: ehrpwm@48306200 {
	569	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	570	reg = <0x48306200 0x80>;
	571	ti,hwmods = "ehrpwm3";
	572	status = "disabled";
	573	};
73456012 AM	574	};
	575
	576	epwmss4: epwmss@48308000 {
	577	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	578	reg = <0x48308000 0x10>;
9e3269b8 LV	579	#address-cells = <1>;
	580	#size-cells = <1>;
	581	ranges;
73456012 AM	582	ti,hwmods = "epwmss4";
73456012 AM	583	status = "disabled";
9e3269b8 LV	584
	585	ehrpwm4: ehrpwm@48308200 {
	586	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	587	reg = <0x48308200 0x80>;
	588	ti,hwmods = "ehrpwm4";
	589	status = "disabled";
	590	};
73456012 AM	591	};
	592
	593	epwmss5: epwmss@4830a000 {
	594	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	595	reg = <0x4830a000 0x10>;
9e3269b8 LV	596	#address-cells = <1>;
	597	#size-cells = <1>;
	598	ranges;
73456012 AM	599	ti,hwmods = "epwmss5";
73456012 AM	600	status = "disabled";
9e3269b8 LV	601
	602	ehrpwm5: ehrpwm@4830a200 {
	603	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	604	reg = <0x4830a200 0x80>;
	605	ti,hwmods = "ehrpwm5";
	606	status = "disabled";
	607	};
	608	};
	609
	610	sham: sham@53100000 {
	611	compatible = "ti,omap5-sham";
	612	ti,hwmods = "sham";
	613	reg = <0x53100000 0x300>;
	614	dmas = <&edma 36>;
	615	dma-names = "rx";
	616	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117	617	};
6e70a510 JF	618
	619	aes: aes@53501000 {
	620	compatible = "ti,omap4-aes";
	621	ti,hwmods = "aes";
	622	reg = <0x53501000 0xa0>;
	623	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 LV	624	dmas = <&edma 6
	625	&edma 5>;
	626	dma-names = "tx", "rx";
6e70a510	627	};
099f3a85 JF	628
	629	des: des@53701000 {
	630	compatible = "ti,omap4-des";
	631	ti,hwmods = "des";
	632	reg = <0x53701000 0xa0>;
	633	interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 LV	634	dmas = <&edma 34
	635	&edma 33>;
	636	dma-names = "tx", "rx";
099f3a85	637	};
9e3269b8	638
b9c95bf4 PU	639	mcasp0: mcasp@48038000 {
	640	compatible = "ti,am33xx-mcasp-audio";
	641	ti,hwmods = "mcasp0";
	642	reg = <0x48038000 0x2000>,
	643	<0x46000000 0x400000>;
	644	reg-names = "mpu", "dat";
	645	interrupts = <80>, <81>;
	646	interrupts-names = "tx", "rx";
	647	status = "disabled";
	648	dmas = <&edma 8>,
	649	<&edma 9>;
	650	dma-names = "tx", "rx";
	651	};
	652
	653	mcasp1: mcasp@4803C000 {
	654	compatible = "ti,am33xx-mcasp-audio";
	655	ti,hwmods = "mcasp1";
	656	reg = <0x4803C000 0x2000>,
	657	<0x46400000 0x400000>;
	658	reg-names = "mpu", "dat";
	659	interrupts = <82>, <83>;
	660	interrupts-names = "tx", "rx";
	661	status = "disabled";
	662	dmas = <&edma 10>,
	663	<&edma 11>;
	664	dma-names = "tx", "rx";
	665	};
6cfd8117 AM	666	};
6cfd8117 AM	667	};