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ca36855e | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
49122145 FF |
2 | /* |
3 | * Device Tree file for Marvell Armada 370 Reference Design board | |
4 | * (RD-88F6710-A1) | |
5 | * | |
6 | * Copied from arch/arm/boot/dts/armada-370-db.dts | |
7 | * | |
8 | * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org> | |
9 | * | |
32c741d0 TP |
10 | * Note: this Device Tree assumes that the bootloader has remapped the |
11 | * internal registers to 0xf1000000 (instead of the default | |
12 | * 0xd0000000). The 0xf1000000 is the default used by the recent, | |
13 | * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier | |
14 | * boards were delivered with an older version of the bootloader that | |
15 | * left internal registers mapped at 0xd0000000. If you are in this | |
16 | * situation, you should either update your bootloader (preferred | |
17 | * solution) or the below Device Tree should be adjusted. | |
49122145 FF |
18 | */ |
19 | ||
20 | /dts-v1/; | |
5c0169d1 | 21 | #include <dt-bindings/input/input.h> |
f8c193ca | 22 | #include <dt-bindings/interrupt-controller/irq.h> |
29e74f8b | 23 | #include <dt-bindings/gpio/gpio.h> |
38149887 | 24 | #include "armada-370.dtsi" |
49122145 FF |
25 | |
26 | / { | |
27 | model = "Marvell Armada 370 Reference Design"; | |
28 | compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; | |
29 | ||
30 | chosen { | |
9552203c | 31 | stdout-path = "serial0:115200n8"; |
49122145 FF |
32 | }; |
33 | ||
6f477f43 | 34 | memory@0 { |
49122145 FF |
35 | device_type = "memory"; |
36 | reg = <0x00000000 0x20000000>; /* 512 MB */ | |
37 | }; | |
38 | ||
39 | soc { | |
32c741d0 | 40 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 |
b416f192 BB |
41 | MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 |
42 | MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; | |
5e12a613 | 43 | |
467f54b2 GC |
44 | internal-regs { |
45 | serial@12000 { | |
467f54b2 | 46 | status = "okay"; |
49122145 | 47 | }; |
467f54b2 GC |
48 | sata@a0000 { |
49 | nr-ports = <2>; | |
50 | status = "okay"; | |
51 | }; | |
52 | ||
467f54b2 GC |
53 | ethernet@70000 { |
54 | status = "okay"; | |
55 | phy = <&phy0>; | |
56 | phy-mode = "sgmii"; | |
57 | }; | |
58 | ethernet@74000 { | |
9dfb5c41 EG |
59 | pinctrl-0 = <&ge1_rgmii_pins>; |
60 | pinctrl-names = "default"; | |
467f54b2 | 61 | status = "okay"; |
467f54b2 | 62 | phy-mode = "rgmii-id"; |
9ef90cbb AL |
63 | fixed-link { |
64 | speed = <1000>; | |
65 | full-duplex; | |
66 | }; | |
467f54b2 | 67 | }; |
56499120 | 68 | |
467f54b2 GC |
69 | mvsdio@d4000 { |
70 | pinctrl-0 = <&sdio_pins1>; | |
71 | pinctrl-names = "default"; | |
72 | status = "okay"; | |
73 | /* No CD or WP GPIOs */ | |
d87b5fbb | 74 | broken-cd; |
467f54b2 | 75 | }; |
e822f75d | 76 | |
467f54b2 GC |
77 | usb@50000 { |
78 | status = "okay"; | |
79 | }; | |
e822f75d | 80 | |
467f54b2 GC |
81 | usb@51000 { |
82 | status = "okay"; | |
83 | }; | |
8c75e7b3 | 84 | |
467f54b2 GC |
85 | gpio-keys { |
86 | compatible = "gpio-keys"; | |
87 | #address-cells = <1>; | |
88 | #size-cells = <0>; | |
9e622af0 | 89 | button { |
467f54b2 | 90 | label = "Software Button"; |
5c0169d1 | 91 | linux,code = <KEY_POWER>; |
29e74f8b | 92 | gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; |
467f54b2 GC |
93 | }; |
94 | }; | |
69e18e26 | 95 | |
e8db78dd TP |
96 | gpio-fan { |
97 | compatible = "gpio-fan"; | |
98 | gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; | |
99 | gpio-fan,speed-map = <0 0 3000 1>; | |
100 | pinctrl-0 = <&fan_pins>; | |
101 | pinctrl-names = "default"; | |
102 | }; | |
103 | ||
5b1e9e80 TP |
104 | gpio_leds { |
105 | compatible = "gpio-leds"; | |
106 | pinctrl-names = "default"; | |
107 | pinctrl-0 = <&led_pins>; | |
108 | ||
109 | sw_led { | |
110 | label = "370rd:green:sw"; | |
111 | gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; | |
112 | default-state = "keep"; | |
113 | }; | |
114 | }; | |
115 | ||
69e18e26 EG |
116 | nand@d0000 { |
117 | status = "okay"; | |
118 | num-cs = <1>; | |
119 | marvell,nand-keep-config; | |
120 | marvell,nand-enable-arbiter; | |
121 | nand-on-flash-bbt; | |
122 | ||
123 | partition@0 { | |
124 | label = "U-Boot"; | |
125 | reg = <0 0x800000>; | |
126 | }; | |
127 | partition@800000 { | |
128 | label = "Linux"; | |
129 | reg = <0x800000 0x800000>; | |
130 | }; | |
131 | partition@1000000 { | |
132 | label = "Filesystem"; | |
133 | reg = <0x1000000 0x3f000000>; | |
134 | }; | |
135 | }; | |
8c75e7b3 EG |
136 | }; |
137 | }; | |
9ef90cbb | 138 | |
eb94ec64 | 139 | dsa { |
4cb2ec8c FF |
140 | status = "disabled"; |
141 | ||
9ef90cbb AL |
142 | compatible = "marvell,dsa"; |
143 | #address-cells = <2>; | |
144 | #size-cells = <0>; | |
145 | ||
146 | dsa,ethernet = <ð1>; | |
147 | dsa,mii-bus = <&mdio>; | |
148 | ||
149 | switch@0 { | |
150 | #address-cells = <1>; | |
151 | #size-cells = <0>; | |
152 | reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */ | |
153 | ||
154 | port@0 { | |
155 | reg = <0>; | |
156 | label = "lan0"; | |
157 | }; | |
158 | ||
159 | port@1 { | |
160 | reg = <1>; | |
161 | label = "lan1"; | |
162 | }; | |
163 | ||
164 | port@2 { | |
165 | reg = <2>; | |
166 | label = "lan2"; | |
167 | }; | |
168 | ||
169 | port@3 { | |
170 | reg = <3>; | |
171 | label = "lan3"; | |
172 | }; | |
173 | ||
174 | port@5 { | |
175 | reg = <5>; | |
176 | label = "cpu"; | |
177 | }; | |
178 | }; | |
179 | }; | |
1fc21295 GC |
180 | }; |
181 | ||
8d977093 GC |
182 | &pciec { |
183 | status = "okay"; | |
184 | ||
185 | /* Internal mini-PCIe connector */ | |
186 | pcie@1,0 { | |
187 | /* Port 0, Lane 0 */ | |
188 | status = "okay"; | |
189 | }; | |
190 | ||
191 | /* Internal mini-PCIe connector */ | |
192 | pcie@2,0 { | |
193 | /* Port 1, Lane 0 */ | |
194 | status = "okay"; | |
195 | }; | |
196 | }; | |
197 | ||
1fc21295 GC |
198 | &mdio { |
199 | pinctrl-0 = <&mdio_pins>; | |
200 | pinctrl-names = "default"; | |
201 | phy0: ethernet-phy@0 { | |
202 | reg = <0>; | |
203 | }; | |
4cb2ec8c FF |
204 | |
205 | switch: switch@10 { | |
206 | compatible = "marvell,mv88e6085"; | |
207 | #address-cells = <1>; | |
208 | #size-cells = <0>; | |
209 | reg = <0x10>; | |
f8c193ca AL |
210 | interrupt-controller; |
211 | #interrupt-cells = <2>; | |
4cb2ec8c FF |
212 | |
213 | ports { | |
214 | #address-cells = <1>; | |
215 | #size-cells = <0>; | |
216 | ||
217 | port@0 { | |
218 | reg = <0>; | |
219 | label = "lan0"; | |
220 | }; | |
221 | ||
222 | port@1 { | |
223 | reg = <1>; | |
224 | label = "lan1"; | |
225 | }; | |
226 | ||
227 | port@2 { | |
228 | reg = <2>; | |
229 | label = "lan2"; | |
230 | }; | |
231 | ||
232 | port@3 { | |
233 | reg = <3>; | |
234 | label = "lan3"; | |
235 | }; | |
236 | ||
237 | port@5 { | |
238 | reg = <5>; | |
239 | label = "cpu"; | |
240 | ethernet = <ð1>; | |
241 | fixed-link { | |
242 | speed = <1000>; | |
243 | full-duplex; | |
244 | }; | |
245 | }; | |
246 | }; | |
f8c193ca AL |
247 | |
248 | mdio { | |
249 | #address-cells = <1>; | |
250 | #size-cells = <0>; | |
251 | ||
252 | switchphy0: switchphy@0 { | |
253 | reg = <0>; | |
254 | interrupt-parent = <&switch>; | |
255 | interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; | |
256 | }; | |
257 | ||
258 | switchphy1: switchphy@1 { | |
259 | reg = <1>; | |
260 | interrupt-parent = <&switch>; | |
261 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; | |
262 | }; | |
263 | ||
264 | switchphy2: switchphy@2 { | |
265 | reg = <2>; | |
266 | interrupt-parent = <&switch>; | |
267 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; | |
268 | }; | |
269 | ||
270 | switchphy3: switchphy@3 { | |
271 | reg = <3>; | |
272 | interrupt-parent = <&switch>; | |
273 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; | |
274 | }; | |
275 | }; | |
4cb2ec8c | 276 | }; |
1fc21295 GC |
277 | }; |
278 | ||
4904a82a AE |
279 | |
280 | &pinctrl { | |
281 | fan_pins: fan-pins { | |
282 | marvell,pins = "mpp8"; | |
283 | marvell,function = "gpio"; | |
284 | }; | |
285 | ||
286 | led_pins: led-pins { | |
287 | marvell,pins = "mpp32"; | |
288 | marvell,function = "gpio"; | |
289 | }; | |
290 | }; |