[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / armada-370-xp.dtsi

/*
 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * This file contains the definitions that are common to the Armada
 * 370 and Armada XP SoC.
 */

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 370 and XP SoC";
	compatible = "marvell,armada-370-xp";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "marvell,sheeva-v7";
			device_type = "cpu";
			reg = <0>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts-extended = <&mpic 3>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&mpic>;
		pcie-mem-aperture = <0xf8000000 0x7e00000>;
		pcie-io-aperture  = <0xffe00000 0x100000>;

		devbus_bootcs: devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs0: devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs1: devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs2: devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs3: devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			rtc: rtc@10300 {
				compatible = "marvell,orion-rtc";
				reg = <0x10300 0x20>;
				interrupts = <50>;
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <31>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <32>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <41>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <42>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl: pin-ctrl@18000 {
				reg = <0x18000 0x38>;
			};

			coredivclk: corediv-clock@18740 {
				compatible = "marvell,armada-370-corediv-clock";
				reg = <0x18740 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>,
				      <0x20250 0x8>;
			};

			mpic: interrupt-controller@20a00 {
				compatible = "marvell,mpic";
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
			};

			coherencyfab: coherency-fabric@20200 {
				compatible = "marvell,coherency-fabric";
				reg = <0x20200 0xb0>, <0x21010 0x1c>;
			};

			timer: timer@20300 {
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
			};

			watchdog: watchdog@20300 {
				reg = <0x20300 0x34>, <0x20704 0x4>;
			};

			cpurst: cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x8>;
			};

			pmsu: pmsu@22000 {
				compatible = "marvell,armada-370-pmsu";
				reg = <0x22000 0x1000>;
			};

			usb0: usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <45>;
				status = "disabled";
			};

			usb1: usb@51000 {
				compatible = "marvell,orion-ehci";
				reg = <0x51000 0x500>;
				interrupts = <46>;
				status = "disabled";
			};

			eth0: ethernet@70000 {
				reg = <0x70000 0x4000>;
				interrupts = <8>;
				clocks = <&gateclk 4>;
				status = "disabled";
			};

			mdio: mdio@72004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x72004 0x4>;
				clocks = <&gateclk 4>;
			};

			eth1: ethernet@74000 {
				reg = <0x74000 0x4000>;
				interrupts = <10>;
				clocks = <&gateclk 3>;
				status = "disabled";
			};

			sata: sata@a0000 {
				compatible = "marvell,armada-370-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <55>;
				clocks = <&gateclk 15>, <&gateclk 30>;
				clock-names = "0", "1";
				status = "disabled";
			};

			nand: nand@d0000 {
				compatible = "marvell,armada370-nand";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupts = <113>;
				clocks = <&coredivclk 0>;
				status = "disabled";
			};

			sdio: mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <54>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};
		};

		spi0: spi@10600 {
			reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
			      <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
			      <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
			      <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
			      <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
			      <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
			      <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
			      <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
			      <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			interrupts = <30>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		spi1: spi@10680 {
			reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
			      <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
			      <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
			      <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
			      <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
			      <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
			      <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
			      <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
			      <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			interrupts = <92>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <2000000000>;
		};
	};
 };
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
8a88daf8 GC	11	* This file is dual-licensed: you can use it either under the terms
	12	* of the GPL or the X11 license, at your option. Note that this dual
	13	* licensing only applies to this file, and not this project as a
	14	* whole.
	15	*
	16	* a) This file is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of the
	19	* License, or (at your option) any later version.
	20	*
	21	* This file is distributed in the hope that it will be useful
	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* Or, alternatively
	27	*
	28	* b) Permission is hereby granted, free of charge, to any person
	29	* obtaining a copy of this software and associated documentation
	30	* files (the "Software"), to deal in the Software without
	31	* restriction, including without limitation the rights to use
	32	* copy, modify, merge, publish, distribute, sublicense, and/or
	33	* sell copies of the Software, and to permit persons to whom the
	34	* Software is furnished to do so, subject to the following
	35	* conditions:
	36	*
	37	* The above copyright notice and this permission notice shall be
	38	* included in all copies or substantial portions of the Software.
	39	*
	40	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	41	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	42	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	43	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	44	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	45	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	46	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	47	* OTHER DEALINGS IN THE SOFTWARE.
9ae6f740 TP	48	*
	49	* This file contains the definitions that are common to the Armada
	50	* 370 and Armada XP SoC.
	51	*/
	52
5e12a613 EG	53	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
5e12a613 EG	54
9ae6f740 TP	55	/ {
9ae6f740 TP	56	model = "Marvell Armada 370 and XP SoC";
92ece1cd	57	compatible = "marvell,armada-370-xp";
9ae6f740	58
be5a9389	59	aliases {
bf6acf16 TP	60	serial0 = &uart0;
bf6acf16 TP	61	serial1 = &uart1;
be5a9389 WT	62	};
be5a9389 WT	63
9ae6f740	64	cpus {
7a7ed290 LP	65	#address-cells = <1>;
7a7ed290 LP	66	#size-cells = <0>;
9ae6f740 TP	67	cpu@0 {
9ae6f740 TP	68	compatible = "marvell,sheeva-v7";
7a7ed290 LP	69	device_type = "cpu";
7a7ed290 LP	70	reg = <0>;
9ae6f740 TP	71	};
	72	};
	73
a87cd07b MR	74	pmu {
	75	compatible = "arm,cortex-a9-pmu";
	76	interrupts-extended = <&mpic 3>;
	77	};
	78
9ae6f740	79	soc {
5e12a613	80	#address-cells = <2>;
9ae6f740	81	#size-cells = <1>;
5e12a613	82	controller = <&mbusc>;
9ae6f740	83	interrupt-parent = <&mpic>;
46febc63 TP	84	pcie-mem-aperture = <0xf8000000 0x7e00000>;
46febc63 TP	85	pcie-io-aperture = <0xffe00000 0x100000>;
9ae6f740	86
11f7135b	87	devbus_bootcs: devbus-bootcs {
de1af8d4 EG	88	compatible = "marvell,mvebu-devbus";
	89	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	90	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	91	#address-cells = <1>;
	92	#size-cells = <1>;
	93	clocks = <&coreclk 0>;
	94	status = "disabled";
	95	};
	96
11f7135b	97	devbus_cs0: devbus-cs0 {
de1af8d4 EG	98	compatible = "marvell,mvebu-devbus";
	99	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	100	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	101	#address-cells = <1>;
	102	#size-cells = <1>;
	103	clocks = <&coreclk 0>;
	104	status = "disabled";
	105	};
	106
11f7135b	107	devbus_cs1: devbus-cs1 {
de1af8d4 EG	108	compatible = "marvell,mvebu-devbus";
	109	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	110	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	111	#address-cells = <1>;
	112	#size-cells = <1>;
	113	clocks = <&coreclk 0>;
	114	status = "disabled";
	115	};
	116
11f7135b	117	devbus_cs2: devbus-cs2 {
de1af8d4 EG	118	compatible = "marvell,mvebu-devbus";
	119	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	120	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	121	#address-cells = <1>;
	122	#size-cells = <1>;
	123	clocks = <&coreclk 0>;
	124	status = "disabled";
	125	};
	126
11f7135b	127	devbus_cs3: devbus-cs3 {
de1af8d4 EG	128	compatible = "marvell,mvebu-devbus";
	129	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
	130	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
	131	#address-cells = <1>;
	132	#size-cells = <1>;
	133	clocks = <&coreclk 0>;
	134	status = "disabled";
	135	};
	136
467f54b2 GC	137	internal-regs {
	138	compatible = "simple-bus";
	139	#address-cells = <1>;
	140	#size-cells = <1>;
5e12a613 EG	141	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
5e12a613 EG	142
11f7135b	143	rtc: rtc@10300 {
a095b1c7 JC	144	compatible = "marvell,orion-rtc";
	145	reg = <0x10300 0x20>;
	146	interrupts = <50>;
5e12a613	147	};
467f54b2	148
a095b1c7 JC	149	i2c0: i2c@11000 {
	150	compatible = "marvell,mv64xxx-i2c";
	151	#address-cells = <1>;
	152	#size-cells = <0>;
	153	interrupts = <31>;
	154	timeout-ms = <1000>;
	155	clocks = <&coreclk 0>;
	156	status = "disabled";
	157	};
	158
	159	i2c1: i2c@11100 {
	160	compatible = "marvell,mv64xxx-i2c";
	161	#address-cells = <1>;
	162	#size-cells = <0>;
	163	interrupts = <32>;
	164	timeout-ms = <1000>;
	165	clocks = <&coreclk 0>;
	166	status = "disabled";
467f54b2	167	};
b18ea4dc	168
181d9b28	169	uart0: serial@12000 {
b24212fb	170	compatible = "snps,dw-apb-uart";
82a68267	171	reg = <0x12000 0x100>;
9ae6f740 TP	172	reg-shift = <2>;
9ae6f740 TP	173	interrupts = <41>;
e366154f	174	reg-io-width = <1>;
64939dc5	175	clocks = <&coreclk 0>;
9ae6f740	176	status = "disabled";
467f54b2	177	};
181d9b28 AE	178
181d9b28 AE	179	uart1: serial@12100 {
b24212fb	180	compatible = "snps,dw-apb-uart";
82a68267	181	reg = <0x12100 0x100>;
9ae6f740 TP	182	reg-shift = <2>;
9ae6f740 TP	183	interrupts = <42>;
e366154f	184	reg-io-width = <1>;
64939dc5	185	clocks = <&coreclk 0>;
9ae6f740	186	status = "disabled";
467f54b2 GC	187	};
467f54b2 GC	188
4904a82a AE	189	pinctrl: pin-ctrl@18000 {
	190	reg = <0x18000 0x38>;
	191	};
	192
f039dfb5 EG	193	coredivclk: corediv-clock@18740 {
	194	compatible = "marvell,armada-370-corediv-clock";
	195	reg = <0x18740 0xc>;
	196	#clock-cells = <1>;
	197	clocks = <&mainpll>;
	198	clock-output-names = "nand";
	199	};
	200
a095b1c7 JC	201	mbusc: mbus-controller@20000 {
a095b1c7 JC	202	compatible = "marvell,mbus-controller";
8b7dc9d3 TP	203	reg = <0x20000 0x100>, <0x20180 0x20>,
8b7dc9d3 TP	204	<0x20250 0x8>;
a095b1c7 JC	205	};
a095b1c7 JC	206
24c2573b	207	mpic: interrupt-controller@20a00 {
a095b1c7 JC	208	compatible = "marvell,mpic";
	209	#interrupt-cells = <1>;
	210	#size-cells = <1>;
	211	interrupt-controller;
	212	msi-controller;
	213	};
	214
11f7135b	215	coherencyfab: coherency-fabric@20200 {
a095b1c7	216	compatible = "marvell,coherency-fabric";
939ac3cd	217	reg = <0x20200 0xb0>, <0x21010 0x1c>;
a095b1c7 JC	218	};
a095b1c7 JC	219
11f7135b	220	timer: timer@20300 {
467f54b2 GC	221	reg = <0x20300 0x30>, <0x21040 0x30>;
467f54b2 GC	222	interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
467f54b2 GC	223	};
467f54b2 GC	224
11f7135b	225	watchdog: watchdog@20300 {
05afeeb9 EG	226	reg = <0x20300 0x34>, <0x20704 0x4>;
	227	};
	228
11f7135b	229	cpurst: cpurst@20800 {
e72996b8 GC	230	compatible = "marvell,armada-370-cpu-reset";
	231	reg = <0x20800 0x8>;
	232	};
	233
11f7135b	234	pmsu: pmsu@22000 {
b6249d4b GC	235	compatible = "marvell,armada-370-pmsu";
	236	reg = <0x22000 0x1000>;
	237	};
	238
11f7135b	239	usb0: usb@50000 {
a095b1c7 JC	240	compatible = "marvell,orion-ehci";
	241	reg = <0x50000 0x500>;
	242	interrupts = <45>;
467f54b2 GC	243	status = "disabled";
467f54b2 GC	244	};
a6a6de1a	245
11f7135b	246	usb1: usb@51000 {
a095b1c7 JC	247	compatible = "marvell,orion-ehci";
	248	reg = <0x51000 0x500>;
	249	interrupts = <46>;
	250	status = "disabled";
467f54b2	251	};
323c1010	252
be5a9389	253	eth0: ethernet@70000 {
cf8088c5	254	reg = <0x70000 0x4000>;
323c1010	255	interrupts = <8>;
4aa935a2	256	clocks = <&gateclk 4>;
323c1010	257	status = "disabled";
467f54b2	258	};
323c1010	259
1fc21295	260	mdio: mdio@72004 {
a095b1c7 JC	261	#address-cells = <1>;
	262	#size-cells = <0>;
	263	compatible = "marvell,orion-mdio";
	264	reg = <0x72004 0x4>;
a6e03dd4	265	clocks = <&gateclk 4>;
a095b1c7 JC	266	};
a095b1c7 JC	267
be5a9389	268	eth1: ethernet@74000 {
cf8088c5	269	reg = <0x74000 0x4000>;
323c1010	270	interrupts = <10>;
4aa935a2	271	clocks = <&gateclk 3>;
323c1010	272	status = "disabled";
467f54b2 GC	273	};
467f54b2 GC	274
11f7135b	275	sata: sata@a0000 {
9b6d351a	276	compatible = "marvell,armada-370-sata";
a095b1c7 JC	277	reg = <0xa0000 0x5000>;
	278	interrupts = <55>;
	279	clocks = <&gateclk 15>, <&gateclk 30>;
	280	clock-names = "0", "1";
467f54b2 GC	281	status = "disabled";
	282	};
	283
11f7135b	284	nand: nand@d0000 {
a095b1c7 JC	285	compatible = "marvell,armada370-nand";
a095b1c7 JC	286	reg = <0xd0000 0x54>;
467f54b2	287	#address-cells = <1>;
a095b1c7 JC	288	#size-cells = <1>;
	289	interrupts = <113>;
	290	clocks = <&coredivclk 0>;
467f54b2 GC	291	status = "disabled";
	292	};
	293
11f7135b	294	sdio: mvsdio@d4000 {
467f54b2 GC	295	compatible = "marvell,orion-sdio";
	296	reg = <0xd4000 0x200>;
	297	interrupts = <54>;
	298	clocks = <&gateclk 17>;
d87b5fbb SB	299	bus-width = <4>;
	300	cap-sdio-irq;
	301	cap-sd-highspeed;
	302	cap-mmc-highspeed;
467f54b2 GC	303	status = "disabled";
467f54b2 GC	304	};
3d76e1f3	305	};
0160a4b6 SR	306
0160a4b6 SR	307	spi0: spi@10600 {
55877f58 SR	308	reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
	309	<MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
	310	<MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
	311	<MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
	312	<MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
	313	<MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
	314	<MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
	315	<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
	316	<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
0160a4b6 SR	317	#address-cells = <1>;
	318	#size-cells = <0>;
	319	cell-index = <0>;
	320	interrupts = <30>;
	321	clocks = <&coreclk 0>;
	322	status = "disabled";
	323	};
	324
	325	spi1: spi@10680 {
55877f58 SR	326	reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
	327	<MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
	328	<MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
	329	<MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
	330	<MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
	331	<MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
	332	<MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
	333	<MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
	334	<MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
0160a4b6 SR	335	#address-cells = <1>;
	336	#size-cells = <0>;
	337	cell-index = <1>;
	338	interrupts = <92>;
	339	clocks = <&coreclk 0>;
	340	status = "disabled";
	341	};
9ae6f740	342	};
4675cf57 EG	343
	344	clocks {
	345	/* 2 GHz fixed main PLL */
	346	mainpll: mainpll {
	347	compatible = "fixed-clock";
	348	#clock-cells = <0>;
	349	clock-frequency = <2000000000>;
	350	};
	351	};
467f54b2	352	};