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9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 370 and Armada XP SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | * | |
15 | * This file contains the definitions that are common to the Armada | |
16 | * 370 and Armada XP SoC. | |
17 | */ | |
18 | ||
74898364 | 19 | /include/ "skeleton64.dtsi" |
9ae6f740 TP |
20 | |
21 | / { | |
22 | model = "Marvell Armada 370 and XP SoC"; | |
92ece1cd | 23 | compatible = "marvell,armada-370-xp"; |
9ae6f740 TP |
24 | |
25 | cpus { | |
26 | cpu@0 { | |
27 | compatible = "marvell,sheeva-v7"; | |
28 | }; | |
29 | }; | |
30 | ||
9ae6f740 TP |
31 | soc { |
32 | #address-cells = <1>; | |
33 | #size-cells = <1>; | |
34 | compatible = "simple-bus"; | |
35 | interrupt-parent = <&mpic>; | |
8eed481e TP |
36 | ranges = <0 0 0xd0000000 0x0100000 /* internal registers */ |
37 | 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>; | |
9ae6f740 | 38 | |
467f54b2 GC |
39 | internal-regs { |
40 | compatible = "simple-bus"; | |
41 | #address-cells = <1>; | |
42 | #size-cells = <1>; | |
43 | ranges; | |
44 | ||
45 | mpic: interrupt-controller@20000 { | |
82a68267 GC |
46 | compatible = "marvell,mpic"; |
47 | #interrupt-cells = <1>; | |
48 | #size-cells = <1>; | |
49 | interrupt-controller; | |
467f54b2 | 50 | }; |
b18ea4dc | 51 | |
467f54b2 | 52 | coherency-fabric@20200 { |
82a68267 | 53 | compatible = "marvell,coherency-fabric"; |
467f54b2 GC |
54 | reg = <0x20200 0xb0>, <0x21810 0x1c>; |
55 | }; | |
b18ea4dc | 56 | |
467f54b2 | 57 | serial@12000 { |
b24212fb | 58 | compatible = "snps,dw-apb-uart"; |
82a68267 | 59 | reg = <0x12000 0x100>; |
9ae6f740 TP |
60 | reg-shift = <2>; |
61 | interrupts = <41>; | |
e366154f | 62 | reg-io-width = <1>; |
9ae6f740 | 63 | status = "disabled"; |
467f54b2 GC |
64 | }; |
65 | serial@12100 { | |
b24212fb | 66 | compatible = "snps,dw-apb-uart"; |
82a68267 | 67 | reg = <0x12100 0x100>; |
9ae6f740 TP |
68 | reg-shift = <2>; |
69 | interrupts = <42>; | |
e366154f | 70 | reg-io-width = <1>; |
9ae6f740 | 71 | status = "disabled"; |
467f54b2 GC |
72 | }; |
73 | ||
74 | timer@20300 { | |
75 | compatible = "marvell,armada-370-xp-timer"; | |
76 | reg = <0x20300 0x30>, <0x21040 0x30>; | |
77 | interrupts = <37>, <38>, <39>, <40>, <5>, <6>; | |
78 | clocks = <&coreclk 2>; | |
79 | }; | |
80 | ||
81 | sata@a0000 { | |
82 | compatible = "marvell,orion-sata"; | |
911492de | 83 | reg = <0xa0000 0x5000>; |
467f54b2 GC |
84 | interrupts = <55>; |
85 | clocks = <&gateclk 15>, <&gateclk 30>; | |
86 | clock-names = "0", "1"; | |
87 | status = "disabled"; | |
88 | }; | |
a6a6de1a | 89 | |
467f54b2 GC |
90 | mdio { |
91 | #address-cells = <1>; | |
92 | #size-cells = <0>; | |
93 | compatible = "marvell,orion-mdio"; | |
94 | reg = <0x72004 0x4>; | |
95 | }; | |
323c1010 | 96 | |
467f54b2 | 97 | ethernet@70000 { |
323c1010 | 98 | compatible = "marvell,armada-370-neta"; |
82a68267 | 99 | reg = <0x70000 0x2500>; |
323c1010 | 100 | interrupts = <8>; |
4aa935a2 | 101 | clocks = <&gateclk 4>; |
323c1010 | 102 | status = "disabled"; |
467f54b2 | 103 | }; |
323c1010 | 104 | |
467f54b2 | 105 | ethernet@74000 { |
323c1010 | 106 | compatible = "marvell,armada-370-neta"; |
82a68267 | 107 | reg = <0x74000 0x2500>; |
323c1010 | 108 | interrupts = <10>; |
4aa935a2 | 109 | clocks = <&gateclk 3>; |
323c1010 | 110 | status = "disabled"; |
467f54b2 GC |
111 | }; |
112 | ||
113 | i2c0: i2c@11000 { | |
114 | compatible = "marvell,mv64xxx-i2c"; | |
115 | reg = <0x11000 0x20>; | |
116 | #address-cells = <1>; | |
117 | #size-cells = <0>; | |
118 | interrupts = <31>; | |
119 | timeout-ms = <1000>; | |
120 | clocks = <&coreclk 0>; | |
121 | status = "disabled"; | |
122 | }; | |
123 | ||
124 | i2c1: i2c@11100 { | |
125 | compatible = "marvell,mv64xxx-i2c"; | |
126 | reg = <0x11100 0x20>; | |
127 | #address-cells = <1>; | |
128 | #size-cells = <0>; | |
129 | interrupts = <32>; | |
130 | timeout-ms = <1000>; | |
131 | clocks = <&coreclk 0>; | |
132 | status = "disabled"; | |
133 | }; | |
134 | ||
135 | rtc@10300 { | |
136 | compatible = "marvell,orion-rtc"; | |
137 | reg = <0x10300 0x20>; | |
138 | interrupts = <50>; | |
139 | }; | |
140 | ||
141 | mvsdio@d4000 { | |
142 | compatible = "marvell,orion-sdio"; | |
143 | reg = <0xd4000 0x200>; | |
144 | interrupts = <54>; | |
145 | clocks = <&gateclk 17>; | |
146 | status = "disabled"; | |
147 | }; | |
b2bb806f | 148 | |
467f54b2 GC |
149 | usb@50000 { |
150 | compatible = "marvell,orion-ehci"; | |
151 | reg = <0x50000 0x500>; | |
152 | interrupts = <45>; | |
153 | status = "disabled"; | |
154 | }; | |
d5dc035e | 155 | |
467f54b2 GC |
156 | usb@51000 { |
157 | compatible = "marvell,orion-ehci"; | |
158 | reg = <0x51000 0x500>; | |
159 | interrupts = <46>; | |
160 | status = "disabled"; | |
161 | }; | |
162 | ||
163 | spi0: spi@10600 { | |
164 | compatible = "marvell,orion-spi"; | |
165 | reg = <0x10600 0x28>; | |
166 | #address-cells = <1>; | |
167 | #size-cells = <0>; | |
168 | cell-index = <0>; | |
169 | interrupts = <30>; | |
170 | clocks = <&coreclk 0>; | |
171 | status = "disabled"; | |
172 | }; | |
173 | ||
174 | spi1: spi@10680 { | |
175 | compatible = "marvell,orion-spi"; | |
176 | reg = <0x10680 0x28>; | |
177 | #address-cells = <1>; | |
178 | #size-cells = <0>; | |
179 | cell-index = <1>; | |
180 | interrupts = <92>; | |
181 | clocks = <&coreclk 0>; | |
182 | status = "disabled"; | |
183 | }; | |
3d76e1f3 | 184 | |
467f54b2 GC |
185 | devbus-bootcs@10400 { |
186 | compatible = "marvell,mvebu-devbus"; | |
187 | reg = <0x10400 0x8>; | |
188 | #address-cells = <1>; | |
189 | #size-cells = <1>; | |
190 | clocks = <&coreclk 0>; | |
191 | status = "disabled"; | |
192 | }; | |
3d76e1f3 | 193 | |
467f54b2 GC |
194 | devbus-cs0@10408 { |
195 | compatible = "marvell,mvebu-devbus"; | |
196 | reg = <0x10408 0x8>; | |
197 | #address-cells = <1>; | |
198 | #size-cells = <1>; | |
199 | clocks = <&coreclk 0>; | |
200 | status = "disabled"; | |
201 | }; | |
3d76e1f3 | 202 | |
467f54b2 GC |
203 | devbus-cs1@10410 { |
204 | compatible = "marvell,mvebu-devbus"; | |
205 | reg = <0x10410 0x8>; | |
206 | #address-cells = <1>; | |
207 | #size-cells = <1>; | |
208 | clocks = <&coreclk 0>; | |
209 | status = "disabled"; | |
210 | }; | |
3d76e1f3 | 211 | |
467f54b2 GC |
212 | devbus-cs2@10418 { |
213 | compatible = "marvell,mvebu-devbus"; | |
214 | reg = <0x10418 0x8>; | |
215 | #address-cells = <1>; | |
216 | #size-cells = <1>; | |
217 | clocks = <&coreclk 0>; | |
218 | status = "disabled"; | |
219 | }; | |
3d76e1f3 | 220 | |
467f54b2 GC |
221 | devbus-cs3@10420 { |
222 | compatible = "marvell,mvebu-devbus"; | |
223 | reg = <0x10420 0x8>; | |
224 | #address-cells = <1>; | |
225 | #size-cells = <1>; | |
226 | clocks = <&coreclk 0>; | |
227 | status = "disabled"; | |
228 | }; | |
3d76e1f3 | 229 | }; |
9ae6f740 | 230 | }; |
467f54b2 | 231 | }; |