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9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 370 family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | * | |
14 | * Contains definitions specific to the Armada 370 SoC that are not | |
15 | * common to all Armada SoCs. | |
16 | */ | |
17 | ||
18 | /include/ "armada-370-xp.dtsi" | |
74898364 | 19 | /include/ "skeleton.dtsi" |
9ae6f740 TP |
20 | |
21 | / { | |
22 | model = "Marvell Armada 370 family SoC"; | |
23 | compatible = "marvell,armada370", "marvell,armada-370-xp"; | |
24 | ||
397d59f3 TP |
25 | aliases { |
26 | gpio0 = &gpio0; | |
27 | gpio1 = &gpio1; | |
28 | gpio2 = &gpio2; | |
29 | }; | |
30 | ||
9ae6f740 | 31 | soc { |
8eed481e TP |
32 | ranges = <0 0xd0000000 0x0100000 /* internal registers */ |
33 | 0xe0000000 0xe0000000 0x8100000 /* PCIe */>; | |
467f54b2 GC |
34 | internal-regs { |
35 | system-controller@18200 { | |
9ae6f740 | 36 | compatible = "marvell,armada-370-xp-system-controller"; |
82a68267 | 37 | reg = <0x18200 0x100>; |
fa1b21d1 TP |
38 | }; |
39 | ||
467f54b2 GC |
40 | L2: l2-cache { |
41 | compatible = "marvell,aurora-outer-cache"; | |
489e138e | 42 | reg = <0x08000 0x1000>; |
467f54b2 GC |
43 | cache-id-part = <0x100>; |
44 | wt-override; | |
fa1b21d1 | 45 | }; |
879d68a4 | 46 | |
be3cd268 | 47 | interrupt-controller@20000 { |
467f54b2 | 48 | reg = <0x20a00 0x1d0>, <0x21870 0x58>; |
879d68a4 | 49 | }; |
397d59f3 | 50 | |
467f54b2 GC |
51 | pinctrl { |
52 | compatible = "marvell,mv88f6710-pinctrl"; | |
53 | reg = <0x18000 0x38>; | |
54 | ||
55 | sdio_pins1: sdio-pins1 { | |
56 | marvell,pins = "mpp9", "mpp11", "mpp12", | |
57 | "mpp13", "mpp14", "mpp15"; | |
58 | marvell,function = "sd0"; | |
59 | }; | |
60 | ||
61 | sdio_pins2: sdio-pins2 { | |
62 | marvell,pins = "mpp47", "mpp48", "mpp49", | |
63 | "mpp50", "mpp51", "mpp52"; | |
64 | marvell,function = "sd0"; | |
65 | }; | |
66 | ||
67 | sdio_pins3: sdio-pins3 { | |
68 | marvell,pins = "mpp48", "mpp49", "mpp50", | |
69 | "mpp51", "mpp52", "mpp53"; | |
70 | marvell,function = "sd0"; | |
71 | }; | |
0122eee8 | 72 | }; |
0122eee8 | 73 | |
467f54b2 GC |
74 | gpio0: gpio@18100 { |
75 | compatible = "marvell,orion-gpio"; | |
76 | reg = <0x18100 0x40>; | |
77 | ngpios = <32>; | |
78 | gpio-controller; | |
79 | #gpio-cells = <2>; | |
80 | interrupt-controller; | |
81 | #interrupts-cells = <2>; | |
82 | interrupts = <82>, <83>, <84>, <85>; | |
0122eee8 | 83 | }; |
b2bb806f | 84 | |
467f54b2 GC |
85 | gpio1: gpio@18140 { |
86 | compatible = "marvell,orion-gpio"; | |
87 | reg = <0x18140 0x40>; | |
88 | ngpios = <32>; | |
89 | gpio-controller; | |
90 | #gpio-cells = <2>; | |
91 | interrupt-controller; | |
92 | #interrupts-cells = <2>; | |
93 | interrupts = <87>, <88>, <89>, <90>; | |
94 | }; | |
b2bb806f | 95 | |
467f54b2 GC |
96 | gpio2: gpio@18180 { |
97 | compatible = "marvell,orion-gpio"; | |
98 | reg = <0x18180 0x40>; | |
99 | ngpios = <2>; | |
100 | gpio-controller; | |
101 | #gpio-cells = <2>; | |
102 | interrupt-controller; | |
103 | #interrupts-cells = <2>; | |
104 | interrupts = <91>; | |
105 | }; | |
a09a0b7c | 106 | |
467f54b2 GC |
107 | coreclk: mvebu-sar@18230 { |
108 | compatible = "marvell,armada-370-core-clock"; | |
109 | reg = <0x18230 0x08>; | |
110 | #clock-cells = <1>; | |
111 | }; | |
a09a0b7c | 112 | |
467f54b2 GC |
113 | gateclk: clock-gating-control@18220 { |
114 | compatible = "marvell,armada-370-gating-clock"; | |
115 | reg = <0x18220 0x4>; | |
116 | clocks = <&coreclk 0>; | |
117 | #clock-cells = <1>; | |
118 | }; | |
a09a0b7c | 119 | |
467f54b2 GC |
120 | xor@60800 { |
121 | compatible = "marvell,orion-xor"; | |
122 | reg = <0x60800 0x100 | |
123 | 0x60A00 0x100>; | |
124 | status = "okay"; | |
125 | ||
126 | xor00 { | |
127 | interrupts = <51>; | |
128 | dmacap,memcpy; | |
129 | dmacap,xor; | |
130 | }; | |
131 | xor01 { | |
132 | interrupts = <52>; | |
133 | dmacap,memcpy; | |
134 | dmacap,xor; | |
135 | dmacap,memset; | |
136 | }; | |
137 | }; | |
a09a0b7c | 138 | |
467f54b2 GC |
139 | xor@60900 { |
140 | compatible = "marvell,orion-xor"; | |
141 | reg = <0x60900 0x100 | |
142 | 0x60b00 0x100>; | |
143 | status = "okay"; | |
144 | ||
145 | xor10 { | |
146 | interrupts = <94>; | |
147 | dmacap,memcpy; | |
148 | dmacap,xor; | |
149 | }; | |
150 | xor11 { | |
151 | interrupts = <95>; | |
152 | dmacap,memcpy; | |
153 | dmacap,xor; | |
154 | dmacap,memset; | |
155 | }; | |
156 | }; | |
a09a0b7c | 157 | |
467f54b2 GC |
158 | usb@50000 { |
159 | clocks = <&coreclk 0>; | |
160 | }; | |
a09a0b7c | 161 | |
467f54b2 GC |
162 | usb@51000 { |
163 | clocks = <&coreclk 0>; | |
164 | }; | |
a09a0b7c | 165 | |
467f54b2 GC |
166 | thermal@18300 { |
167 | compatible = "marvell,armada370-thermal"; | |
168 | reg = <0x18300 0x4 | |
169 | 0x18304 0x4>; | |
170 | status = "okay"; | |
a09a0b7c TP |
171 | }; |
172 | ||
467f54b2 GC |
173 | pcie-controller { |
174 | compatible = "marvell,armada-370-pcie"; | |
175 | status = "disabled"; | |
a09a0b7c | 176 | device_type = "pci"; |
467f54b2 | 177 | |
a09a0b7c TP |
178 | #address-cells = <3>; |
179 | #size-cells = <2>; | |
467f54b2 GC |
180 | |
181 | bus-range = <0x00 0xff>; | |
182 | ||
467f54b2 GC |
183 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ |
184 | 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ | |
185 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | |
186 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | |
187 | ||
188 | pcie@1,0 { | |
189 | device_type = "pci"; | |
190 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
191 | reg = <0x0800 0 0 0 0>; | |
192 | #address-cells = <3>; | |
193 | #size-cells = <2>; | |
194 | #interrupt-cells = <1>; | |
195 | ranges; | |
196 | interrupt-map-mask = <0 0 0 0>; | |
197 | interrupt-map = <0 0 0 0 &mpic 58>; | |
198 | marvell,pcie-port = <0>; | |
199 | marvell,pcie-lane = <0>; | |
200 | clocks = <&gateclk 5>; | |
201 | status = "disabled"; | |
202 | }; | |
203 | ||
204 | pcie@2,0 { | |
205 | device_type = "pci"; | |
206 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | |
207 | reg = <0x1000 0 0 0 0>; | |
208 | #address-cells = <3>; | |
209 | #size-cells = <2>; | |
210 | #interrupt-cells = <1>; | |
211 | ranges; | |
212 | interrupt-map-mask = <0 0 0 0>; | |
213 | interrupt-map = <0 0 0 0 &mpic 62>; | |
214 | marvell,pcie-port = <1>; | |
215 | marvell,pcie-lane = <0>; | |
216 | clocks = <&gateclk 9>; | |
217 | status = "disabled"; | |
218 | }; | |
a09a0b7c TP |
219 | }; |
220 | }; | |
9ae6f740 TP |
221 | }; |
222 | }; |